paul@33 | 1 | /* |
paul@229 | 2 | * U-Boot and jz4740 LCD controller definitions. |
paul@33 | 3 | * |
paul@38 | 4 | * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
paul@33 | 5 | * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. |
paul@229 | 6 | * Copyright (C) 2009 Qi Hardware Inc. |
paul@229 | 7 | * Author: Xiangfu Liu <xiangfu@sharism.cc> |
paul@38 | 8 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
paul@217 | 9 | * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> |
paul@33 | 10 | * |
paul@33 | 11 | * This program is free software; you can redistribute it and/or |
paul@33 | 12 | * modify it under the terms of the GNU General Public License as |
paul@33 | 13 | * published by the Free Software Foundation; either version 2 of |
paul@33 | 14 | * the License, or (at your option) any later version. |
paul@33 | 15 | * |
paul@33 | 16 | * This program is distributed in the hope that it will be useful, |
paul@33 | 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@33 | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@33 | 19 | * GNU General Public License for more details. |
paul@33 | 20 | * |
paul@33 | 21 | * You should have received a copy of the GNU General Public License |
paul@33 | 22 | * along with this program; if not, write to the Free Software |
paul@42 | 23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@42 | 24 | * Boston, MA 02110-1301, USA |
paul@33 | 25 | */ |
paul@33 | 26 | |
paul@33 | 27 | #ifndef __JZLCD_H__ |
paul@33 | 28 | #define __JZLCD_H__ |
paul@33 | 29 | |
paul@217 | 30 | #include <stdint.h> |
paul@106 | 31 | |
paul@223 | 32 | /* Framebuffer characteristics. */ |
paul@223 | 33 | |
paul@33 | 34 | struct jzfb_info { |
paul@217 | 35 | uint32_t cfg; /* panel mode and pin usage etc. */ |
paul@223 | 36 | uint16_t w; /* display width in pixels */ |
paul@223 | 37 | uint16_t h; /* display height in pixels */ |
paul@223 | 38 | uint8_t bpp; /* bits per pixel */ |
paul@223 | 39 | uint32_t fclk; /* frame clock */ |
paul@223 | 40 | uint32_t hsw; /* hsync width, in pixel clock */ |
paul@217 | 41 | uint32_t vsw; /* vsync width, in line count */ |
paul@223 | 42 | uint32_t elw; /* end of line, in pixel clock */ |
paul@223 | 43 | uint32_t blw; /* begin of line, in pixel clock */ |
paul@217 | 44 | uint32_t efw; /* end of frame, in line count */ |
paul@217 | 45 | uint32_t bfw; /* begin of frame, in line count */ |
paul@33 | 46 | }; |
paul@33 | 47 | |
paul@223 | 48 | /* LCD controller stucture for jz4740. */ |
paul@223 | 49 | |
paul@38 | 50 | struct jz_fb_dma_descriptor { |
paul@223 | 51 | struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */ |
paul@223 | 52 | uint32_t fsadr; /* frame source address register */ |
paul@223 | 53 | uint32_t fidr; /* frame identifier register */ |
paul@223 | 54 | uint32_t ldcmd; /* command register */ |
paul@38 | 55 | }; |
paul@38 | 56 | |
paul@223 | 57 | /* Framebuffer and controller memory information. */ |
paul@223 | 58 | |
paul@221 | 59 | struct jz_mem_info { |
paul@38 | 60 | |
paul@223 | 61 | /* DMA descriptor references (updated for transfers). */ |
paul@223 | 62 | |
paul@224 | 63 | struct jz_fb_dma_descriptor *fdadr0; /* physical address of frame descriptor */ |
paul@224 | 64 | struct jz_fb_dma_descriptor *fdadr1; /* physical address of frame/palette descriptor */ |
paul@38 | 65 | |
paul@223 | 66 | /* DMA descriptor references (indicating allocated regions). */ |
paul@223 | 67 | |
paul@224 | 68 | struct jz_fb_dma_descriptor *dmadesc_fb0; |
paul@224 | 69 | struct jz_fb_dma_descriptor *dmadesc_fb1; |
paul@38 | 70 | struct jz_fb_dma_descriptor *dmadesc_palette; |
paul@93 | 71 | |
paul@229 | 72 | /* Region addresses. */ |
paul@229 | 73 | |
paul@223 | 74 | uint32_t screen; /* address of first frame buffer (base of memory used) */ |
paul@217 | 75 | uint32_t palette; /* address of palette memory */ |
paul@223 | 76 | uint32_t total; /* total memory used */ |
paul@38 | 77 | }; |
paul@38 | 78 | |
paul@223 | 79 | /* Display characteristics and memory resources. */ |
paul@223 | 80 | |
paul@38 | 81 | typedef struct vidinfo { |
paul@223 | 82 | struct jzfb_info *jz_fb; /* framebuffer and panel properties */ |
paul@223 | 83 | struct jz_mem_info jz_mem; /* framebuffer memory information */ |
paul@223 | 84 | void *lcd; /* address of LCD controller registers */ |
paul@38 | 85 | } vidinfo_t; |
paul@38 | 86 | |
paul@229 | 87 | |
paul@229 | 88 | |
paul@227 | 89 | /* Public functions. */ |
paul@227 | 90 | |
paul@227 | 91 | uint32_t jz4740_lcd_get_total_size(vidinfo_t *vid); |
paul@227 | 92 | uint32_t jz4740_lcd_get_pixel_clock(vidinfo_t *vid); |
paul@227 | 93 | void jz4740_lcd_ctrl_init(void *lcd_base, void *fb_vaddr, vidinfo_t *vid); |
paul@227 | 94 | void jz4740_lcd_hw_init(vidinfo_t *vid); |
paul@227 | 95 | void jz4740_lcd_dma_init(vidinfo_t *vid); |
paul@229 | 96 | void jz4740_lcd_set_bpp(uint8_t bpp, vidinfo_t *vid); |
paul@229 | 97 | void jz4740_lcd_enable(vidinfo_t *vid); |
paul@229 | 98 | void jz4740_lcd_disable(vidinfo_t *vid); |
paul@229 | 99 | void jz4740_lcd_quick_disable(vidinfo_t *vid); |
paul@229 | 100 | |
paul@229 | 101 | |
paul@227 | 102 | |
paul@100 | 103 | /* Alignment/rounding macros. */ |
paul@100 | 104 | |
paul@100 | 105 | #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) |
paul@100 | 106 | #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) |
paul@100 | 107 | |
paul@229 | 108 | /* Display device mode select (LCD_CFG.MODE). */ |
paul@38 | 109 | |
paul@33 | 110 | #define MODE_MASK 0x0f |
paul@33 | 111 | #define MODE_TFT_GEN 0x00 |
paul@33 | 112 | #define MODE_TFT_SHARP 0x01 |
paul@33 | 113 | #define MODE_TFT_CASIO 0x02 |
paul@33 | 114 | #define MODE_TFT_SAMSUNG 0x03 |
paul@33 | 115 | #define MODE_CCIR656_NONINT 0x04 |
paul@33 | 116 | #define MODE_CCIR656_INT 0x05 |
paul@33 | 117 | #define MODE_STN_COLOR_SINGLE 0x08 |
paul@33 | 118 | #define MODE_STN_MONO_SINGLE 0x09 |
paul@33 | 119 | #define MODE_STN_COLOR_DUAL 0x0a |
paul@33 | 120 | #define MODE_STN_MONO_DUAL 0x0b |
paul@33 | 121 | #define MODE_8BIT_SERIAL_TFT 0x0c |
paul@33 | 122 | |
paul@229 | 123 | /* 16-bit or 18-bit TFT panel selection (LCD_CFG.18/16). */ |
paul@229 | 124 | |
paul@33 | 125 | #define MODE_TFT_18BIT (1<<7) |
paul@33 | 126 | |
paul@229 | 127 | /* STN pin utilisation (LCD_CFG.PDW). */ |
paul@229 | 128 | |
paul@229 | 129 | #define STN_DAT_PIN1 (0x00 << 4) |
paul@229 | 130 | #define STN_DAT_PIN2 (0x01 << 4) |
paul@229 | 131 | #define STN_DAT_PIN4 (0x02 << 4) |
paul@229 | 132 | #define STN_DAT_PIN8 (0x03 << 4) |
paul@229 | 133 | #define STN_DAT_PINMASK STN_DAT_PIN8 |
paul@229 | 134 | |
paul@229 | 135 | /* Pin reset states (LCD_CFG). */ |
paul@33 | 136 | |
paul@229 | 137 | #define STFT_PSHI (1 << 15) |
paul@229 | 138 | #define STFT_CLSHI (1 << 14) |
paul@229 | 139 | #define STFT_SPLHI (1 << 13) |
paul@229 | 140 | #define STFT_REVHI (1 << 12) |
paul@33 | 141 | |
paul@229 | 142 | /* Sync direction (LCD_CFG.SYNDIR). */ |
paul@229 | 143 | |
paul@229 | 144 | #define SYNC_MASTER (0 << 16) |
paul@229 | 145 | #define SYNC_SLAVE (1 << 16) |
paul@229 | 146 | |
paul@229 | 147 | /* Data enable polarity (LCD_CFG.DEP). */ |
paul@33 | 148 | |
paul@229 | 149 | #define DE_P (0 << 9) |
paul@229 | 150 | #define DE_N (1 << 9) |
paul@229 | 151 | |
paul@229 | 152 | /* Pixel clock polarity (LCD_CFG.PCP). */ |
paul@33 | 153 | |
paul@229 | 154 | #define PCLK_P (0 << 10) |
paul@229 | 155 | #define PCLK_N (1 << 10) |
paul@33 | 156 | |
paul@229 | 157 | /* Horizontal sync polarity (LCD_CFG.HSP). */ |
paul@33 | 158 | |
paul@229 | 159 | #define HSYNC_P (0 << 11) |
paul@229 | 160 | #define HSYNC_N (1 << 11) |
paul@229 | 161 | |
paul@229 | 162 | /* Vertical sync polarity (LCD_CFG.VSP). */ |
paul@33 | 163 | |
paul@229 | 164 | #define VSYNC_P (0 << 8) |
paul@229 | 165 | #define VSYNC_N (1 << 8) |
paul@33 | 166 | |
paul@229 | 167 | /* Inverse output data (LCD_CFG.INVDAT). */ |
paul@225 | 168 | |
paul@229 | 169 | #define DATA_NORMAL (0 << 17) |
paul@229 | 170 | #define DATA_INVERSE (1 << 17) |
paul@225 | 171 | |
paul@225 | 172 | /* Register offsets. */ |
paul@225 | 173 | |
paul@225 | 174 | #define LCD_CFG 0x00 /* LCD Configure Register */ |
paul@225 | 175 | #define LCD_VSYNC 0x04 /* Vertical Synchronize Register */ |
paul@225 | 176 | #define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */ |
paul@225 | 177 | #define LCD_VAT 0x0c /* Virtual Area Setting Register */ |
paul@225 | 178 | #define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */ |
paul@225 | 179 | #define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */ |
paul@225 | 180 | #define LCD_PS 0x18 /* PS Signal Setting */ |
paul@225 | 181 | #define LCD_CLS 0x1c /* CLS Signal Setting */ |
paul@225 | 182 | #define LCD_SPL 0x20 /* SPL Signal Setting */ |
paul@225 | 183 | #define LCD_REV 0x24 /* REV Signal Setting */ |
paul@225 | 184 | #define LCD_CTRL 0x30 /* LCD Control Register */ |
paul@225 | 185 | #define LCD_STATE 0x34 /* LCD Status Register */ |
paul@225 | 186 | #define LCD_IID 0x38 /* Interrupt ID Register */ |
paul@225 | 187 | #define LCD_DA0 0x40 /* Descriptor Address Register 0 */ |
paul@225 | 188 | #define LCD_SA0 0x44 /* Source Address Register 0 */ |
paul@225 | 189 | #define LCD_FID0 0x48 /* Frame ID Register 0 */ |
paul@225 | 190 | #define LCD_CMD0 0x4c /* DMA Command Register 0 */ |
paul@225 | 191 | #define LCD_DA1 0x50 /* Descriptor Address Register 1 */ |
paul@225 | 192 | #define LCD_SA1 0x54 /* Source Address Register 1 */ |
paul@225 | 193 | #define LCD_FID1 0x58 /* Frame ID Register 1 */ |
paul@225 | 194 | #define LCD_CMD1 0x5c /* DMA Command Register 1 */ |
paul@225 | 195 | |
paul@224 | 196 | /* Palette buffer (LCD_CMDx.PAL). */ |
paul@224 | 197 | |
paul@224 | 198 | #define LCD_CMD_PAL (1 << 28) |
paul@224 | 199 | |
paul@33 | 200 | #endif /* __JZLCD_H__ */ |