| paul@0 | 1 | /* |
| paul@0 | 2 | * Include file for Ingenic Semiconductor's JZ4740 CPU. |
| paul@0 | 3 | * |
| paul@0 | 4 | * Copyright 2009 (C) Qi Hardware Inc., |
| paul@0 | 5 | * Author: Xiangfu Liu <xiangfu@sharism.cc> |
| paul@0 | 6 | * |
| paul@0 | 7 | * This program is free software; you can redistribute it and/or |
| paul@0 | 8 | * modify it under the terms of the GNU General Public License |
| paul@0 | 9 | * version 3 as published by the Free Software Foundation. |
| paul@0 | 10 | * |
| paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
| paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| paul@0 | 14 | * GNU General Public License for more details. |
| paul@0 | 15 | * |
| paul@0 | 16 | * You should have received a copy of the GNU General Public License |
| paul@0 | 17 | * along with this program; if not, write to the Free Software |
| paul@0 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| paul@0 | 19 | * Boston, MA 02110-1301, USA |
| paul@0 | 20 | */ |
| paul@0 | 21 | #ifndef __JZ4740_H__ |
| paul@0 | 22 | #define __JZ4740_H__ |
| paul@0 | 23 | |
| paul@0 | 24 | #include "xburst_types.h" |
| paul@0 | 25 | |
| paul@1 | 26 | /* Boot ROM Specification */ |
| paul@0 | 27 | /* NOR Boot config */ |
| paul@0 | 28 | #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ |
| paul@0 | 29 | #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ |
| paul@0 | 30 | #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ |
| paul@0 | 31 | |
| paul@0 | 32 | /* NAND Boot config */ |
| paul@0 | 33 | #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ |
| paul@0 | 34 | #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ |
| paul@0 | 35 | #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ |
| paul@0 | 36 | #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ |
| paul@0 | 37 | |
| paul@0 | 38 | |
| paul@0 | 39 | /* Register Definitions */ |
| paul@0 | 40 | #define CPM_BASE 0xB0000000 |
| paul@0 | 41 | #define INTC_BASE 0xB0001000 |
| paul@0 | 42 | #define TCU_BASE 0xB0002000 |
| paul@0 | 43 | #define WDT_BASE 0xB0002000 |
| paul@0 | 44 | #define RTC_BASE 0xB0003000 |
| paul@0 | 45 | #define GPIO_BASE 0xB0010000 |
| paul@0 | 46 | #define AIC_BASE 0xB0020000 |
| paul@0 | 47 | #define ICDC_BASE 0xB0020000 |
| paul@0 | 48 | #define MSC_BASE 0xB0021000 |
| paul@0 | 49 | #define UART0_BASE 0xB0030000 |
| paul@0 | 50 | #define I2C_BASE 0xB0042000 |
| paul@0 | 51 | #define SSI_BASE 0xB0043000 |
| paul@0 | 52 | #define SADC_BASE 0xB0070000 |
| paul@0 | 53 | #define EMC_BASE 0xB3010000 |
| paul@0 | 54 | #define DMAC_BASE 0xB3020000 |
| paul@0 | 55 | #define UHC_BASE 0xB3030000 |
| paul@0 | 56 | #define UDC_BASE 0xB3040000 |
| paul@0 | 57 | #define LCD_BASE 0xB3050000 |
| paul@0 | 58 | #define SLCD_BASE 0xB3050000 |
| paul@0 | 59 | #define CIM_BASE 0xB3060000 |
| paul@0 | 60 | #define ETH_BASE 0xB3100000 |
| paul@0 | 61 | |
| paul@0 | 62 | |
| paul@1 | 63 | /* |
| paul@0 | 64 | * INTC (Interrupt Controller) |
| paul@1 | 65 | */ |
| paul@0 | 66 | #define INTC_ISR (INTC_BASE + 0x00) |
| paul@0 | 67 | #define INTC_IMR (INTC_BASE + 0x04) |
| paul@0 | 68 | #define INTC_IMSR (INTC_BASE + 0x08) |
| paul@0 | 69 | #define INTC_IMCR (INTC_BASE + 0x0c) |
| paul@0 | 70 | #define INTC_IPR (INTC_BASE + 0x10) |
| paul@0 | 71 | |
| paul@0 | 72 | #define REG_INTC_ISR REG32(INTC_ISR) |
| paul@0 | 73 | #define REG_INTC_IMR REG32(INTC_IMR) |
| paul@0 | 74 | #define REG_INTC_IMSR REG32(INTC_IMSR) |
| paul@0 | 75 | #define REG_INTC_IMCR REG32(INTC_IMCR) |
| paul@0 | 76 | #define REG_INTC_IPR REG32(INTC_IPR) |
| paul@0 | 77 | |
| paul@0 | 78 | /* 1st-level interrupts */ |
| paul@0 | 79 | #define IRQ_I2C 1 |
| paul@0 | 80 | #define IRQ_UHC 3 |
| paul@0 | 81 | #define IRQ_UART0 9 |
| paul@0 | 82 | #define IRQ_SADC 12 |
| paul@0 | 83 | #define IRQ_MSC 14 |
| paul@0 | 84 | #define IRQ_RTC 15 |
| paul@0 | 85 | #define IRQ_SSI 16 |
| paul@0 | 86 | #define IRQ_CIM 17 |
| paul@0 | 87 | #define IRQ_AIC 18 |
| paul@0 | 88 | #define IRQ_ETH 19 |
| paul@0 | 89 | #define IRQ_DMAC 20 |
| paul@0 | 90 | #define IRQ_TCU2 21 |
| paul@0 | 91 | #define IRQ_TCU1 22 |
| paul@0 | 92 | #define IRQ_TCU0 23 |
| paul@0 | 93 | #define IRQ_UDC 24 |
| paul@0 | 94 | #define IRQ_GPIO3 25 |
| paul@0 | 95 | #define IRQ_GPIO2 26 |
| paul@0 | 96 | #define IRQ_GPIO1 27 |
| paul@0 | 97 | #define IRQ_GPIO0 28 |
| paul@0 | 98 | #define IRQ_IPU 29 |
| paul@0 | 99 | #define IRQ_LCD 30 |
| paul@0 | 100 | |
| paul@0 | 101 | /* 2nd-level interrupts */ |
| paul@0 | 102 | #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ |
| paul@0 | 103 | #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ |
| paul@0 | 104 | |
| paul@0 | 105 | |
| paul@1 | 106 | /* |
| paul@0 | 107 | * RTC |
| paul@1 | 108 | */ |
| paul@0 | 109 | #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ |
| paul@0 | 110 | #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ |
| paul@0 | 111 | #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ |
| paul@0 | 112 | #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ |
| paul@0 | 113 | |
| paul@0 | 114 | #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ |
| paul@0 | 115 | #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ |
| paul@0 | 116 | #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ |
| paul@0 | 117 | #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ |
| paul@0 | 118 | #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ |
| paul@0 | 119 | #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ |
| paul@0 | 120 | |
| paul@0 | 121 | #define REG_RTC_RCR REG32(RTC_RCR) |
| paul@0 | 122 | #define REG_RTC_RSR REG32(RTC_RSR) |
| paul@0 | 123 | #define REG_RTC_RSAR REG32(RTC_RSAR) |
| paul@0 | 124 | #define REG_RTC_RGR REG32(RTC_RGR) |
| paul@0 | 125 | #define REG_RTC_HCR REG32(RTC_HCR) |
| paul@0 | 126 | #define REG_RTC_HWFCR REG32(RTC_HWFCR) |
| paul@0 | 127 | #define REG_RTC_HRCR REG32(RTC_HRCR) |
| paul@0 | 128 | #define REG_RTC_HWCR REG32(RTC_HWCR) |
| paul@0 | 129 | #define REG_RTC_HWRSR REG32(RTC_HWRSR) |
| paul@0 | 130 | #define REG_RTC_HSPR REG32(RTC_HSPR) |
| paul@0 | 131 | |
| paul@0 | 132 | /* RTC Control Register */ |
| paul@0 | 133 | #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ |
| paul@0 | 134 | #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ |
| paul@0 | 135 | #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ |
| paul@0 | 136 | #define RTC_RCR_AF (1 << 4) /* Alarm Flag */ |
| paul@0 | 137 | #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ |
| paul@0 | 138 | #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ |
| paul@0 | 139 | #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ |
| paul@0 | 140 | |
| paul@0 | 141 | /* RTC Regulator Register */ |
| paul@0 | 142 | #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ |
| paul@0 | 143 | #define RTC_RGR_ADJC_BIT 16 |
| paul@0 | 144 | #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) |
| paul@0 | 145 | #define RTC_RGR_NC1HZ_BIT 0 |
| paul@0 | 146 | #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) |
| paul@0 | 147 | |
| paul@0 | 148 | /* Hibernate Control Register */ |
| paul@0 | 149 | #define RTC_HCR_PD (1 << 0) /* Power Down */ |
| paul@0 | 150 | |
| paul@0 | 151 | /* Hibernate Wakeup Filter Counter Register */ |
| paul@0 | 152 | #define RTC_HWFCR_BIT 5 |
| paul@0 | 153 | #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) |
| paul@0 | 154 | |
| paul@0 | 155 | /* Hibernate Reset Counter Register */ |
| paul@0 | 156 | #define RTC_HRCR_BIT 5 |
| paul@0 | 157 | #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) |
| paul@0 | 158 | |
| paul@0 | 159 | /* Hibernate Wakeup Control Register */ |
| paul@0 | 160 | #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ |
| paul@0 | 161 | |
| paul@0 | 162 | /* Hibernate Wakeup Status Register */ |
| paul@0 | 163 | #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ |
| paul@0 | 164 | #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ |
| paul@0 | 165 | #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ |
| paul@0 | 166 | #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ |
| paul@0 | 167 | |
| paul@0 | 168 | /************************************************************************* |
| paul@0 | 169 | * CPM (Clock reset and Power control Management) |
| paul@0 | 170 | *************************************************************************/ |
| paul@0 | 171 | #define CPM_CPCCR (CPM_BASE+0x00) |
| paul@0 | 172 | #define CPM_CPPCR (CPM_BASE+0x10) |
| paul@0 | 173 | #define CPM_I2SCDR (CPM_BASE+0x60) |
| paul@0 | 174 | #define CPM_LPCDR (CPM_BASE+0x64) |
| paul@0 | 175 | #define CPM_MSCCDR (CPM_BASE+0x68) |
| paul@0 | 176 | #define CPM_UHCCDR (CPM_BASE+0x6C) |
| paul@0 | 177 | |
| paul@0 | 178 | #define CPM_LCR (CPM_BASE+0x04) |
| paul@0 | 179 | #define CPM_CLKGR (CPM_BASE+0x20) |
| paul@0 | 180 | #define CPM_SCR (CPM_BASE+0x24) |
| paul@0 | 181 | |
| paul@0 | 182 | #define CPM_HCR (CPM_BASE+0x30) |
| paul@0 | 183 | #define CPM_HWFCR (CPM_BASE+0x34) |
| paul@0 | 184 | #define CPM_HRCR (CPM_BASE+0x38) |
| paul@0 | 185 | #define CPM_HWCR (CPM_BASE+0x3c) |
| paul@0 | 186 | #define CPM_HWSR (CPM_BASE+0x40) |
| paul@0 | 187 | #define CPM_HSPR (CPM_BASE+0x44) |
| paul@0 | 188 | |
| paul@0 | 189 | #define CPM_RSR (CPM_BASE+0x08) |
| paul@0 | 190 | |
| paul@0 | 191 | |
| paul@0 | 192 | #define REG_CPM_CPCCR REG32(CPM_CPCCR) |
| paul@0 | 193 | #define REG_CPM_CPPCR REG32(CPM_CPPCR) |
| paul@0 | 194 | #define REG_CPM_I2SCDR REG32(CPM_I2SCDR) |
| paul@0 | 195 | #define REG_CPM_LPCDR REG32(CPM_LPCDR) |
| paul@0 | 196 | #define REG_CPM_MSCCDR REG32(CPM_MSCCDR) |
| paul@0 | 197 | #define REG_CPM_UHCCDR REG32(CPM_UHCCDR) |
| paul@0 | 198 | |
| paul@0 | 199 | #define REG_CPM_LCR REG32(CPM_LCR) |
| paul@0 | 200 | #define REG_CPM_CLKGR REG32(CPM_CLKGR) |
| paul@0 | 201 | #define REG_CPM_SCR REG32(CPM_SCR) |
| paul@0 | 202 | #define REG_CPM_HCR REG32(CPM_HCR) |
| paul@0 | 203 | #define REG_CPM_HWFCR REG32(CPM_HWFCR) |
| paul@0 | 204 | #define REG_CPM_HRCR REG32(CPM_HRCR) |
| paul@0 | 205 | #define REG_CPM_HWCR REG32(CPM_HWCR) |
| paul@0 | 206 | #define REG_CPM_HWSR REG32(CPM_HWSR) |
| paul@0 | 207 | #define REG_CPM_HSPR REG32(CPM_HSPR) |
| paul@0 | 208 | |
| paul@0 | 209 | #define REG_CPM_RSR REG32(CPM_RSR) |
| paul@0 | 210 | |
| paul@0 | 211 | |
| paul@0 | 212 | /* Clock Control Register */ |
| paul@0 | 213 | #define CPM_CPCCR_I2CS (1 << 31) |
| paul@0 | 214 | #define CPM_CPCCR_CLKOEN (1 << 30) |
| paul@0 | 215 | #define CPM_CPCCR_UCS (1 << 29) |
| paul@0 | 216 | #define CPM_CPCCR_UDIV_BIT 23 |
| paul@0 | 217 | #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) |
| paul@0 | 218 | #define CPM_CPCCR_CE (1 << 22) |
| paul@0 | 219 | #define CPM_CPCCR_PCS (1 << 21) |
| paul@0 | 220 | #define CPM_CPCCR_LDIV_BIT 16 |
| paul@0 | 221 | #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) |
| paul@0 | 222 | #define CPM_CPCCR_MDIV_BIT 12 |
| paul@0 | 223 | #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) |
| paul@0 | 224 | #define CPM_CPCCR_PDIV_BIT 8 |
| paul@0 | 225 | #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) |
| paul@0 | 226 | #define CPM_CPCCR_HDIV_BIT 4 |
| paul@0 | 227 | #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) |
| paul@0 | 228 | #define CPM_CPCCR_CDIV_BIT 0 |
| paul@0 | 229 | #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) |
| paul@0 | 230 | |
| paul@0 | 231 | /* I2S Clock Divider Register */ |
| paul@0 | 232 | #define CPM_I2SCDR_I2SDIV_BIT 0 |
| paul@0 | 233 | #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) |
| paul@0 | 234 | |
| paul@0 | 235 | /* LCD Pixel Clock Divider Register */ |
| paul@0 | 236 | #define CPM_LPCDR_PIXDIV_BIT 0 |
| paul@0 | 237 | #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) |
| paul@0 | 238 | |
| paul@0 | 239 | /* MSC Clock Divider Register */ |
| paul@0 | 240 | #define CPM_MSCCDR_MSCDIV_BIT 0 |
| paul@0 | 241 | #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) |
| paul@0 | 242 | |
| paul@0 | 243 | /* PLL Control Register */ |
| paul@0 | 244 | #define CPM_CPPCR_PLLM_BIT 23 |
| paul@0 | 245 | #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) |
| paul@0 | 246 | #define CPM_CPPCR_PLLN_BIT 18 |
| paul@0 | 247 | #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) |
| paul@0 | 248 | #define CPM_CPPCR_PLLOD_BIT 16 |
| paul@0 | 249 | #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) |
| paul@0 | 250 | #define CPM_CPPCR_PLLS (1 << 10) |
| paul@0 | 251 | #define CPM_CPPCR_PLLBP (1 << 9) |
| paul@0 | 252 | #define CPM_CPPCR_PLLEN (1 << 8) |
| paul@0 | 253 | #define CPM_CPPCR_PLLST_BIT 0 |
| paul@0 | 254 | #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) |
| paul@0 | 255 | |
| paul@0 | 256 | /* Low Power Control Register */ |
| paul@0 | 257 | #define CPM_LCR_DOZE_DUTY_BIT 3 |
| paul@0 | 258 | #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) |
| paul@0 | 259 | #define CPM_LCR_DOZE_ON (1 << 2) |
| paul@0 | 260 | #define CPM_LCR_LPM_BIT 0 |
| paul@0 | 261 | #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) |
| paul@0 | 262 | #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) |
| paul@0 | 263 | #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) |
| paul@0 | 264 | |
| paul@0 | 265 | /* Clock Gate Register */ |
| paul@0 | 266 | #define CPM_CLKGR_UART1 (1 << 15) |
| paul@0 | 267 | #define CPM_CLKGR_UHC (1 << 14) |
| paul@0 | 268 | #define CPM_CLKGR_IPU (1 << 13) |
| paul@0 | 269 | #define CPM_CLKGR_DMAC (1 << 12) |
| paul@0 | 270 | #define CPM_CLKGR_UDC (1 << 11) |
| paul@0 | 271 | #define CPM_CLKGR_LCD (1 << 10) |
| paul@0 | 272 | #define CPM_CLKGR_CIM (1 << 9) |
| paul@0 | 273 | #define CPM_CLKGR_SADC (1 << 8) |
| paul@0 | 274 | #define CPM_CLKGR_MSC (1 << 7) |
| paul@0 | 275 | #define CPM_CLKGR_AIC1 (1 << 6) |
| paul@0 | 276 | #define CPM_CLKGR_AIC2 (1 << 5) |
| paul@0 | 277 | #define CPM_CLKGR_SSI (1 << 4) |
| paul@0 | 278 | #define CPM_CLKGR_I2C (1 << 3) |
| paul@0 | 279 | #define CPM_CLKGR_RTC (1 << 2) |
| paul@0 | 280 | #define CPM_CLKGR_TCU (1 << 1) |
| paul@0 | 281 | #define CPM_CLKGR_UART0 (1 << 0) |
| paul@0 | 282 | |
| paul@0 | 283 | /* Sleep Control Register */ |
| paul@0 | 284 | #define CPM_SCR_O1ST_BIT 8 |
| paul@0 | 285 | #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) |
| paul@1 | 286 | #define CPM_SCR_UDCPHY_ENABLE (1 << 6) |
| paul@1 | 287 | #define CPM_SCR_USBPHY_DISABLE (1 << 7) |
| paul@0 | 288 | #define CPM_SCR_OSC_ENABLE (1 << 4) |
| paul@0 | 289 | |
| paul@0 | 290 | /* Hibernate Control Register */ |
| paul@0 | 291 | #define CPM_HCR_PD (1 << 0) |
| paul@0 | 292 | |
| paul@0 | 293 | /* Wakeup Filter Counter Register in Hibernate Mode */ |
| paul@0 | 294 | #define CPM_HWFCR_TIME_BIT 0 |
| paul@0 | 295 | #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) |
| paul@0 | 296 | |
| paul@0 | 297 | /* Reset Counter Register in Hibernate Mode */ |
| paul@0 | 298 | #define CPM_HRCR_TIME_BIT 0 |
| paul@0 | 299 | #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) |
| paul@0 | 300 | |
| paul@0 | 301 | /* Wakeup Control Register in Hibernate Mode */ |
| paul@0 | 302 | #define CPM_HWCR_WLE_LOW (0 << 2) |
| paul@0 | 303 | #define CPM_HWCR_WLE_HIGH (1 << 2) |
| paul@0 | 304 | #define CPM_HWCR_PIN_WAKEUP (1 << 1) |
| paul@0 | 305 | #define CPM_HWCR_RTC_WAKEUP (1 << 0) |
| paul@0 | 306 | |
| paul@0 | 307 | /* Wakeup Status Register in Hibernate Mode */ |
| paul@0 | 308 | #define CPM_HWSR_WSR_PIN (1 << 1) |
| paul@0 | 309 | #define CPM_HWSR_WSR_RTC (1 << 0) |
| paul@0 | 310 | |
| paul@0 | 311 | /* Reset Status Register */ |
| paul@0 | 312 | #define CPM_RSR_HR (1 << 2) |
| paul@0 | 313 | #define CPM_RSR_WR (1 << 1) |
| paul@0 | 314 | #define CPM_RSR_PR (1 << 0) |
| paul@0 | 315 | |
| paul@0 | 316 | |
| paul@0 | 317 | /************************************************************************* |
| paul@0 | 318 | * TCU (Timer Counter Unit) |
| paul@0 | 319 | *************************************************************************/ |
| paul@0 | 320 | #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ |
| paul@0 | 321 | #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ |
| paul@0 | 322 | #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ |
| paul@0 | 323 | #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ |
| paul@0 | 324 | #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ |
| paul@0 | 325 | #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ |
| paul@0 | 326 | #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ |
| paul@0 | 327 | #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ |
| paul@0 | 328 | #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ |
| paul@0 | 329 | #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ |
| paul@0 | 330 | #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ |
| paul@0 | 331 | #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ |
| paul@0 | 332 | #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ |
| paul@0 | 333 | #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ |
| paul@0 | 334 | #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ |
| paul@0 | 335 | #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ |
| paul@0 | 336 | #define TCU_TDFR1 (TCU_BASE + 0x50) |
| paul@0 | 337 | #define TCU_TDHR1 (TCU_BASE + 0x54) |
| paul@0 | 338 | #define TCU_TCNT1 (TCU_BASE + 0x58) |
| paul@0 | 339 | #define TCU_TCSR1 (TCU_BASE + 0x5C) |
| paul@0 | 340 | #define TCU_TDFR2 (TCU_BASE + 0x60) |
| paul@0 | 341 | #define TCU_TDHR2 (TCU_BASE + 0x64) |
| paul@0 | 342 | #define TCU_TCNT2 (TCU_BASE + 0x68) |
| paul@0 | 343 | #define TCU_TCSR2 (TCU_BASE + 0x6C) |
| paul@0 | 344 | #define TCU_TDFR3 (TCU_BASE + 0x70) |
| paul@0 | 345 | #define TCU_TDHR3 (TCU_BASE + 0x74) |
| paul@0 | 346 | #define TCU_TCNT3 (TCU_BASE + 0x78) |
| paul@0 | 347 | #define TCU_TCSR3 (TCU_BASE + 0x7C) |
| paul@0 | 348 | #define TCU_TDFR4 (TCU_BASE + 0x80) |
| paul@0 | 349 | #define TCU_TDHR4 (TCU_BASE + 0x84) |
| paul@0 | 350 | #define TCU_TCNT4 (TCU_BASE + 0x88) |
| paul@0 | 351 | #define TCU_TCSR4 (TCU_BASE + 0x8C) |
| paul@0 | 352 | #define TCU_TDFR5 (TCU_BASE + 0x90) |
| paul@0 | 353 | #define TCU_TDHR5 (TCU_BASE + 0x94) |
| paul@0 | 354 | #define TCU_TCNT5 (TCU_BASE + 0x98) |
| paul@0 | 355 | #define TCU_TCSR5 (TCU_BASE + 0x9C) |
| paul@0 | 356 | |
| paul@0 | 357 | #define REG_TCU_TSR REG32(TCU_TSR) |
| paul@0 | 358 | #define REG_TCU_TSSR REG32(TCU_TSSR) |
| paul@0 | 359 | #define REG_TCU_TSCR REG32(TCU_TSCR) |
| paul@0 | 360 | #define REG_TCU_TER REG8(TCU_TER) |
| paul@0 | 361 | #define REG_TCU_TESR REG8(TCU_TESR) |
| paul@0 | 362 | #define REG_TCU_TECR REG8(TCU_TECR) |
| paul@0 | 363 | #define REG_TCU_TFR REG32(TCU_TFR) |
| paul@0 | 364 | #define REG_TCU_TFSR REG32(TCU_TFSR) |
| paul@0 | 365 | #define REG_TCU_TFCR REG32(TCU_TFCR) |
| paul@0 | 366 | #define REG_TCU_TMR REG32(TCU_TMR) |
| paul@0 | 367 | #define REG_TCU_TMSR REG32(TCU_TMSR) |
| paul@0 | 368 | #define REG_TCU_TMCR REG32(TCU_TMCR) |
| paul@0 | 369 | #define REG_TCU_TDFR0 REG16(TCU_TDFR0) |
| paul@0 | 370 | #define REG_TCU_TDHR0 REG16(TCU_TDHR0) |
| paul@0 | 371 | #define REG_TCU_TCNT0 REG16(TCU_TCNT0) |
| paul@0 | 372 | #define REG_TCU_TCSR0 REG16(TCU_TCSR0) |
| paul@0 | 373 | #define REG_TCU_TDFR1 REG16(TCU_TDFR1) |
| paul@0 | 374 | #define REG_TCU_TDHR1 REG16(TCU_TDHR1) |
| paul@0 | 375 | #define REG_TCU_TCNT1 REG16(TCU_TCNT1) |
| paul@0 | 376 | #define REG_TCU_TCSR1 REG16(TCU_TCSR1) |
| paul@0 | 377 | #define REG_TCU_TDFR2 REG16(TCU_TDFR2) |
| paul@0 | 378 | #define REG_TCU_TDHR2 REG16(TCU_TDHR2) |
| paul@0 | 379 | #define REG_TCU_TCNT2 REG16(TCU_TCNT2) |
| paul@0 | 380 | #define REG_TCU_TCSR2 REG16(TCU_TCSR2) |
| paul@0 | 381 | #define REG_TCU_TDFR3 REG16(TCU_TDFR3) |
| paul@0 | 382 | #define REG_TCU_TDHR3 REG16(TCU_TDHR3) |
| paul@0 | 383 | #define REG_TCU_TCNT3 REG16(TCU_TCNT3) |
| paul@0 | 384 | #define REG_TCU_TCSR3 REG16(TCU_TCSR3) |
| paul@0 | 385 | #define REG_TCU_TDFR4 REG16(TCU_TDFR4) |
| paul@0 | 386 | #define REG_TCU_TDHR4 REG16(TCU_TDHR4) |
| paul@0 | 387 | #define REG_TCU_TCNT4 REG16(TCU_TCNT4) |
| paul@0 | 388 | #define REG_TCU_TCSR4 REG16(TCU_TCSR4) |
| paul@0 | 389 | |
| paul@0 | 390 | /* n = 0,1,2,3,4,5 */ |
| paul@0 | 391 | #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ |
| paul@0 | 392 | #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ |
| paul@0 | 393 | #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ |
| paul@0 | 394 | #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ |
| paul@0 | 395 | |
| paul@0 | 396 | #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) |
| paul@0 | 397 | #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) |
| paul@0 | 398 | #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) |
| paul@0 | 399 | #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) |
| paul@0 | 400 | |
| paul@0 | 401 | /* Register definitions */ |
| paul@0 | 402 | #define TCU_TCSR_PWM_SD (1 << 9) |
| paul@0 | 403 | #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) |
| paul@0 | 404 | #define TCU_TCSR_PWM_EN (1 << 7) |
| paul@0 | 405 | #define TCU_TCSR_PRESCALE_BIT 3 |
| paul@0 | 406 | #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) |
| paul@1 | 407 | #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) |
| paul@1 | 408 | #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) |
| paul@1 | 409 | #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) |
| paul@1 | 410 | #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) |
| paul@1 | 411 | #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) |
| paul@1 | 412 | #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) |
| paul@0 | 413 | #define TCU_TCSR_EXT_EN (1 << 2) |
| paul@0 | 414 | #define TCU_TCSR_RTC_EN (1 << 1) |
| paul@0 | 415 | #define TCU_TCSR_PCK_EN (1 << 0) |
| paul@0 | 416 | |
| paul@0 | 417 | #define TCU_TER_TCEN5 (1 << 5) |
| paul@0 | 418 | #define TCU_TER_TCEN4 (1 << 4) |
| paul@0 | 419 | #define TCU_TER_TCEN3 (1 << 3) |
| paul@0 | 420 | #define TCU_TER_TCEN2 (1 << 2) |
| paul@0 | 421 | #define TCU_TER_TCEN1 (1 << 1) |
| paul@0 | 422 | #define TCU_TER_TCEN0 (1 << 0) |
| paul@0 | 423 | |
| paul@0 | 424 | #define TCU_TESR_TCST5 (1 << 5) |
| paul@0 | 425 | #define TCU_TESR_TCST4 (1 << 4) |
| paul@0 | 426 | #define TCU_TESR_TCST3 (1 << 3) |
| paul@0 | 427 | #define TCU_TESR_TCST2 (1 << 2) |
| paul@0 | 428 | #define TCU_TESR_TCST1 (1 << 1) |
| paul@0 | 429 | #define TCU_TESR_TCST0 (1 << 0) |
| paul@0 | 430 | |
| paul@0 | 431 | #define TCU_TECR_TCCL5 (1 << 5) |
| paul@0 | 432 | #define TCU_TECR_TCCL4 (1 << 4) |
| paul@0 | 433 | #define TCU_TECR_TCCL3 (1 << 3) |
| paul@0 | 434 | #define TCU_TECR_TCCL2 (1 << 2) |
| paul@0 | 435 | #define TCU_TECR_TCCL1 (1 << 1) |
| paul@0 | 436 | #define TCU_TECR_TCCL0 (1 << 0) |
| paul@0 | 437 | |
| paul@0 | 438 | #define TCU_TFR_HFLAG5 (1 << 21) |
| paul@0 | 439 | #define TCU_TFR_HFLAG4 (1 << 20) |
| paul@0 | 440 | #define TCU_TFR_HFLAG3 (1 << 19) |
| paul@0 | 441 | #define TCU_TFR_HFLAG2 (1 << 18) |
| paul@0 | 442 | #define TCU_TFR_HFLAG1 (1 << 17) |
| paul@0 | 443 | #define TCU_TFR_HFLAG0 (1 << 16) |
| paul@0 | 444 | #define TCU_TFR_FFLAG5 (1 << 5) |
| paul@0 | 445 | #define TCU_TFR_FFLAG4 (1 << 4) |
| paul@0 | 446 | #define TCU_TFR_FFLAG3 (1 << 3) |
| paul@0 | 447 | #define TCU_TFR_FFLAG2 (1 << 2) |
| paul@0 | 448 | #define TCU_TFR_FFLAG1 (1 << 1) |
| paul@0 | 449 | #define TCU_TFR_FFLAG0 (1 << 0) |
| paul@0 | 450 | |
| paul@0 | 451 | #define TCU_TFSR_HFLAG5 (1 << 21) |
| paul@0 | 452 | #define TCU_TFSR_HFLAG4 (1 << 20) |
| paul@0 | 453 | #define TCU_TFSR_HFLAG3 (1 << 19) |
| paul@0 | 454 | #define TCU_TFSR_HFLAG2 (1 << 18) |
| paul@0 | 455 | #define TCU_TFSR_HFLAG1 (1 << 17) |
| paul@0 | 456 | #define TCU_TFSR_HFLAG0 (1 << 16) |
| paul@0 | 457 | #define TCU_TFSR_FFLAG5 (1 << 5) |
| paul@0 | 458 | #define TCU_TFSR_FFLAG4 (1 << 4) |
| paul@0 | 459 | #define TCU_TFSR_FFLAG3 (1 << 3) |
| paul@0 | 460 | #define TCU_TFSR_FFLAG2 (1 << 2) |
| paul@0 | 461 | #define TCU_TFSR_FFLAG1 (1 << 1) |
| paul@0 | 462 | #define TCU_TFSR_FFLAG0 (1 << 0) |
| paul@0 | 463 | |
| paul@0 | 464 | #define TCU_TFCR_HFLAG5 (1 << 21) |
| paul@0 | 465 | #define TCU_TFCR_HFLAG4 (1 << 20) |
| paul@0 | 466 | #define TCU_TFCR_HFLAG3 (1 << 19) |
| paul@0 | 467 | #define TCU_TFCR_HFLAG2 (1 << 18) |
| paul@0 | 468 | #define TCU_TFCR_HFLAG1 (1 << 17) |
| paul@0 | 469 | #define TCU_TFCR_HFLAG0 (1 << 16) |
| paul@0 | 470 | #define TCU_TFCR_FFLAG5 (1 << 5) |
| paul@0 | 471 | #define TCU_TFCR_FFLAG4 (1 << 4) |
| paul@0 | 472 | #define TCU_TFCR_FFLAG3 (1 << 3) |
| paul@0 | 473 | #define TCU_TFCR_FFLAG2 (1 << 2) |
| paul@0 | 474 | #define TCU_TFCR_FFLAG1 (1 << 1) |
| paul@0 | 475 | #define TCU_TFCR_FFLAG0 (1 << 0) |
| paul@0 | 476 | |
| paul@0 | 477 | #define TCU_TMR_HMASK5 (1 << 21) |
| paul@0 | 478 | #define TCU_TMR_HMASK4 (1 << 20) |
| paul@0 | 479 | #define TCU_TMR_HMASK3 (1 << 19) |
| paul@0 | 480 | #define TCU_TMR_HMASK2 (1 << 18) |
| paul@0 | 481 | #define TCU_TMR_HMASK1 (1 << 17) |
| paul@0 | 482 | #define TCU_TMR_HMASK0 (1 << 16) |
| paul@0 | 483 | #define TCU_TMR_FMASK5 (1 << 5) |
| paul@0 | 484 | #define TCU_TMR_FMASK4 (1 << 4) |
| paul@0 | 485 | #define TCU_TMR_FMASK3 (1 << 3) |
| paul@0 | 486 | #define TCU_TMR_FMASK2 (1 << 2) |
| paul@0 | 487 | #define TCU_TMR_FMASK1 (1 << 1) |
| paul@0 | 488 | #define TCU_TMR_FMASK0 (1 << 0) |
| paul@0 | 489 | |
| paul@0 | 490 | #define TCU_TMSR_HMST5 (1 << 21) |
| paul@0 | 491 | #define TCU_TMSR_HMST4 (1 << 20) |
| paul@0 | 492 | #define TCU_TMSR_HMST3 (1 << 19) |
| paul@0 | 493 | #define TCU_TMSR_HMST2 (1 << 18) |
| paul@0 | 494 | #define TCU_TMSR_HMST1 (1 << 17) |
| paul@0 | 495 | #define TCU_TMSR_HMST0 (1 << 16) |
| paul@0 | 496 | #define TCU_TMSR_FMST5 (1 << 5) |
| paul@0 | 497 | #define TCU_TMSR_FMST4 (1 << 4) |
| paul@0 | 498 | #define TCU_TMSR_FMST3 (1 << 3) |
| paul@0 | 499 | #define TCU_TMSR_FMST2 (1 << 2) |
| paul@0 | 500 | #define TCU_TMSR_FMST1 (1 << 1) |
| paul@0 | 501 | #define TCU_TMSR_FMST0 (1 << 0) |
| paul@0 | 502 | |
| paul@0 | 503 | #define TCU_TMCR_HMCL5 (1 << 21) |
| paul@0 | 504 | #define TCU_TMCR_HMCL4 (1 << 20) |
| paul@0 | 505 | #define TCU_TMCR_HMCL3 (1 << 19) |
| paul@0 | 506 | #define TCU_TMCR_HMCL2 (1 << 18) |
| paul@0 | 507 | #define TCU_TMCR_HMCL1 (1 << 17) |
| paul@0 | 508 | #define TCU_TMCR_HMCL0 (1 << 16) |
| paul@0 | 509 | #define TCU_TMCR_FMCL5 (1 << 5) |
| paul@0 | 510 | #define TCU_TMCR_FMCL4 (1 << 4) |
| paul@0 | 511 | #define TCU_TMCR_FMCL3 (1 << 3) |
| paul@0 | 512 | #define TCU_TMCR_FMCL2 (1 << 2) |
| paul@0 | 513 | #define TCU_TMCR_FMCL1 (1 << 1) |
| paul@0 | 514 | #define TCU_TMCR_FMCL0 (1 << 0) |
| paul@0 | 515 | |
| paul@0 | 516 | #define TCU_TSR_WDTS (1 << 16) |
| paul@0 | 517 | #define TCU_TSR_STOP5 (1 << 5) |
| paul@0 | 518 | #define TCU_TSR_STOP4 (1 << 4) |
| paul@0 | 519 | #define TCU_TSR_STOP3 (1 << 3) |
| paul@0 | 520 | #define TCU_TSR_STOP2 (1 << 2) |
| paul@0 | 521 | #define TCU_TSR_STOP1 (1 << 1) |
| paul@0 | 522 | #define TCU_TSR_STOP0 (1 << 0) |
| paul@0 | 523 | |
| paul@0 | 524 | #define TCU_TSSR_WDTSS (1 << 16) |
| paul@0 | 525 | #define TCU_TSSR_STPS5 (1 << 5) |
| paul@0 | 526 | #define TCU_TSSR_STPS4 (1 << 4) |
| paul@0 | 527 | #define TCU_TSSR_STPS3 (1 << 3) |
| paul@0 | 528 | #define TCU_TSSR_STPS2 (1 << 2) |
| paul@0 | 529 | #define TCU_TSSR_STPS1 (1 << 1) |
| paul@0 | 530 | #define TCU_TSSR_STPS0 (1 << 0) |
| paul@0 | 531 | |
| paul@0 | 532 | #define TCU_TSSR_WDTSC (1 << 16) |
| paul@0 | 533 | #define TCU_TSSR_STPC5 (1 << 5) |
| paul@0 | 534 | #define TCU_TSSR_STPC4 (1 << 4) |
| paul@0 | 535 | #define TCU_TSSR_STPC3 (1 << 3) |
| paul@0 | 536 | #define TCU_TSSR_STPC2 (1 << 2) |
| paul@0 | 537 | #define TCU_TSSR_STPC1 (1 << 1) |
| paul@0 | 538 | #define TCU_TSSR_STPC0 (1 << 0) |
| paul@0 | 539 | |
| paul@0 | 540 | |
| paul@1 | 541 | /* |
| paul@0 | 542 | * WDT (WatchDog Timer) |
| paul@1 | 543 | */ |
| paul@0 | 544 | #define WDT_TDR (WDT_BASE + 0x00) |
| paul@0 | 545 | #define WDT_TCER (WDT_BASE + 0x04) |
| paul@0 | 546 | #define WDT_TCNT (WDT_BASE + 0x08) |
| paul@0 | 547 | #define WDT_TCSR (WDT_BASE + 0x0C) |
| paul@0 | 548 | |
| paul@0 | 549 | #define REG_WDT_TDR REG16(WDT_TDR) |
| paul@0 | 550 | #define REG_WDT_TCER REG8(WDT_TCER) |
| paul@0 | 551 | #define REG_WDT_TCNT REG16(WDT_TCNT) |
| paul@0 | 552 | #define REG_WDT_TCSR REG16(WDT_TCSR) |
| paul@0 | 553 | |
| paul@0 | 554 | /* Register definition */ |
| paul@0 | 555 | #define WDT_TCSR_PRESCALE_BIT 3 |
| paul@0 | 556 | #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) |
| paul@0 | 557 | #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) |
| paul@0 | 558 | #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) |
| paul@0 | 559 | #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) |
| paul@0 | 560 | #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) |
| paul@0 | 561 | #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) |
| paul@0 | 562 | #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) |
| paul@0 | 563 | #define WDT_TCSR_EXT_EN (1 << 2) |
| paul@0 | 564 | #define WDT_TCSR_RTC_EN (1 << 1) |
| paul@0 | 565 | #define WDT_TCSR_PCK_EN (1 << 0) |
| paul@0 | 566 | |
| paul@0 | 567 | #define WDT_TCER_TCEN (1 << 0) |
| paul@0 | 568 | |
| paul@0 | 569 | |
| paul@1 | 570 | /* |
| paul@0 | 571 | * DMAC (DMA Controller) |
| paul@1 | 572 | */ |
| paul@0 | 573 | |
| paul@0 | 574 | #define MAX_DMA_NUM 6 /* max 6 channels */ |
| paul@0 | 575 | |
| paul@0 | 576 | #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ |
| paul@0 | 577 | #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ |
| paul@0 | 578 | #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ |
| paul@0 | 579 | #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ |
| paul@0 | 580 | #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ |
| paul@0 | 581 | #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ |
| paul@0 | 582 | #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ |
| paul@0 | 583 | #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ |
| paul@0 | 584 | #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ |
| paul@0 | 585 | #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ |
| paul@0 | 586 | #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ |
| paul@0 | 587 | |
| paul@0 | 588 | /* channel 0 */ |
| paul@0 | 589 | #define DMAC_DSAR0 DMAC_DSAR(0) |
| paul@0 | 590 | #define DMAC_DTAR0 DMAC_DTAR(0) |
| paul@0 | 591 | #define DMAC_DTCR0 DMAC_DTCR(0) |
| paul@0 | 592 | #define DMAC_DRSR0 DMAC_DRSR(0) |
| paul@0 | 593 | #define DMAC_DCCSR0 DMAC_DCCSR(0) |
| paul@0 | 594 | #define DMAC_DCMD0 DMAC_DCMD(0) |
| paul@0 | 595 | #define DMAC_DDA0 DMAC_DDA(0) |
| paul@0 | 596 | |
| paul@0 | 597 | /* channel 1 */ |
| paul@0 | 598 | #define DMAC_DSAR1 DMAC_DSAR(1) |
| paul@0 | 599 | #define DMAC_DTAR1 DMAC_DTAR(1) |
| paul@0 | 600 | #define DMAC_DTCR1 DMAC_DTCR(1) |
| paul@0 | 601 | #define DMAC_DRSR1 DMAC_DRSR(1) |
| paul@0 | 602 | #define DMAC_DCCSR1 DMAC_DCCSR(1) |
| paul@0 | 603 | #define DMAC_DCMD1 DMAC_DCMD(1) |
| paul@0 | 604 | #define DMAC_DDA1 DMAC_DDA(1) |
| paul@0 | 605 | |
| paul@0 | 606 | /* channel 2 */ |
| paul@0 | 607 | #define DMAC_DSAR2 DMAC_DSAR(2) |
| paul@0 | 608 | #define DMAC_DTAR2 DMAC_DTAR(2) |
| paul@0 | 609 | #define DMAC_DTCR2 DMAC_DTCR(2) |
| paul@0 | 610 | #define DMAC_DRSR2 DMAC_DRSR(2) |
| paul@0 | 611 | #define DMAC_DCCSR2 DMAC_DCCSR(2) |
| paul@0 | 612 | #define DMAC_DCMD2 DMAC_DCMD(2) |
| paul@0 | 613 | #define DMAC_DDA2 DMAC_DDA(2) |
| paul@0 | 614 | |
| paul@0 | 615 | /* channel 3 */ |
| paul@0 | 616 | #define DMAC_DSAR3 DMAC_DSAR(3) |
| paul@0 | 617 | #define DMAC_DTAR3 DMAC_DTAR(3) |
| paul@0 | 618 | #define DMAC_DTCR3 DMAC_DTCR(3) |
| paul@0 | 619 | #define DMAC_DRSR3 DMAC_DRSR(3) |
| paul@0 | 620 | #define DMAC_DCCSR3 DMAC_DCCSR(3) |
| paul@0 | 621 | #define DMAC_DCMD3 DMAC_DCMD(3) |
| paul@0 | 622 | #define DMAC_DDA3 DMAC_DDA(3) |
| paul@0 | 623 | |
| paul@0 | 624 | /* channel 4 */ |
| paul@0 | 625 | #define DMAC_DSAR4 DMAC_DSAR(4) |
| paul@0 | 626 | #define DMAC_DTAR4 DMAC_DTAR(4) |
| paul@0 | 627 | #define DMAC_DTCR4 DMAC_DTCR(4) |
| paul@0 | 628 | #define DMAC_DRSR4 DMAC_DRSR(4) |
| paul@0 | 629 | #define DMAC_DCCSR4 DMAC_DCCSR(4) |
| paul@0 | 630 | #define DMAC_DCMD4 DMAC_DCMD(4) |
| paul@0 | 631 | #define DMAC_DDA4 DMAC_DDA(4) |
| paul@0 | 632 | |
| paul@0 | 633 | /* channel 5 */ |
| paul@0 | 634 | #define DMAC_DSAR5 DMAC_DSAR(5) |
| paul@0 | 635 | #define DMAC_DTAR5 DMAC_DTAR(5) |
| paul@0 | 636 | #define DMAC_DTCR5 DMAC_DTCR(5) |
| paul@0 | 637 | #define DMAC_DRSR5 DMAC_DRSR(5) |
| paul@0 | 638 | #define DMAC_DCCSR5 DMAC_DCCSR(5) |
| paul@0 | 639 | #define DMAC_DCMD5 DMAC_DCMD(5) |
| paul@0 | 640 | #define DMAC_DDA5 DMAC_DDA(5) |
| paul@0 | 641 | |
| paul@0 | 642 | #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) |
| paul@0 | 643 | #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) |
| paul@0 | 644 | #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) |
| paul@0 | 645 | #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) |
| paul@0 | 646 | #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) |
| paul@0 | 647 | #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) |
| paul@0 | 648 | #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) |
| paul@0 | 649 | #define REG_DMAC_DMACR REG32(DMAC_DMACR) |
| paul@0 | 650 | #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) |
| paul@0 | 651 | #define REG_DMAC_DMADBR REG32(DMAC_DMADBR) |
| paul@0 | 652 | #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) |
| paul@0 | 653 | |
| paul@0 | 654 | /* DMA request source register */ |
| paul@0 | 655 | #define DMAC_DRSR_RS_BIT 0 |
| paul@0 | 656 | #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) |
| paul@1 | 657 | #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) |
| paul@1 | 658 | #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) |
| paul@1 | 659 | #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) |
| paul@1 | 660 | #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) |
| paul@1 | 661 | #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) |
| paul@1 | 662 | #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) |
| paul@1 | 663 | #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) |
| paul@1 | 664 | #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) |
| paul@1 | 665 | #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) |
| paul@1 | 666 | #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) |
| paul@1 | 667 | #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) |
| paul@1 | 668 | #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) |
| paul@0 | 669 | |
| paul@0 | 670 | /* DMA channel control/status register */ |
| paul@0 | 671 | #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ |
| paul@0 | 672 | #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ |
| paul@0 | 673 | #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) |
| paul@0 | 674 | #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ |
| paul@0 | 675 | #define DMAC_DCCSR_AR (1 << 4) /* address error */ |
| paul@0 | 676 | #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ |
| paul@0 | 677 | #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ |
| paul@0 | 678 | #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ |
| paul@0 | 679 | #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ |
| paul@0 | 680 | |
| paul@0 | 681 | /* DMA channel command register */ |
| paul@0 | 682 | #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ |
| paul@0 | 683 | #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ |
| paul@0 | 684 | #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ |
| paul@0 | 685 | #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 686 | #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 687 | #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 688 | #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 689 | #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 690 | #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 691 | #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 692 | #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 693 | #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 694 | #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 695 | #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 696 | #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 697 | #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 698 | #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 699 | #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 700 | #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 701 | #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) |
| paul@0 | 702 | #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ |
| paul@0 | 703 | #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) |
| paul@0 | 704 | #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) |
| paul@0 | 705 | #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) |
| paul@0 | 706 | #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) |
| paul@0 | 707 | #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ |
| paul@0 | 708 | #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) |
| paul@0 | 709 | #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) |
| paul@0 | 710 | #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) |
| paul@0 | 711 | #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) |
| paul@0 | 712 | #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ |
| paul@0 | 713 | #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) |
| paul@0 | 714 | #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) |
| paul@0 | 715 | #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) |
| paul@0 | 716 | #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) |
| paul@0 | 717 | #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) |
| paul@0 | 718 | #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) |
| paul@0 | 719 | #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ |
| paul@0 | 720 | #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ |
| paul@0 | 721 | #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ |
| paul@0 | 722 | #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ |
| paul@0 | 723 | #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ |
| paul@0 | 724 | #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ |
| paul@0 | 725 | |
| paul@0 | 726 | /* DMA descriptor address register */ |
| paul@0 | 727 | #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ |
| paul@0 | 728 | #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) |
| paul@0 | 729 | #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ |
| paul@0 | 730 | #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) |
| paul@0 | 731 | |
| paul@0 | 732 | /* DMA control register */ |
| paul@0 | 733 | #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ |
| paul@0 | 734 | #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) |
| paul@0 | 735 | #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) |
| paul@0 | 736 | #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) |
| paul@0 | 737 | #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) |
| paul@0 | 738 | #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ |
| paul@0 | 739 | #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ |
| paul@0 | 740 | #define DMAC_DMACR_AR (1 << 2) /* address error flag */ |
| paul@0 | 741 | #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ |
| paul@0 | 742 | |
| paul@0 | 743 | /* DMA doorbell register */ |
| paul@0 | 744 | #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ |
| paul@0 | 745 | #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ |
| paul@0 | 746 | #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ |
| paul@0 | 747 | #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ |
| paul@0 | 748 | #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ |
| paul@0 | 749 | #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ |
| paul@0 | 750 | |
| paul@0 | 751 | /* DMA doorbell set register */ |
| paul@0 | 752 | #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ |
| paul@0 | 753 | #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ |
| paul@0 | 754 | #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ |
| paul@0 | 755 | #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ |
| paul@0 | 756 | #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ |
| paul@0 | 757 | #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ |
| paul@0 | 758 | |
| paul@0 | 759 | /* DMA interrupt pending register */ |
| paul@0 | 760 | #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ |
| paul@0 | 761 | #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ |
| paul@0 | 762 | #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ |
| paul@0 | 763 | #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ |
| paul@0 | 764 | #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ |
| paul@0 | 765 | #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ |
| paul@0 | 766 | |
| paul@0 | 767 | |
| paul@0 | 768 | /************************************************************************* |
| paul@0 | 769 | * GPIO (General-Purpose I/O Ports) |
| paul@0 | 770 | *************************************************************************/ |
| paul@0 | 771 | #define MAX_GPIO_NUM 128 |
| paul@0 | 772 | |
| paul@1 | 773 | /* = 0,1,2,3 */ |
| paul@0 | 774 | #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ |
| paul@0 | 775 | #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ |
| paul@0 | 776 | #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ |
| paul@0 | 777 | #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ |
| paul@0 | 778 | #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ |
| paul@0 | 779 | #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ |
| paul@0 | 780 | #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ |
| paul@0 | 781 | #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ |
| paul@0 | 782 | #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ |
| paul@0 | 783 | #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ |
| paul@0 | 784 | #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ |
| paul@0 | 785 | #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ |
| paul@0 | 786 | #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ |
| paul@0 | 787 | #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ |
| paul@0 | 788 | #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ |
| paul@0 | 789 | #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ |
| paul@0 | 790 | #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ |
| paul@0 | 791 | #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ |
| paul@0 | 792 | #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ |
| paul@0 | 793 | #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ |
| paul@0 | 794 | #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ |
| paul@0 | 795 | #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ |
| paul@0 | 796 | #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ |
| paul@0 | 797 | #define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */ |
| paul@0 | 798 | |
| paul@0 | 799 | #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ |
| paul@0 | 800 | #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ |
| paul@0 | 801 | #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) |
| paul@0 | 802 | #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) |
| paul@0 | 803 | #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ |
| paul@0 | 804 | #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) |
| paul@0 | 805 | #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) |
| paul@0 | 806 | #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ |
| paul@0 | 807 | #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) |
| paul@0 | 808 | #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) |
| paul@0 | 809 | #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ |
| paul@0 | 810 | #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) |
| paul@0 | 811 | #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) |
| paul@0 | 812 | #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ |
| paul@0 | 813 | #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) |
| paul@0 | 814 | #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) |
| paul@0 | 815 | #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ |
| paul@0 | 816 | #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) |
| paul@0 | 817 | #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) |
| paul@0 | 818 | #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ |
| paul@0 | 819 | #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) |
| paul@0 | 820 | #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) |
| paul@0 | 821 | #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ |
| paul@0 | 822 | #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ |
| paul@0 | 823 | |
| paul@0 | 824 | |
| paul@0 | 825 | /************************************************************************* |
| paul@0 | 826 | * UART |
| paul@0 | 827 | *************************************************************************/ |
| paul@0 | 828 | |
| paul@0 | 829 | #define IRDA_BASE UART0_BASE |
| paul@1 | 830 | /* #define UART_BASE UART0_BASE */ |
| paul@0 | 831 | #define UART_OFF 0x1000 |
| paul@0 | 832 | |
| paul@0 | 833 | /* Register Offset */ |
| paul@0 | 834 | #define OFF_RDR (0x00) /* R 8b H'xx */ |
| paul@0 | 835 | #define OFF_TDR (0x00) /* W 8b H'xx */ |
| paul@0 | 836 | #define OFF_DLLR (0x00) /* RW 8b H'00 */ |
| paul@0 | 837 | #define OFF_DLHR (0x04) /* RW 8b H'00 */ |
| paul@0 | 838 | #define OFF_IER (0x04) /* RW 8b H'00 */ |
| paul@0 | 839 | #define OFF_ISR (0x08) /* R 8b H'01 */ |
| paul@0 | 840 | #define OFF_FCR (0x08) /* W 8b H'00 */ |
| paul@0 | 841 | #define OFF_LCR (0x0C) /* RW 8b H'00 */ |
| paul@0 | 842 | #define OFF_MCR (0x10) /* RW 8b H'00 */ |
| paul@0 | 843 | #define OFF_LSR (0x14) /* R 8b H'00 */ |
| paul@0 | 844 | #define OFF_MSR (0x18) /* R 8b H'00 */ |
| paul@0 | 845 | #define OFF_SPR (0x1C) /* RW 8b H'00 */ |
| paul@0 | 846 | #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ |
| paul@0 | 847 | #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ |
| paul@0 | 848 | #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ |
| paul@0 | 849 | |
| paul@0 | 850 | /* Register Address */ |
| paul@0 | 851 | #define UART0_RDR (UART0_BASE + OFF_RDR) |
| paul@0 | 852 | #define UART0_TDR (UART0_BASE + OFF_TDR) |
| paul@0 | 853 | #define UART0_DLLR (UART0_BASE + OFF_DLLR) |
| paul@0 | 854 | #define UART0_DLHR (UART0_BASE + OFF_DLHR) |
| paul@0 | 855 | #define UART0_IER (UART0_BASE + OFF_IER) |
| paul@0 | 856 | #define UART0_ISR (UART0_BASE + OFF_ISR) |
| paul@0 | 857 | #define UART0_FCR (UART0_BASE + OFF_FCR) |
| paul@0 | 858 | #define UART0_LCR (UART0_BASE + OFF_LCR) |
| paul@0 | 859 | #define UART0_MCR (UART0_BASE + OFF_MCR) |
| paul@0 | 860 | #define UART0_LSR (UART0_BASE + OFF_LSR) |
| paul@0 | 861 | #define UART0_MSR (UART0_BASE + OFF_MSR) |
| paul@0 | 862 | #define UART0_SPR (UART0_BASE + OFF_SPR) |
| paul@0 | 863 | #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) |
| paul@0 | 864 | #define UART0_UMR (UART0_BASE + OFF_UMR) |
| paul@0 | 865 | #define UART0_UACR (UART0_BASE + OFF_UACR) |
| paul@0 | 866 | |
| paul@0 | 867 | /* |
| paul@0 | 868 | * Define macros for UART_IER |
| paul@0 | 869 | * UART Interrupt Enable Register |
| paul@0 | 870 | */ |
| paul@0 | 871 | #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ |
| paul@0 | 872 | #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ |
| paul@0 | 873 | #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ |
| paul@0 | 874 | #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ |
| paul@0 | 875 | #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ |
| paul@0 | 876 | |
| paul@0 | 877 | /* |
| paul@0 | 878 | * Define macros for UART_ISR |
| paul@0 | 879 | * UART Interrupt Status Register |
| paul@0 | 880 | */ |
| paul@0 | 881 | #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ |
| paul@0 | 882 | #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ |
| paul@0 | 883 | #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ |
| paul@0 | 884 | #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ |
| paul@0 | 885 | #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ |
| paul@0 | 886 | #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ |
| paul@0 | 887 | #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ |
| paul@0 | 888 | #define UART_ISR_FFMS_NO_FIFO (0 << 6) |
| paul@0 | 889 | #define UART_ISR_FFMS_FIFO_MODE (3 << 6) |
| paul@0 | 890 | |
| paul@0 | 891 | /* |
| paul@0 | 892 | * Define macros for UART_FCR |
| paul@0 | 893 | * UART FIFO Control Register |
| paul@0 | 894 | */ |
| paul@0 | 895 | #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ |
| paul@0 | 896 | #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ |
| paul@0 | 897 | #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ |
| paul@0 | 898 | #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ |
| paul@0 | 899 | #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ |
| paul@0 | 900 | #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ |
| paul@0 | 901 | #define UART_FCR_RTRG_1 (0 << 6) |
| paul@0 | 902 | #define UART_FCR_RTRG_4 (1 << 6) |
| paul@0 | 903 | #define UART_FCR_RTRG_8 (2 << 6) |
| paul@0 | 904 | #define UART_FCR_RTRG_15 (3 << 6) |
| paul@0 | 905 | |
| paul@0 | 906 | /* |
| paul@0 | 907 | * Define macros for UART_LCR |
| paul@0 | 908 | * UART Line Control Register |
| paul@0 | 909 | */ |
| paul@0 | 910 | #define UART_LCR_WLEN (3 << 0) /* word length */ |
| paul@0 | 911 | #define UART_LCR_WLEN_5 (0 << 0) |
| paul@0 | 912 | #define UART_LCR_WLEN_6 (1 << 0) |
| paul@0 | 913 | #define UART_LCR_WLEN_7 (2 << 0) |
| paul@0 | 914 | #define UART_LCR_WLEN_8 (3 << 0) |
| paul@0 | 915 | #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| paul@0 | 916 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| paul@0 | 917 | #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| paul@0 | 918 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| paul@0 | 919 | #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| paul@0 | 920 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| paul@0 | 921 | |
| paul@0 | 922 | #define UART_LCR_PE (1 << 3) /* 0: parity disable */ |
| paul@0 | 923 | #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ |
| paul@0 | 924 | #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ |
| paul@0 | 925 | #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ |
| paul@0 | 926 | #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ |
| paul@0 | 927 | |
| paul@0 | 928 | /* |
| paul@0 | 929 | * Define macros for UART_LSR |
| paul@0 | 930 | * UART Line Status Register |
| paul@0 | 931 | */ |
| paul@0 | 932 | #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ |
| paul@0 | 933 | #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ |
| paul@0 | 934 | #define UART_LSR_PER (1 << 2) /* 0: no parity error */ |
| paul@0 | 935 | #define UART_LSR_FER (1 << 3) /* 0; no framing error */ |
| paul@0 | 936 | #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ |
| paul@0 | 937 | #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ |
| paul@0 | 938 | #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ |
| paul@0 | 939 | #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ |
| paul@0 | 940 | |
| paul@0 | 941 | /* |
| paul@0 | 942 | * Define macros for UART_MCR |
| paul@0 | 943 | * UART Modem Control Register |
| paul@0 | 944 | */ |
| paul@0 | 945 | #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ |
| paul@0 | 946 | #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ |
| paul@0 | 947 | #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ |
| paul@0 | 948 | #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ |
| paul@0 | 949 | #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ |
| paul@0 | 950 | #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ |
| paul@0 | 951 | |
| paul@0 | 952 | /* |
| paul@0 | 953 | * Define macros for UART_MSR |
| paul@0 | 954 | * UART Modem Status Register |
| paul@0 | 955 | */ |
| paul@0 | 956 | #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ |
| paul@0 | 957 | #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ |
| paul@0 | 958 | #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ |
| paul@0 | 959 | #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ |
| paul@0 | 960 | #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ |
| paul@0 | 961 | #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ |
| paul@0 | 962 | #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ |
| paul@0 | 963 | #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ |
| paul@0 | 964 | |
| paul@0 | 965 | /* |
| paul@0 | 966 | * Define macros for SIRCR |
| paul@0 | 967 | * Slow IrDA Control Register |
| paul@0 | 968 | */ |
| paul@0 | 969 | #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ |
| paul@0 | 970 | #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ |
| paul@0 | 971 | #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length |
| paul@0 | 972 | 1: 0 pulse width is 1.6us for 115.2Kbps */ |
| paul@0 | 973 | #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ |
| paul@0 | 974 | #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ |
| paul@0 | 975 | |
| paul@0 | 976 | |
| paul@0 | 977 | /************************************************************************* |
| paul@0 | 978 | * AIC (AC97/I2S Controller) |
| paul@0 | 979 | *************************************************************************/ |
| paul@0 | 980 | #define AIC_FR (AIC_BASE + 0x000) |
| paul@0 | 981 | #define AIC_CR (AIC_BASE + 0x004) |
| paul@0 | 982 | #define AIC_ACCR1 (AIC_BASE + 0x008) |
| paul@0 | 983 | #define AIC_ACCR2 (AIC_BASE + 0x00C) |
| paul@0 | 984 | #define AIC_I2SCR (AIC_BASE + 0x010) |
| paul@0 | 985 | #define AIC_SR (AIC_BASE + 0x014) |
| paul@0 | 986 | #define AIC_ACSR (AIC_BASE + 0x018) |
| paul@0 | 987 | #define AIC_I2SSR (AIC_BASE + 0x01C) |
| paul@0 | 988 | #define AIC_ACCAR (AIC_BASE + 0x020) |
| paul@0 | 989 | #define AIC_ACCDR (AIC_BASE + 0x024) |
| paul@0 | 990 | #define AIC_ACSAR (AIC_BASE + 0x028) |
| paul@0 | 991 | #define AIC_ACSDR (AIC_BASE + 0x02C) |
| paul@0 | 992 | #define AIC_I2SDIV (AIC_BASE + 0x030) |
| paul@0 | 993 | #define AIC_DR (AIC_BASE + 0x034) |
| paul@0 | 994 | |
| paul@0 | 995 | #define REG_AIC_FR REG32(AIC_FR) |
| paul@0 | 996 | #define REG_AIC_CR REG32(AIC_CR) |
| paul@0 | 997 | #define REG_AIC_ACCR1 REG32(AIC_ACCR1) |
| paul@0 | 998 | #define REG_AIC_ACCR2 REG32(AIC_ACCR2) |
| paul@0 | 999 | #define REG_AIC_I2SCR REG32(AIC_I2SCR) |
| paul@0 | 1000 | #define REG_AIC_SR REG32(AIC_SR) |
| paul@0 | 1001 | #define REG_AIC_ACSR REG32(AIC_ACSR) |
| paul@0 | 1002 | #define REG_AIC_I2SSR REG32(AIC_I2SSR) |
| paul@0 | 1003 | #define REG_AIC_ACCAR REG32(AIC_ACCAR) |
| paul@0 | 1004 | #define REG_AIC_ACCDR REG32(AIC_ACCDR) |
| paul@0 | 1005 | #define REG_AIC_ACSAR REG32(AIC_ACSAR) |
| paul@0 | 1006 | #define REG_AIC_ACSDR REG32(AIC_ACSDR) |
| paul@0 | 1007 | #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) |
| paul@0 | 1008 | #define REG_AIC_DR REG32(AIC_DR) |
| paul@0 | 1009 | |
| paul@0 | 1010 | /* AIC Controller Configuration Register (AIC_FR) */ |
| paul@0 | 1011 | |
| paul@0 | 1012 | #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ |
| paul@0 | 1013 | #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) |
| paul@0 | 1014 | #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ |
| paul@0 | 1015 | #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) |
| paul@0 | 1016 | #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ |
| paul@0 | 1017 | #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ |
| paul@0 | 1018 | #define AIC_FR_RST (1 << 3) /* AIC registers reset */ |
| paul@0 | 1019 | #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ |
| paul@0 | 1020 | #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ |
| paul@0 | 1021 | #define AIC_FR_ENB (1 << 0) /* AIC enable bit */ |
| paul@0 | 1022 | |
| paul@0 | 1023 | /* AIC Controller Common Control Register (AIC_CR) */ |
| paul@0 | 1024 | |
| paul@0 | 1025 | #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ |
| paul@0 | 1026 | #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) |
| paul@0 | 1027 | #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) |
| paul@0 | 1028 | #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) |
| paul@0 | 1029 | #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) |
| paul@0 | 1030 | #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) |
| paul@0 | 1031 | #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) |
| paul@0 | 1032 | #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ |
| paul@0 | 1033 | #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) |
| paul@0 | 1034 | #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) |
| paul@0 | 1035 | #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) |
| paul@0 | 1036 | #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) |
| paul@0 | 1037 | #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) |
| paul@0 | 1038 | #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) |
| paul@0 | 1039 | #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ |
| paul@0 | 1040 | #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ |
| paul@0 | 1041 | #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ |
| paul@0 | 1042 | #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ |
| paul@0 | 1043 | #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ |
| paul@0 | 1044 | #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ |
| paul@0 | 1045 | #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ |
| paul@0 | 1046 | #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ |
| paul@0 | 1047 | #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ |
| paul@0 | 1048 | #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ |
| paul@0 | 1049 | #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ |
| paul@0 | 1050 | #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ |
| paul@0 | 1051 | #define AIC_CR_EREC (1 << 0) /* Enable Record Function */ |
| paul@0 | 1052 | |
| paul@0 | 1053 | /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ |
| paul@0 | 1054 | |
| paul@0 | 1055 | #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ |
| paul@0 | 1056 | #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) |
| paul@0 | 1057 | #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ |
| paul@0 | 1058 | #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ |
| paul@0 | 1059 | #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ |
| paul@0 | 1060 | #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ |
| paul@0 | 1061 | #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ |
| paul@0 | 1062 | #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ |
| paul@0 | 1063 | #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ |
| paul@0 | 1064 | #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ |
| paul@0 | 1065 | #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ |
| paul@0 | 1066 | #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ |
| paul@0 | 1067 | #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ |
| paul@0 | 1068 | #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) |
| paul@0 | 1069 | #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ |
| paul@0 | 1070 | #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ |
| paul@0 | 1071 | #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ |
| paul@0 | 1072 | #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ |
| paul@0 | 1073 | #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ |
| paul@0 | 1074 | #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ |
| paul@0 | 1075 | #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ |
| paul@0 | 1076 | #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ |
| paul@0 | 1077 | #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ |
| paul@0 | 1078 | #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ |
| paul@0 | 1079 | |
| paul@0 | 1080 | /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ |
| paul@0 | 1081 | |
| paul@0 | 1082 | #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ |
| paul@0 | 1083 | #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ |
| paul@0 | 1084 | #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ |
| paul@0 | 1085 | #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ |
| paul@0 | 1086 | #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) |
| paul@0 | 1087 | #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ |
| paul@0 | 1088 | #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ |
| paul@0 | 1089 | #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ |
| paul@0 | 1090 | #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ |
| paul@0 | 1091 | #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ |
| paul@0 | 1092 | #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) |
| paul@0 | 1093 | #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ |
| paul@0 | 1094 | #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ |
| paul@0 | 1095 | #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ |
| paul@0 | 1096 | #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ |
| paul@0 | 1097 | #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ |
| paul@0 | 1098 | #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ |
| paul@0 | 1099 | #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ |
| paul@0 | 1100 | #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ |
| paul@0 | 1101 | |
| paul@0 | 1102 | /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ |
| paul@0 | 1103 | |
| paul@0 | 1104 | #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ |
| paul@0 | 1105 | #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ |
| paul@0 | 1106 | #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) |
| paul@0 | 1107 | #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ |
| paul@0 | 1108 | #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ |
| paul@0 | 1109 | #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ |
| paul@0 | 1110 | #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ |
| paul@0 | 1111 | #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ |
| paul@0 | 1112 | #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ |
| paul@0 | 1113 | |
| paul@0 | 1114 | /* AIC Controller FIFO Status Register (AIC_SR) */ |
| paul@0 | 1115 | |
| paul@0 | 1116 | #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ |
| paul@0 | 1117 | #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) |
| paul@0 | 1118 | #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ |
| paul@0 | 1119 | #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) |
| paul@0 | 1120 | #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ |
| paul@0 | 1121 | #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ |
| paul@0 | 1122 | #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ |
| paul@0 | 1123 | #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ |
| paul@0 | 1124 | |
| paul@0 | 1125 | /* AIC Controller AC-link Status Register (AIC_ACSR) */ |
| paul@0 | 1126 | |
| paul@0 | 1127 | #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ |
| paul@0 | 1128 | #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ |
| paul@0 | 1129 | #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ |
| paul@0 | 1130 | #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ |
| paul@0 | 1131 | #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ |
| paul@0 | 1132 | #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ |
| paul@0 | 1133 | |
| paul@0 | 1134 | /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ |
| paul@0 | 1135 | |
| paul@0 | 1136 | #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ |
| paul@0 | 1137 | |
| paul@0 | 1138 | /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ |
| paul@0 | 1139 | |
| paul@0 | 1140 | #define AIC_ACCAR_CAR_BIT 0 |
| paul@0 | 1141 | #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) |
| paul@0 | 1142 | |
| paul@0 | 1143 | /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ |
| paul@0 | 1144 | |
| paul@0 | 1145 | #define AIC_ACCDR_CDR_BIT 0 |
| paul@0 | 1146 | #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) |
| paul@0 | 1147 | |
| paul@0 | 1148 | /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ |
| paul@0 | 1149 | |
| paul@0 | 1150 | #define AIC_ACSAR_SAR_BIT 0 |
| paul@0 | 1151 | #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) |
| paul@0 | 1152 | |
| paul@0 | 1153 | /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ |
| paul@0 | 1154 | |
| paul@0 | 1155 | #define AIC_ACSDR_SDR_BIT 0 |
| paul@0 | 1156 | #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) |
| paul@0 | 1157 | |
| paul@0 | 1158 | /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ |
| paul@0 | 1159 | |
| paul@0 | 1160 | #define AIC_I2SDIV_DIV_BIT 0 |
| paul@0 | 1161 | #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) |
| paul@0 | 1162 | #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ |
| paul@0 | 1163 | #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ |
| paul@0 | 1164 | #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ |
| paul@0 | 1165 | #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ |
| paul@0 | 1166 | #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ |
| paul@0 | 1167 | #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ |
| paul@0 | 1168 | |
| paul@0 | 1169 | |
| paul@0 | 1170 | /************************************************************************* |
| paul@0 | 1171 | * ICDC (Internal CODEC) |
| paul@0 | 1172 | *************************************************************************/ |
| paul@0 | 1173 | #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ |
| paul@0 | 1174 | #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ |
| paul@0 | 1175 | #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ |
| paul@0 | 1176 | #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ |
| paul@0 | 1177 | #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ |
| paul@0 | 1178 | #define ICDC_CDCCR1 (ICDC_BASE + 0x0080) |
| paul@0 | 1179 | #define ICDC_CDCCR2 (ICDC_BASE + 0x0084) |
| paul@0 | 1180 | |
| paul@0 | 1181 | #define REG_ICDC_CR REG32(ICDC_CR) |
| paul@0 | 1182 | #define REG_ICDC_APWAIT REG32(ICDC_APWAIT) |
| paul@0 | 1183 | #define REG_ICDC_APPRE REG32(ICDC_APPRE) |
| paul@0 | 1184 | #define REG_ICDC_APHPEN REG32(ICDC_APHPEN) |
| paul@0 | 1185 | #define REG_ICDC_APSR REG32(ICDC_APSR) |
| paul@0 | 1186 | #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) |
| paul@0 | 1187 | #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) |
| paul@0 | 1188 | |
| paul@0 | 1189 | /* ICDC Control Register */ |
| paul@0 | 1190 | #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ |
| paul@0 | 1191 | #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) |
| paul@0 | 1192 | #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ |
| paul@0 | 1193 | #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1194 | #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1195 | #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1196 | #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1197 | #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1198 | #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1199 | #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1200 | #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1201 | #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1202 | #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) |
| paul@0 | 1203 | #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ |
| paul@0 | 1204 | #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) |
| paul@0 | 1205 | #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) |
| paul@0 | 1206 | #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) |
| paul@0 | 1207 | #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) |
| paul@0 | 1208 | #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) |
| paul@0 | 1209 | #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ |
| paul@0 | 1210 | #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) |
| paul@0 | 1211 | #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) |
| paul@0 | 1212 | #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) |
| paul@0 | 1213 | #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) |
| paul@0 | 1214 | #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) |
| paul@0 | 1215 | #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ |
| paul@0 | 1216 | #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ |
| paul@0 | 1217 | #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ |
| paul@0 | 1218 | #define ICDC_CR_EADC (1 << 10) /* Enable ADC */ |
| paul@0 | 1219 | #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ |
| paul@0 | 1220 | #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ |
| paul@0 | 1221 | #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ |
| paul@0 | 1222 | #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ |
| paul@0 | 1223 | #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ |
| paul@0 | 1224 | #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ |
| paul@0 | 1225 | #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ |
| paul@0 | 1226 | #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ |
| paul@0 | 1227 | |
| paul@0 | 1228 | /* Anti-Pop WAIT Stage Timing Control Register */ |
| paul@0 | 1229 | #define ICDC_APWAIT_WAITSN_BIT 0 |
| paul@0 | 1230 | #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) |
| paul@0 | 1231 | |
| paul@0 | 1232 | /* Anti-Pop HPEN-PRE Stage Timing Control Register */ |
| paul@0 | 1233 | #define ICDC_APPRE_PRESN_BIT 0 |
| paul@0 | 1234 | #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) |
| paul@0 | 1235 | |
| paul@0 | 1236 | /* Anti-Pop HPEN Stage Timing Control Register */ |
| paul@0 | 1237 | #define ICDC_APHPEN_HPENSN_BIT 0 |
| paul@0 | 1238 | #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) |
| paul@0 | 1239 | |
| paul@0 | 1240 | /* Anti-Pop Status Register */ |
| paul@0 | 1241 | #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ |
| paul@0 | 1242 | #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) |
| paul@0 | 1243 | #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ |
| paul@0 | 1244 | #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ |
| paul@0 | 1245 | #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ |
| paul@0 | 1246 | #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ |
| paul@0 | 1247 | #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ |
| paul@0 | 1248 | #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ |
| paul@0 | 1249 | #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ |
| paul@0 | 1250 | #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ |
| paul@0 | 1251 | #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ |
| paul@0 | 1252 | #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) |
| paul@0 | 1253 | |
| paul@0 | 1254 | |
| paul@0 | 1255 | /************************************************************************* |
| paul@0 | 1256 | * I2C |
| paul@0 | 1257 | *************************************************************************/ |
| paul@0 | 1258 | #define I2C_DR (I2C_BASE + 0x000) |
| paul@0 | 1259 | #define I2C_CR (I2C_BASE + 0x004) |
| paul@0 | 1260 | #define I2C_SR (I2C_BASE + 0x008) |
| paul@0 | 1261 | #define I2C_GR (I2C_BASE + 0x00C) |
| paul@0 | 1262 | |
| paul@0 | 1263 | #define REG_I2C_DR REG8(I2C_DR) |
| paul@0 | 1264 | #define REG_I2C_CR REG8(I2C_CR) |
| paul@0 | 1265 | #define REG_I2C_SR REG8(I2C_SR) |
| paul@0 | 1266 | #define REG_I2C_GR REG16(I2C_GR) |
| paul@0 | 1267 | |
| paul@0 | 1268 | /* I2C Control Register (I2C_CR) */ |
| paul@0 | 1269 | |
| paul@0 | 1270 | #define I2C_CR_IEN (1 << 4) |
| paul@0 | 1271 | #define I2C_CR_STA (1 << 3) |
| paul@0 | 1272 | #define I2C_CR_STO (1 << 2) |
| paul@0 | 1273 | #define I2C_CR_AC (1 << 1) |
| paul@0 | 1274 | #define I2C_CR_I2CE (1 << 0) |
| paul@0 | 1275 | |
| paul@0 | 1276 | /* I2C Status Register (I2C_SR) */ |
| paul@0 | 1277 | |
| paul@0 | 1278 | #define I2C_SR_STX (1 << 4) |
| paul@0 | 1279 | #define I2C_SR_BUSY (1 << 3) |
| paul@0 | 1280 | #define I2C_SR_TEND (1 << 2) |
| paul@0 | 1281 | #define I2C_SR_DRF (1 << 1) |
| paul@0 | 1282 | #define I2C_SR_ACKF (1 << 0) |
| paul@0 | 1283 | |
| paul@0 | 1284 | |
| paul@0 | 1285 | /************************************************************************* |
| paul@0 | 1286 | * SSI |
| paul@0 | 1287 | *************************************************************************/ |
| paul@0 | 1288 | #define SSI_DR (SSI_BASE + 0x000) |
| paul@0 | 1289 | #define SSI_CR0 (SSI_BASE + 0x004) |
| paul@0 | 1290 | #define SSI_CR1 (SSI_BASE + 0x008) |
| paul@0 | 1291 | #define SSI_SR (SSI_BASE + 0x00C) |
| paul@0 | 1292 | #define SSI_ITR (SSI_BASE + 0x010) |
| paul@0 | 1293 | #define SSI_ICR (SSI_BASE + 0x014) |
| paul@0 | 1294 | #define SSI_GR (SSI_BASE + 0x018) |
| paul@0 | 1295 | |
| paul@0 | 1296 | #define REG_SSI_DR REG32(SSI_DR) |
| paul@0 | 1297 | #define REG_SSI_CR0 REG16(SSI_CR0) |
| paul@0 | 1298 | #define REG_SSI_CR1 REG32(SSI_CR1) |
| paul@0 | 1299 | #define REG_SSI_SR REG32(SSI_SR) |
| paul@0 | 1300 | #define REG_SSI_ITR REG16(SSI_ITR) |
| paul@0 | 1301 | #define REG_SSI_ICR REG8(SSI_ICR) |
| paul@0 | 1302 | #define REG_SSI_GR REG16(SSI_GR) |
| paul@0 | 1303 | |
| paul@0 | 1304 | /* SSI Data Register (SSI_DR) */ |
| paul@0 | 1305 | |
| paul@0 | 1306 | #define SSI_DR_GPC_BIT 0 |
| paul@0 | 1307 | #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) |
| paul@0 | 1308 | |
| paul@0 | 1309 | /* SSI Control Register 0 (SSI_CR0) */ |
| paul@0 | 1310 | |
| paul@0 | 1311 | #define SSI_CR0_SSIE (1 << 15) |
| paul@0 | 1312 | #define SSI_CR0_TIE (1 << 14) |
| paul@0 | 1313 | #define SSI_CR0_RIE (1 << 13) |
| paul@0 | 1314 | #define SSI_CR0_TEIE (1 << 12) |
| paul@0 | 1315 | #define SSI_CR0_REIE (1 << 11) |
| paul@0 | 1316 | #define SSI_CR0_LOOP (1 << 10) |
| paul@0 | 1317 | #define SSI_CR0_RFINE (1 << 9) |
| paul@0 | 1318 | #define SSI_CR0_RFINC (1 << 8) |
| paul@0 | 1319 | #define SSI_CR0_FSEL (1 << 6) |
| paul@0 | 1320 | #define SSI_CR0_TFLUSH (1 << 2) |
| paul@0 | 1321 | #define SSI_CR0_RFLUSH (1 << 1) |
| paul@0 | 1322 | #define SSI_CR0_DISREV (1 << 0) |
| paul@0 | 1323 | |
| paul@0 | 1324 | /* SSI Control Register 1 (SSI_CR1) */ |
| paul@0 | 1325 | |
| paul@0 | 1326 | #define SSI_CR1_FRMHL_BIT 30 |
| paul@0 | 1327 | #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) |
| paul@0 | 1328 | #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ |
| paul@0 | 1329 | #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ |
| paul@0 | 1330 | #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ |
| paul@0 | 1331 | #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ |
| paul@0 | 1332 | #define SSI_CR1_TFVCK_BIT 28 |
| paul@0 | 1333 | #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) |
| paul@0 | 1334 | #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) |
| paul@0 | 1335 | #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) |
| paul@0 | 1336 | #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) |
| paul@0 | 1337 | #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) |
| paul@0 | 1338 | #define SSI_CR1_TCKFI_BIT 26 |
| paul@0 | 1339 | #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) |
| paul@0 | 1340 | #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) |
| paul@0 | 1341 | #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) |
| paul@0 | 1342 | #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) |
| paul@0 | 1343 | #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) |
| paul@0 | 1344 | #define SSI_CR1_LFST (1 << 25) |
| paul@0 | 1345 | #define SSI_CR1_ITFRM (1 << 24) |
| paul@0 | 1346 | #define SSI_CR1_UNFIN (1 << 23) |
| paul@0 | 1347 | #define SSI_CR1_MULTS (1 << 22) |
| paul@0 | 1348 | #define SSI_CR1_FMAT_BIT 20 |
| paul@0 | 1349 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) |
| paul@0 | 1350 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ |
| paul@0 | 1351 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ |
| paul@0 | 1352 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ |
| paul@0 | 1353 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ |
| paul@0 | 1354 | #define SSI_CR1_TTRG_BIT 16 |
| paul@0 | 1355 | #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) |
| paul@0 | 1356 | #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1357 | #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1358 | #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1359 | #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1360 | #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1361 | #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1362 | #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1363 | #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1364 | #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1365 | #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) |
| paul@0 | 1366 | #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) |
| paul@0 | 1367 | #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) |
| paul@0 | 1368 | #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) |
| paul@0 | 1369 | #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) |
| paul@0 | 1370 | #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) |
| paul@0 | 1371 | #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) |
| paul@0 | 1372 | #define SSI_CR1_MCOM_BIT 12 |
| paul@0 | 1373 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) |
| paul@0 | 1374 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ |
| paul@0 | 1375 | #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ |
| paul@0 | 1376 | #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ |
| paul@0 | 1377 | #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ |
| paul@0 | 1378 | #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ |
| paul@0 | 1379 | #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ |
| paul@0 | 1380 | #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ |
| paul@0 | 1381 | #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ |
| paul@0 | 1382 | #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ |
| paul@0 | 1383 | #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ |
| paul@0 | 1384 | #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ |
| paul@0 | 1385 | #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ |
| paul@0 | 1386 | #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ |
| paul@0 | 1387 | #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ |
| paul@0 | 1388 | #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ |
| paul@0 | 1389 | #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ |
| paul@0 | 1390 | #define SSI_CR1_RTRG_BIT 8 |
| paul@0 | 1391 | #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) |
| paul@0 | 1392 | #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1393 | #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1394 | #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1395 | #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1396 | #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1397 | #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1398 | #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1399 | #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1400 | #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1401 | #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) |
| paul@0 | 1402 | #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) |
| paul@0 | 1403 | #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) |
| paul@0 | 1404 | #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) |
| paul@0 | 1405 | #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) |
| paul@0 | 1406 | #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) |
| paul@0 | 1407 | #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) |
| paul@0 | 1408 | #define SSI_CR1_FLEN_BIT 4 |
| paul@0 | 1409 | #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) |
| paul@0 | 1410 | #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1411 | #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1412 | #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1413 | #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1414 | #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1415 | #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1416 | #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1417 | #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1418 | #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1419 | #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) |
| paul@0 | 1420 | #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) |
| paul@0 | 1421 | #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) |
| paul@0 | 1422 | #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) |
| paul@0 | 1423 | #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) |
| paul@0 | 1424 | #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) |
| paul@0 | 1425 | #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) |
| paul@0 | 1426 | #define SSI_CR1_PHA (1 << 1) |
| paul@0 | 1427 | #define SSI_CR1_POL (1 << 0) |
| paul@0 | 1428 | |
| paul@0 | 1429 | /* SSI Status Register (SSI_SR) */ |
| paul@0 | 1430 | |
| paul@0 | 1431 | #define SSI_SR_TFIFONUM_BIT 16 |
| paul@0 | 1432 | #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) |
| paul@0 | 1433 | #define SSI_SR_RFIFONUM_BIT 8 |
| paul@0 | 1434 | #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) |
| paul@0 | 1435 | #define SSI_SR_END (1 << 7) |
| paul@0 | 1436 | #define SSI_SR_BUSY (1 << 6) |
| paul@0 | 1437 | #define SSI_SR_TFF (1 << 5) |
| paul@0 | 1438 | #define SSI_SR_RFE (1 << 4) |
| paul@0 | 1439 | #define SSI_SR_TFHE (1 << 3) |
| paul@0 | 1440 | #define SSI_SR_RFHF (1 << 2) |
| paul@0 | 1441 | #define SSI_SR_UNDR (1 << 1) |
| paul@0 | 1442 | #define SSI_SR_OVER (1 << 0) |
| paul@0 | 1443 | |
| paul@0 | 1444 | /* SSI Interval Time Control Register (SSI_ITR) */ |
| paul@0 | 1445 | |
| paul@0 | 1446 | #define SSI_ITR_CNTCLK (1 << 15) |
| paul@0 | 1447 | #define SSI_ITR_IVLTM_BIT 0 |
| paul@0 | 1448 | #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) |
| paul@0 | 1449 | |
| paul@0 | 1450 | |
| paul@0 | 1451 | /************************************************************************* |
| paul@0 | 1452 | * MSC |
| paul@0 | 1453 | *************************************************************************/ |
| paul@0 | 1454 | #define MSC_STRPCL (MSC_BASE + 0x000) |
| paul@0 | 1455 | #define MSC_STAT (MSC_BASE + 0x004) |
| paul@0 | 1456 | #define MSC_CLKRT (MSC_BASE + 0x008) |
| paul@0 | 1457 | #define MSC_CMDAT (MSC_BASE + 0x00C) |
| paul@0 | 1458 | #define MSC_RESTO (MSC_BASE + 0x010) |
| paul@0 | 1459 | #define MSC_RDTO (MSC_BASE + 0x014) |
| paul@0 | 1460 | #define MSC_BLKLEN (MSC_BASE + 0x018) |
| paul@0 | 1461 | #define MSC_NOB (MSC_BASE + 0x01C) |
| paul@0 | 1462 | #define MSC_SNOB (MSC_BASE + 0x020) |
| paul@0 | 1463 | #define MSC_IMASK (MSC_BASE + 0x024) |
| paul@0 | 1464 | #define MSC_IREG (MSC_BASE + 0x028) |
| paul@0 | 1465 | #define MSC_CMD (MSC_BASE + 0x02C) |
| paul@0 | 1466 | #define MSC_ARG (MSC_BASE + 0x030) |
| paul@0 | 1467 | #define MSC_RES (MSC_BASE + 0x034) |
| paul@0 | 1468 | #define MSC_RXFIFO (MSC_BASE + 0x038) |
| paul@0 | 1469 | #define MSC_TXFIFO (MSC_BASE + 0x03C) |
| paul@0 | 1470 | |
| paul@0 | 1471 | #define REG_MSC_STRPCL REG16(MSC_STRPCL) |
| paul@0 | 1472 | #define REG_MSC_STAT REG32(MSC_STAT) |
| paul@0 | 1473 | #define REG_MSC_CLKRT REG16(MSC_CLKRT) |
| paul@0 | 1474 | #define REG_MSC_CMDAT REG32(MSC_CMDAT) |
| paul@0 | 1475 | #define REG_MSC_RESTO REG16(MSC_RESTO) |
| paul@0 | 1476 | #define REG_MSC_RDTO REG16(MSC_RDTO) |
| paul@0 | 1477 | #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) |
| paul@0 | 1478 | #define REG_MSC_NOB REG16(MSC_NOB) |
| paul@0 | 1479 | #define REG_MSC_SNOB REG16(MSC_SNOB) |
| paul@0 | 1480 | #define REG_MSC_IMASK REG16(MSC_IMASK) |
| paul@0 | 1481 | #define REG_MSC_IREG REG16(MSC_IREG) |
| paul@0 | 1482 | #define REG_MSC_CMD REG8(MSC_CMD) |
| paul@0 | 1483 | #define REG_MSC_ARG REG32(MSC_ARG) |
| paul@0 | 1484 | #define REG_MSC_RES REG16(MSC_RES) |
| paul@0 | 1485 | #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) |
| paul@0 | 1486 | #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) |
| paul@0 | 1487 | |
| paul@0 | 1488 | /* MSC Clock and Control Register (MSC_STRPCL) */ |
| paul@0 | 1489 | |
| paul@0 | 1490 | #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) |
| paul@0 | 1491 | #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) |
| paul@0 | 1492 | #define MSC_STRPCL_START_READWAIT (1 << 5) |
| paul@0 | 1493 | #define MSC_STRPCL_STOP_READWAIT (1 << 4) |
| paul@0 | 1494 | #define MSC_STRPCL_RESET (1 << 3) |
| paul@0 | 1495 | #define MSC_STRPCL_START_OP (1 << 2) |
| paul@0 | 1496 | #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 |
| paul@0 | 1497 | #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) |
| paul@0 | 1498 | #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ |
| paul@0 | 1499 | #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ |
| paul@0 | 1500 | |
| paul@0 | 1501 | /* MSC Status Register (MSC_STAT) */ |
| paul@0 | 1502 | |
| paul@0 | 1503 | #define MSC_STAT_IS_RESETTING (1 << 15) |
| paul@0 | 1504 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) |
| paul@0 | 1505 | #define MSC_STAT_PRG_DONE (1 << 13) |
| paul@0 | 1506 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) |
| paul@0 | 1507 | #define MSC_STAT_END_CMD_RES (1 << 11) |
| paul@0 | 1508 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) |
| paul@0 | 1509 | #define MSC_STAT_IS_READWAIT (1 << 9) |
| paul@0 | 1510 | #define MSC_STAT_CLK_EN (1 << 8) |
| paul@0 | 1511 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) |
| paul@0 | 1512 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) |
| paul@0 | 1513 | #define MSC_STAT_CRC_RES_ERR (1 << 5) |
| paul@0 | 1514 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) |
| paul@0 | 1515 | #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 |
| paul@0 | 1516 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) |
| paul@0 | 1517 | #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ |
| paul@0 | 1518 | #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ |
| paul@0 | 1519 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ |
| paul@0 | 1520 | #define MSC_STAT_TIME_OUT_RES (1 << 1) |
| paul@0 | 1521 | #define MSC_STAT_TIME_OUT_READ (1 << 0) |
| paul@0 | 1522 | |
| paul@0 | 1523 | /* MSC Bus Clock Control Register (MSC_CLKRT) */ |
| paul@0 | 1524 | |
| paul@0 | 1525 | #define MSC_CLKRT_CLK_RATE_BIT 0 |
| paul@0 | 1526 | #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) |
| paul@0 | 1527 | #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ |
| paul@0 | 1528 | #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ |
| paul@0 | 1529 | #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ |
| paul@0 | 1530 | #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ |
| paul@0 | 1531 | #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ |
| paul@0 | 1532 | #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ |
| paul@0 | 1533 | #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ |
| paul@0 | 1534 | #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ |
| paul@0 | 1535 | |
| paul@0 | 1536 | /* MSC Command Sequence Control Register (MSC_CMDAT) */ |
| paul@0 | 1537 | |
| paul@1 | 1538 | #define MSC_CMDAT_IO_ABORT (1 << 11) |
| paul@1 | 1539 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 |
| paul@1 | 1540 | #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) |
| paul@1 | 1541 | #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) |
| paul@1 | 1542 | #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) |
| paul@1 | 1543 | #define MSC_CMDAT_DMA_EN (1 << 8) |
| paul@1 | 1544 | #define MSC_CMDAT_INIT (1 << 7) |
| paul@1 | 1545 | #define MSC_CMDAT_BUSY (1 << 6) |
| paul@1 | 1546 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) |
| paul@1 | 1547 | #define MSC_CMDAT_WRITE (1 << 4) |
| paul@1 | 1548 | #define MSC_CMDAT_READ (0 << 4) |
| paul@1 | 1549 | #define MSC_CMDAT_DATA_EN (1 << 3) |
| paul@0 | 1550 | #define MSC_CMDAT_RESPONSE_BIT 0 |
| paul@0 | 1551 | #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) |
| paul@1 | 1552 | #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) |
| paul@1 | 1553 | #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) |
| paul@1 | 1554 | #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) |
| paul@1 | 1555 | #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) |
| paul@1 | 1556 | #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) |
| paul@1 | 1557 | #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) |
| paul@1 | 1558 | #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) |
| paul@0 | 1559 | |
| paul@0 | 1560 | /* MSC Interrupts Mask Register (MSC_IMASK) */ |
| paul@0 | 1561 | #define MSC_IMASK_SDIO (1 << 7) |
| paul@0 | 1562 | #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) |
| paul@0 | 1563 | #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) |
| paul@0 | 1564 | #define MSC_IMASK_END_CMD_RES (1 << 2) |
| paul@0 | 1565 | #define MSC_IMASK_PRG_DONE (1 << 1) |
| paul@0 | 1566 | #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) |
| paul@0 | 1567 | |
| paul@0 | 1568 | |
| paul@0 | 1569 | /* MSC Interrupts Status Register (MSC_IREG) */ |
| paul@0 | 1570 | #define MSC_IREG_SDIO (1 << 7) |
| paul@0 | 1571 | #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) |
| paul@0 | 1572 | #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) |
| paul@0 | 1573 | #define MSC_IREG_END_CMD_RES (1 << 2) |
| paul@0 | 1574 | #define MSC_IREG_PRG_DONE (1 << 1) |
| paul@0 | 1575 | #define MSC_IREG_DATA_TRAN_DONE (1 << 0) |
| paul@0 | 1576 | |
| paul@0 | 1577 | |
| paul@1 | 1578 | /* |
| paul@0 | 1579 | * EMC (External Memory Controller) |
| paul@1 | 1580 | */ |
| paul@0 | 1581 | #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ |
| paul@0 | 1582 | |
| paul@0 | 1583 | #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ |
| paul@0 | 1584 | #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ |
| paul@0 | 1585 | #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ |
| paul@0 | 1586 | #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ |
| paul@0 | 1587 | #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ |
| paul@0 | 1588 | #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ |
| paul@0 | 1589 | #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ |
| paul@0 | 1590 | #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ |
| paul@0 | 1591 | #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ |
| paul@0 | 1592 | #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ |
| paul@0 | 1593 | |
| paul@0 | 1594 | #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ |
| paul@0 | 1595 | #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ |
| paul@0 | 1596 | #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ |
| paul@0 | 1597 | #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ |
| paul@0 | 1598 | #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ |
| paul@0 | 1599 | #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ |
| paul@0 | 1600 | #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ |
| paul@0 | 1601 | #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ |
| paul@0 | 1602 | #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ |
| paul@0 | 1603 | #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ |
| paul@0 | 1604 | #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ |
| paul@0 | 1605 | #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ |
| paul@0 | 1606 | |
| paul@0 | 1607 | #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ |
| paul@0 | 1608 | #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ |
| paul@0 | 1609 | #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ |
| paul@0 | 1610 | #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ |
| paul@0 | 1611 | #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ |
| paul@0 | 1612 | #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ |
| paul@0 | 1613 | |
| paul@0 | 1614 | #define REG_EMC_BCR REG32(EMC_BCR) |
| paul@0 | 1615 | |
| paul@0 | 1616 | #define REG_EMC_SMCR0 REG32(EMC_SMCR0) |
| paul@0 | 1617 | #define REG_EMC_SMCR1 REG32(EMC_SMCR1) |
| paul@0 | 1618 | #define REG_EMC_SMCR2 REG32(EMC_SMCR2) |
| paul@0 | 1619 | #define REG_EMC_SMCR3 REG32(EMC_SMCR3) |
| paul@0 | 1620 | #define REG_EMC_SMCR4 REG32(EMC_SMCR4) |
| paul@0 | 1621 | #define REG_EMC_SACR0 REG32(EMC_SACR0) |
| paul@0 | 1622 | #define REG_EMC_SACR1 REG32(EMC_SACR1) |
| paul@0 | 1623 | #define REG_EMC_SACR2 REG32(EMC_SACR2) |
| paul@0 | 1624 | #define REG_EMC_SACR3 REG32(EMC_SACR3) |
| paul@0 | 1625 | #define REG_EMC_SACR4 REG32(EMC_SACR4) |
| paul@0 | 1626 | |
| paul@0 | 1627 | #define REG_EMC_NFCSR REG32(EMC_NFCSR) |
| paul@0 | 1628 | #define REG_EMC_NFECR REG32(EMC_NFECR) |
| paul@0 | 1629 | #define REG_EMC_NFECC REG32(EMC_NFECC) |
| paul@0 | 1630 | #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) |
| paul@0 | 1631 | #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) |
| paul@0 | 1632 | #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) |
| paul@0 | 1633 | #define REG_EMC_NFINTS REG32(EMC_NFINTS) |
| paul@0 | 1634 | #define REG_EMC_NFINTE REG32(EMC_NFINTE) |
| paul@0 | 1635 | #define REG_EMC_NFERR0 REG32(EMC_NFERR0) |
| paul@0 | 1636 | #define REG_EMC_NFERR1 REG32(EMC_NFERR1) |
| paul@0 | 1637 | #define REG_EMC_NFERR2 REG32(EMC_NFERR2) |
| paul@0 | 1638 | #define REG_EMC_NFERR3 REG32(EMC_NFERR3) |
| paul@0 | 1639 | |
| paul@0 | 1640 | #define REG_EMC_DMCR REG32(EMC_DMCR) |
| paul@0 | 1641 | #define REG_EMC_RTCSR REG16(EMC_RTCSR) |
| paul@0 | 1642 | #define REG_EMC_RTCNT REG16(EMC_RTCNT) |
| paul@0 | 1643 | #define REG_EMC_RTCOR REG16(EMC_RTCOR) |
| paul@0 | 1644 | #define REG_EMC_DMAR0 REG32(EMC_DMAR0) |
| paul@0 | 1645 | |
| paul@0 | 1646 | /* Static Memory Control Register */ |
| paul@0 | 1647 | #define EMC_SMCR_STRV_BIT 24 |
| paul@0 | 1648 | #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) |
| paul@0 | 1649 | #define EMC_SMCR_TAW_BIT 20 |
| paul@0 | 1650 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) |
| paul@0 | 1651 | #define EMC_SMCR_TBP_BIT 16 |
| paul@0 | 1652 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) |
| paul@0 | 1653 | #define EMC_SMCR_TAH_BIT 12 |
| paul@0 | 1654 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) |
| paul@0 | 1655 | #define EMC_SMCR_TAS_BIT 8 |
| paul@0 | 1656 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) |
| paul@0 | 1657 | #define EMC_SMCR_BW_BIT 6 |
| paul@0 | 1658 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) |
| paul@0 | 1659 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) |
| paul@0 | 1660 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) |
| paul@0 | 1661 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) |
| paul@0 | 1662 | #define EMC_SMCR_BCM (1 << 3) |
| paul@0 | 1663 | #define EMC_SMCR_BL_BIT 1 |
| paul@0 | 1664 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) |
| paul@0 | 1665 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) |
| paul@0 | 1666 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) |
| paul@0 | 1667 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) |
| paul@0 | 1668 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) |
| paul@0 | 1669 | #define EMC_SMCR_SMT (1 << 0) |
| paul@0 | 1670 | |
| paul@0 | 1671 | /* Static Memory Bank Addr Config Reg */ |
| paul@0 | 1672 | #define EMC_SACR_BASE_BIT 8 |
| paul@0 | 1673 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) |
| paul@0 | 1674 | #define EMC_SACR_MASK_BIT 0 |
| paul@0 | 1675 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) |
| paul@0 | 1676 | |
| paul@0 | 1677 | /* NAND Flash Control/Status Register */ |
| paul@0 | 1678 | #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ |
| paul@0 | 1679 | #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ |
| paul@0 | 1680 | #define EMC_NFCSR_NFCE3 (1 << 5) |
| paul@0 | 1681 | #define EMC_NFCSR_NFE3 (1 << 4) |
| paul@0 | 1682 | #define EMC_NFCSR_NFCE2 (1 << 3) |
| paul@0 | 1683 | #define EMC_NFCSR_NFE2 (1 << 2) |
| paul@0 | 1684 | #define EMC_NFCSR_NFCE1 (1 << 1) |
| paul@0 | 1685 | #define EMC_NFCSR_NFE1 (1 << 0) |
| paul@0 | 1686 | |
| paul@0 | 1687 | /* NAND Flash ECC Control Register */ |
| paul@0 | 1688 | #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ |
| paul@0 | 1689 | #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ |
| paul@0 | 1690 | #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ |
| paul@0 | 1691 | #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ |
| paul@0 | 1692 | #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ |
| paul@0 | 1693 | #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ |
| paul@0 | 1694 | #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ |
| paul@0 | 1695 | |
| paul@0 | 1696 | /* NAND Flash ECC Data Register */ |
| paul@0 | 1697 | #define EMC_NFECC_ECC2_BIT 16 |
| paul@0 | 1698 | #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) |
| paul@0 | 1699 | #define EMC_NFECC_ECC1_BIT 8 |
| paul@0 | 1700 | #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) |
| paul@0 | 1701 | #define EMC_NFECC_ECC0_BIT 0 |
| paul@0 | 1702 | #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) |
| paul@0 | 1703 | |
| paul@0 | 1704 | /* NAND Flash Interrupt Status Register */ |
| paul@0 | 1705 | #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ |
| paul@0 | 1706 | #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) |
| paul@0 | 1707 | #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ |
| paul@0 | 1708 | #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ |
| paul@0 | 1709 | #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ |
| paul@0 | 1710 | #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ |
| paul@0 | 1711 | #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ |
| paul@0 | 1712 | |
| paul@0 | 1713 | /* NAND Flash Interrupt Enable Register */ |
| paul@0 | 1714 | #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ |
| paul@0 | 1715 | #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ |
| paul@0 | 1716 | #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ |
| paul@0 | 1717 | #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ |
| paul@0 | 1718 | #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ |
| paul@0 | 1719 | |
| paul@0 | 1720 | /* NAND Flash RS Error Report Register */ |
| paul@0 | 1721 | #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ |
| paul@0 | 1722 | #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) |
| paul@0 | 1723 | #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ |
| paul@0 | 1724 | #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) |
| paul@0 | 1725 | |
| paul@0 | 1726 | |
| paul@0 | 1727 | /* DRAM Control Register */ |
| paul@0 | 1728 | #define EMC_DMCR_BW_BIT 31 |
| paul@0 | 1729 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) |
| paul@0 | 1730 | #define EMC_DMCR_CA_BIT 26 |
| paul@0 | 1731 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) |
| paul@0 | 1732 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) |
| paul@0 | 1733 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) |
| paul@0 | 1734 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) |
| paul@0 | 1735 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) |
| paul@0 | 1736 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) |
| paul@0 | 1737 | #define EMC_DMCR_RMODE (1 << 25) |
| paul@0 | 1738 | #define EMC_DMCR_RFSH (1 << 24) |
| paul@0 | 1739 | #define EMC_DMCR_MRSET (1 << 23) |
| paul@0 | 1740 | #define EMC_DMCR_RA_BIT 20 |
| paul@0 | 1741 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) |
| paul@0 | 1742 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) |
| paul@0 | 1743 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) |
| paul@0 | 1744 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) |
| paul@0 | 1745 | #define EMC_DMCR_BA_BIT 19 |
| paul@0 | 1746 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) |
| paul@0 | 1747 | #define EMC_DMCR_PDM (1 << 18) |
| paul@0 | 1748 | #define EMC_DMCR_EPIN (1 << 17) |
| paul@0 | 1749 | #define EMC_DMCR_TRAS_BIT 13 |
| paul@0 | 1750 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) |
| paul@0 | 1751 | #define EMC_DMCR_RCD_BIT 11 |
| paul@0 | 1752 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) |
| paul@0 | 1753 | #define EMC_DMCR_TPC_BIT 8 |
| paul@0 | 1754 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) |
| paul@0 | 1755 | #define EMC_DMCR_TRWL_BIT 5 |
| paul@0 | 1756 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) |
| paul@0 | 1757 | #define EMC_DMCR_TRC_BIT 2 |
| paul@0 | 1758 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) |
| paul@0 | 1759 | #define EMC_DMCR_TCL_BIT 0 |
| paul@0 | 1760 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) |
| paul@0 | 1761 | |
| paul@0 | 1762 | /* Refresh Time Control/Status Register */ |
| paul@0 | 1763 | #define EMC_RTCSR_CMF (1 << 7) |
| paul@0 | 1764 | #define EMC_RTCSR_CKS_BIT 0 |
| paul@0 | 1765 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1766 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1767 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1768 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1769 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1770 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1771 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1772 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1773 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) |
| paul@0 | 1774 | |
| paul@0 | 1775 | /* SDRAM Bank Address Configuration Register */ |
| paul@0 | 1776 | #define EMC_DMAR_BASE_BIT 8 |
| paul@0 | 1777 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) |
| paul@0 | 1778 | #define EMC_DMAR_MASK_BIT 0 |
| paul@0 | 1779 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) |
| paul@0 | 1780 | |
| paul@0 | 1781 | /* Mode Register of SDRAM bank 0 */ |
| paul@0 | 1782 | #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ |
| paul@0 | 1783 | #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ |
| paul@0 | 1784 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) |
| paul@0 | 1785 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) |
| paul@0 | 1786 | #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ |
| paul@0 | 1787 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) |
| paul@0 | 1788 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) |
| paul@0 | 1789 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) |
| paul@0 | 1790 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) |
| paul@0 | 1791 | #define EMC_SDMR_BT_BIT 3 /* Burst Type */ |
| paul@0 | 1792 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) |
| paul@0 | 1793 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ |
| paul@0 | 1794 | #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ |
| paul@0 | 1795 | #define EMC_SDMR_BL_BIT 0 /* Burst Length */ |
| paul@0 | 1796 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) |
| paul@0 | 1797 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) |
| paul@0 | 1798 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) |
| paul@0 | 1799 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) |
| paul@0 | 1800 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) |
| paul@0 | 1801 | |
| paul@0 | 1802 | #define EMC_SDMR_CAS2_16BIT \ |
| paul@0 | 1803 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| paul@0 | 1804 | #define EMC_SDMR_CAS2_32BIT \ |
| paul@0 | 1805 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| paul@0 | 1806 | #define EMC_SDMR_CAS3_16BIT \ |
| paul@0 | 1807 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| paul@0 | 1808 | #define EMC_SDMR_CAS3_32BIT \ |
| paul@0 | 1809 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| paul@0 | 1810 | |
| paul@0 | 1811 | /************************************************************************* |
| paul@0 | 1812 | * CIM |
| paul@0 | 1813 | *************************************************************************/ |
| paul@0 | 1814 | #define CIM_CFG (CIM_BASE + 0x0000) |
| paul@0 | 1815 | #define CIM_CTRL (CIM_BASE + 0x0004) |
| paul@0 | 1816 | #define CIM_STATE (CIM_BASE + 0x0008) |
| paul@0 | 1817 | #define CIM_IID (CIM_BASE + 0x000C) |
| paul@0 | 1818 | #define CIM_RXFIFO (CIM_BASE + 0x0010) |
| paul@0 | 1819 | #define CIM_DA (CIM_BASE + 0x0020) |
| paul@0 | 1820 | #define CIM_FA (CIM_BASE + 0x0024) |
| paul@0 | 1821 | #define CIM_FID (CIM_BASE + 0x0028) |
| paul@0 | 1822 | #define CIM_CMD (CIM_BASE + 0x002C) |
| paul@0 | 1823 | |
| paul@0 | 1824 | #define REG_CIM_CFG REG32(CIM_CFG) |
| paul@0 | 1825 | #define REG_CIM_CTRL REG32(CIM_CTRL) |
| paul@0 | 1826 | #define REG_CIM_STATE REG32(CIM_STATE) |
| paul@0 | 1827 | #define REG_CIM_IID REG32(CIM_IID) |
| paul@0 | 1828 | #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) |
| paul@0 | 1829 | #define REG_CIM_DA REG32(CIM_DA) |
| paul@0 | 1830 | #define REG_CIM_FA REG32(CIM_FA) |
| paul@0 | 1831 | #define REG_CIM_FID REG32(CIM_FID) |
| paul@0 | 1832 | #define REG_CIM_CMD REG32(CIM_CMD) |
| paul@0 | 1833 | |
| paul@0 | 1834 | /* CIM Configuration Register (CIM_CFG) */ |
| paul@0 | 1835 | |
| paul@0 | 1836 | #define CIM_CFG_INV_DAT (1 << 15) |
| paul@0 | 1837 | #define CIM_CFG_VSP (1 << 14) |
| paul@0 | 1838 | #define CIM_CFG_HSP (1 << 13) |
| paul@0 | 1839 | #define CIM_CFG_PCP (1 << 12) |
| paul@0 | 1840 | #define CIM_CFG_DUMMY_ZERO (1 << 9) |
| paul@0 | 1841 | #define CIM_CFG_EXT_VSYNC (1 << 8) |
| paul@0 | 1842 | #define CIM_CFG_PACK_BIT 4 |
| paul@0 | 1843 | #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) |
| paul@0 | 1844 | #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) |
| paul@0 | 1845 | #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) |
| paul@0 | 1846 | #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) |
| paul@0 | 1847 | #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) |
| paul@0 | 1848 | #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) |
| paul@0 | 1849 | #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) |
| paul@0 | 1850 | #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) |
| paul@0 | 1851 | #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) |
| paul@0 | 1852 | #define CIM_CFG_DSM_BIT 0 |
| paul@0 | 1853 | #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) |
| paul@0 | 1854 | #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ |
| paul@0 | 1855 | #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ |
| paul@0 | 1856 | #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ |
| paul@0 | 1857 | #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ |
| paul@0 | 1858 | |
| paul@0 | 1859 | /* CIM Control Register (CIM_CTRL) */ |
| paul@0 | 1860 | |
| paul@0 | 1861 | #define CIM_CTRL_MCLKDIV_BIT 24 |
| paul@0 | 1862 | #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) |
| paul@0 | 1863 | #define CIM_CTRL_FRC_BIT 16 |
| paul@0 | 1864 | #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) |
| paul@0 | 1865 | #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ |
| paul@0 | 1866 | #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ |
| paul@0 | 1867 | #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ |
| paul@0 | 1868 | #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ |
| paul@0 | 1869 | #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ |
| paul@0 | 1870 | #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ |
| paul@0 | 1871 | #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ |
| paul@0 | 1872 | #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ |
| paul@0 | 1873 | #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ |
| paul@0 | 1874 | #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ |
| paul@0 | 1875 | #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ |
| paul@0 | 1876 | #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ |
| paul@0 | 1877 | #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ |
| paul@0 | 1878 | #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ |
| paul@0 | 1879 | #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ |
| paul@0 | 1880 | #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ |
| paul@0 | 1881 | #define CIM_CTRL_VDDM (1 << 13) |
| paul@0 | 1882 | #define CIM_CTRL_DMA_SOFM (1 << 12) |
| paul@0 | 1883 | #define CIM_CTRL_DMA_EOFM (1 << 11) |
| paul@0 | 1884 | #define CIM_CTRL_DMA_STOPM (1 << 10) |
| paul@0 | 1885 | #define CIM_CTRL_RXF_TRIGM (1 << 9) |
| paul@0 | 1886 | #define CIM_CTRL_RXF_OFM (1 << 8) |
| paul@0 | 1887 | #define CIM_CTRL_RXF_TRIG_BIT 4 |
| paul@0 | 1888 | #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) |
| paul@0 | 1889 | #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ |
| paul@0 | 1890 | #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ |
| paul@0 | 1891 | #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ |
| paul@0 | 1892 | #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ |
| paul@0 | 1893 | #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ |
| paul@0 | 1894 | #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ |
| paul@0 | 1895 | #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ |
| paul@0 | 1896 | #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ |
| paul@0 | 1897 | #define CIM_CTRL_DMA_EN (1 << 2) |
| paul@0 | 1898 | #define CIM_CTRL_RXF_RST (1 << 1) |
| paul@0 | 1899 | #define CIM_CTRL_ENA (1 << 0) |
| paul@0 | 1900 | |
| paul@0 | 1901 | /* CIM State Register (CIM_STATE) */ |
| paul@0 | 1902 | |
| paul@0 | 1903 | #define CIM_STATE_DMA_SOF (1 << 6) |
| paul@0 | 1904 | #define CIM_STATE_DMA_EOF (1 << 5) |
| paul@0 | 1905 | #define CIM_STATE_DMA_STOP (1 << 4) |
| paul@0 | 1906 | #define CIM_STATE_RXF_OF (1 << 3) |
| paul@0 | 1907 | #define CIM_STATE_RXF_TRIG (1 << 2) |
| paul@0 | 1908 | #define CIM_STATE_RXF_EMPTY (1 << 1) |
| paul@0 | 1909 | #define CIM_STATE_VDD (1 << 0) |
| paul@0 | 1910 | |
| paul@0 | 1911 | /* CIM DMA Command Register (CIM_CMD) */ |
| paul@0 | 1912 | |
| paul@0 | 1913 | #define CIM_CMD_SOFINT (1 << 31) |
| paul@0 | 1914 | #define CIM_CMD_EOFINT (1 << 30) |
| paul@0 | 1915 | #define CIM_CMD_STOP (1 << 28) |
| paul@0 | 1916 | #define CIM_CMD_LEN_BIT 0 |
| paul@0 | 1917 | #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) |
| paul@0 | 1918 | |
| paul@0 | 1919 | |
| paul@0 | 1920 | /************************************************************************* |
| paul@0 | 1921 | * SADC (Smart A/D Controller) |
| paul@0 | 1922 | *************************************************************************/ |
| paul@0 | 1923 | |
| paul@0 | 1924 | #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ |
| paul@0 | 1925 | #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ |
| paul@0 | 1926 | #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ |
| paul@0 | 1927 | #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ |
| paul@0 | 1928 | #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ |
| paul@0 | 1929 | #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ |
| paul@0 | 1930 | #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ |
| paul@0 | 1931 | #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ |
| paul@0 | 1932 | #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ |
| paul@0 | 1933 | |
| paul@0 | 1934 | #define REG_SADC_ENA REG8(SADC_ENA) |
| paul@0 | 1935 | #define REG_SADC_CFG REG32(SADC_CFG) |
| paul@0 | 1936 | #define REG_SADC_CTRL REG8(SADC_CTRL) |
| paul@0 | 1937 | #define REG_SADC_STATE REG8(SADC_STATE) |
| paul@0 | 1938 | #define REG_SADC_SAMETIME REG16(SADC_SAMETIME) |
| paul@0 | 1939 | #define REG_SADC_WAITTIME REG16(SADC_WAITTIME) |
| paul@0 | 1940 | #define REG_SADC_TSDAT REG32(SADC_TSDAT) |
| paul@0 | 1941 | #define REG_SADC_BATDAT REG16(SADC_BATDAT) |
| paul@0 | 1942 | #define REG_SADC_SADDAT REG16(SADC_SADDAT) |
| paul@0 | 1943 | |
| paul@0 | 1944 | /* ADC Enable Register */ |
| paul@0 | 1945 | #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ |
| paul@0 | 1946 | #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ |
| paul@0 | 1947 | #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ |
| paul@0 | 1948 | #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ |
| paul@0 | 1949 | |
| paul@0 | 1950 | /* ADC Configure Register */ |
| paul@0 | 1951 | #define SADC_CFG_CLKOUT_NUM_BIT 16 |
| paul@0 | 1952 | #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) |
| paul@0 | 1953 | #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ |
| paul@0 | 1954 | #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ |
| paul@0 | 1955 | #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) |
| paul@0 | 1956 | #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) |
| paul@0 | 1957 | #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) |
| paul@0 | 1958 | #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) |
| paul@0 | 1959 | #define SADC_CFG_SNUM_BIT 10 /* Sample Number */ |
| paul@0 | 1960 | #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1961 | #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1962 | #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1963 | #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1964 | #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1965 | #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1966 | #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1967 | #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1968 | #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) |
| paul@0 | 1969 | #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ |
| paul@0 | 1970 | #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) |
| paul@0 | 1971 | #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ |
| paul@0 | 1972 | #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ |
| paul@0 | 1973 | #define SADC_CFG_CMD_BIT 0 /* ADC Command */ |
| paul@0 | 1974 | #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) |
| paul@0 | 1975 | #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ |
| paul@0 | 1976 | #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ |
| paul@0 | 1977 | #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ |
| paul@0 | 1978 | #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ |
| paul@0 | 1979 | #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ |
| paul@0 | 1980 | #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ |
| paul@0 | 1981 | #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ |
| paul@0 | 1982 | #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ |
| paul@0 | 1983 | #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ |
| paul@0 | 1984 | #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ |
| paul@0 | 1985 | #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ |
| paul@0 | 1986 | #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ |
| paul@0 | 1987 | #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ |
| paul@0 | 1988 | |
| paul@0 | 1989 | /* ADC Control Register */ |
| paul@0 | 1990 | #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ |
| paul@0 | 1991 | #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ |
| paul@0 | 1992 | #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ |
| paul@0 | 1993 | #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ |
| paul@0 | 1994 | #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ |
| paul@0 | 1995 | |
| paul@0 | 1996 | /* ADC Status Register */ |
| paul@0 | 1997 | #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ |
| paul@0 | 1998 | #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ |
| paul@0 | 1999 | #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ |
| paul@0 | 2000 | #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ |
| paul@0 | 2001 | #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ |
| paul@0 | 2002 | #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ |
| paul@0 | 2003 | #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ |
| paul@0 | 2004 | #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ |
| paul@0 | 2005 | |
| paul@0 | 2006 | /* ADC Touch Screen Data Register */ |
| paul@0 | 2007 | #define SADC_TSDAT_DATA0_BIT 0 |
| paul@0 | 2008 | #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) |
| paul@0 | 2009 | #define SADC_TSDAT_TYPE0 (1 << 15) |
| paul@0 | 2010 | #define SADC_TSDAT_DATA1_BIT 16 |
| paul@0 | 2011 | #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) |
| paul@0 | 2012 | #define SADC_TSDAT_TYPE1 (1 << 31) |
| paul@0 | 2013 | |
| paul@0 | 2014 | |
| paul@0 | 2015 | /************************************************************************* |
| paul@0 | 2016 | * SLCD (Smart LCD Controller) |
| paul@0 | 2017 | *************************************************************************/ |
| paul@0 | 2018 | |
| paul@0 | 2019 | #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ |
| paul@0 | 2020 | #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ |
| paul@0 | 2021 | #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ |
| paul@0 | 2022 | #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ |
| paul@0 | 2023 | #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ |
| paul@0 | 2024 | |
| paul@0 | 2025 | #define REG_SLCD_CFG REG32(SLCD_CFG) |
| paul@0 | 2026 | #define REG_SLCD_CTRL REG8(SLCD_CTRL) |
| paul@0 | 2027 | #define REG_SLCD_STATE REG8(SLCD_STATE) |
| paul@0 | 2028 | #define REG_SLCD_DATA REG32(SLCD_DATA) |
| paul@0 | 2029 | #define REG_SLCD_FIFO REG32(SLCD_FIFO) |
| paul@0 | 2030 | |
| paul@0 | 2031 | /* SLCD Configure Register */ |
| paul@0 | 2032 | #define SLCD_CFG_BURST_BIT 14 |
| paul@0 | 2033 | #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) |
| paul@0 | 2034 | #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) |
| paul@0 | 2035 | #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) |
| paul@0 | 2036 | #define SLCD_CFG_DWIDTH_BIT 10 |
| paul@0 | 2037 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) |
| paul@0 | 2038 | #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) |
| paul@0 | 2039 | #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) |
| paul@0 | 2040 | #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) |
| paul@0 | 2041 | #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) |
| paul@1 | 2042 | #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) |
| paul@0 | 2043 | #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) |
| paul@0 | 2044 | #define SLCD_CFG_CWIDTH_16BIT (0 << 8) |
| paul@0 | 2045 | #define SLCD_CFG_CWIDTH_8BIT (1 << 8) |
| paul@1 | 2046 | #define SLCD_CFG_CWIDTH_18BIT (2 << 8) |
| paul@0 | 2047 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) |
| paul@0 | 2048 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) |
| paul@0 | 2049 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) |
| paul@0 | 2050 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) |
| paul@0 | 2051 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) |
| paul@0 | 2052 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) |
| paul@0 | 2053 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) |
| paul@0 | 2054 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) |
| paul@0 | 2055 | |
| paul@0 | 2056 | /* SLCD Control Register */ |
| paul@0 | 2057 | #define SLCD_CTRL_DMA_EN (1 << 0) |
| paul@0 | 2058 | |
| paul@0 | 2059 | /* SLCD Status Register */ |
| paul@0 | 2060 | #define SLCD_STATE_BUSY (1 << 0) |
| paul@0 | 2061 | |
| paul@0 | 2062 | /* SLCD Data Register */ |
| paul@0 | 2063 | #define SLCD_DATA_RS_DATA (0 << 31) |
| paul@0 | 2064 | #define SLCD_DATA_RS_COMMAND (1 << 31) |
| paul@0 | 2065 | |
| paul@0 | 2066 | /* SLCD FIFO Register */ |
| paul@0 | 2067 | #define SLCD_FIFO_RS_DATA (0 << 31) |
| paul@0 | 2068 | #define SLCD_FIFO_RS_COMMAND (1 << 31) |
| paul@0 | 2069 | |
| paul@0 | 2070 | |
| paul@0 | 2071 | /************************************************************************* |
| paul@0 | 2072 | * LCD (LCD Controller) |
| paul@0 | 2073 | *************************************************************************/ |
| paul@0 | 2074 | #define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ |
| paul@0 | 2075 | #define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ |
| paul@0 | 2076 | #define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ |
| paul@0 | 2077 | #define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ |
| paul@0 | 2078 | #define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ |
| paul@0 | 2079 | #define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ |
| paul@0 | 2080 | #define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ |
| paul@0 | 2081 | #define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ |
| paul@0 | 2082 | #define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ |
| paul@0 | 2083 | #define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ |
| paul@0 | 2084 | #define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ |
| paul@0 | 2085 | #define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ |
| paul@0 | 2086 | #define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ |
| paul@0 | 2087 | #define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ |
| paul@0 | 2088 | #define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ |
| paul@0 | 2089 | #define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ |
| paul@0 | 2090 | #define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ |
| paul@0 | 2091 | #define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ |
| paul@0 | 2092 | #define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ |
| paul@0 | 2093 | #define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ |
| paul@0 | 2094 | #define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ |
| paul@0 | 2095 | |
| paul@0 | 2096 | #define REG_LCD_CFG REG32(LCD_CFG) |
| paul@0 | 2097 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) |
| paul@0 | 2098 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) |
| paul@0 | 2099 | #define REG_LCD_VAT REG32(LCD_VAT) |
| paul@0 | 2100 | #define REG_LCD_DAH REG32(LCD_DAH) |
| paul@0 | 2101 | #define REG_LCD_DAV REG32(LCD_DAV) |
| paul@0 | 2102 | #define REG_LCD_PS REG32(LCD_PS) |
| paul@0 | 2103 | #define REG_LCD_CLS REG32(LCD_CLS) |
| paul@0 | 2104 | #define REG_LCD_SPL REG32(LCD_SPL) |
| paul@0 | 2105 | #define REG_LCD_REV REG32(LCD_REV) |
| paul@0 | 2106 | #define REG_LCD_CTRL REG32(LCD_CTRL) |
| paul@0 | 2107 | #define REG_LCD_STATE REG32(LCD_STATE) |
| paul@0 | 2108 | #define REG_LCD_IID REG32(LCD_IID) |
| paul@0 | 2109 | #define REG_LCD_DA0 REG32(LCD_DA0) |
| paul@0 | 2110 | #define REG_LCD_SA0 REG32(LCD_SA0) |
| paul@0 | 2111 | #define REG_LCD_FID0 REG32(LCD_FID0) |
| paul@0 | 2112 | #define REG_LCD_CMD0 REG32(LCD_CMD0) |
| paul@0 | 2113 | #define REG_LCD_DA1 REG32(LCD_DA1) |
| paul@0 | 2114 | #define REG_LCD_SA1 REG32(LCD_SA1) |
| paul@0 | 2115 | #define REG_LCD_FID1 REG32(LCD_FID1) |
| paul@0 | 2116 | #define REG_LCD_CMD1 REG32(LCD_CMD1) |
| paul@0 | 2117 | |
| paul@0 | 2118 | /* LCD Configure Register */ |
| paul@0 | 2119 | #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ |
| paul@0 | 2120 | #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) |
| paul@0 | 2121 | #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) |
| paul@0 | 2122 | #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) |
| paul@0 | 2123 | #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ |
| paul@0 | 2124 | #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ |
| paul@0 | 2125 | #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ |
| paul@0 | 2126 | #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ |
| paul@0 | 2127 | #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ |
| paul@0 | 2128 | #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ |
| paul@0 | 2129 | #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ |
| paul@0 | 2130 | #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ |
| paul@0 | 2131 | #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ |
| paul@0 | 2132 | #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ |
| paul@0 | 2133 | #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ |
| paul@0 | 2134 | #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ |
| paul@0 | 2135 | #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ |
| paul@0 | 2136 | #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ |
| paul@0 | 2137 | #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ |
| paul@0 | 2138 | #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ |
| paul@0 | 2139 | #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ |
| paul@0 | 2140 | #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) |
| paul@0 | 2141 | #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ |
| paul@0 | 2142 | #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ |
| paul@0 | 2143 | #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ |
| paul@0 | 2144 | #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ |
| paul@0 | 2145 | #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ |
| paul@0 | 2146 | #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) |
| paul@0 | 2147 | #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ |
| paul@0 | 2148 | #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) |
| paul@0 | 2149 | #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) |
| paul@0 | 2150 | #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) |
| paul@0 | 2151 | #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) |
| paul@0 | 2152 | #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) |
| paul@0 | 2153 | #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) |
| paul@0 | 2154 | #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) |
| paul@0 | 2155 | #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) |
| paul@0 | 2156 | #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) |
| paul@0 | 2157 | #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) |
| paul@0 | 2158 | #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) |
| paul@0 | 2159 | /* JZ47XX defines */ |
| paul@0 | 2160 | #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) |
| paul@0 | 2161 | #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) |
| paul@0 | 2162 | #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) |
| paul@0 | 2163 | |
| paul@0 | 2164 | |
| paul@0 | 2165 | |
| paul@0 | 2166 | /* Vertical Synchronize Register */ |
| paul@0 | 2167 | #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ |
| paul@0 | 2168 | #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| paul@0 | 2169 | #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ |
| paul@0 | 2170 | #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| paul@0 | 2171 | |
| paul@0 | 2172 | /* Horizontal Synchronize Register */ |
| paul@0 | 2173 | #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ |
| paul@0 | 2174 | #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) |
| paul@0 | 2175 | #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ |
| paul@0 | 2176 | #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) |
| paul@0 | 2177 | |
| paul@0 | 2178 | /* Virtual Area Setting Register */ |
| paul@0 | 2179 | #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ |
| paul@0 | 2180 | #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) |
| paul@0 | 2181 | #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ |
| paul@0 | 2182 | #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) |
| paul@0 | 2183 | |
| paul@0 | 2184 | /* Display Area Horizontal Start/End Point Register */ |
| paul@0 | 2185 | #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ |
| paul@0 | 2186 | #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) |
| paul@0 | 2187 | #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ |
| paul@0 | 2188 | #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) |
| paul@0 | 2189 | |
| paul@0 | 2190 | /* Display Area Vertical Start/End Point Register */ |
| paul@0 | 2191 | #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ |
| paul@0 | 2192 | #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) |
| paul@0 | 2193 | #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ |
| paul@0 | 2194 | #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) |
| paul@0 | 2195 | |
| paul@0 | 2196 | /* PS Signal Setting */ |
| paul@0 | 2197 | #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ |
| paul@0 | 2198 | #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) |
| paul@0 | 2199 | #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ |
| paul@0 | 2200 | #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) |
| paul@0 | 2201 | |
| paul@0 | 2202 | /* CLS Signal Setting */ |
| paul@0 | 2203 | #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ |
| paul@0 | 2204 | #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) |
| paul@0 | 2205 | #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ |
| paul@0 | 2206 | #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) |
| paul@0 | 2207 | |
| paul@0 | 2208 | /* SPL Signal Setting */ |
| paul@0 | 2209 | #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ |
| paul@0 | 2210 | #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) |
| paul@0 | 2211 | #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ |
| paul@0 | 2212 | #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) |
| paul@0 | 2213 | |
| paul@0 | 2214 | /* REV Signal Setting */ |
| paul@0 | 2215 | #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ |
| paul@0 | 2216 | #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) |
| paul@0 | 2217 | |
| paul@0 | 2218 | /* LCD Control Register */ |
| paul@0 | 2219 | #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ |
| paul@0 | 2220 | #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) |
| paul@0 | 2221 | #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ |
| paul@0 | 2222 | #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ |
| paul@0 | 2223 | #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ |
| paul@0 | 2224 | #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ |
| paul@0 | 2225 | #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ |
| paul@0 | 2226 | #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ |
| paul@0 | 2227 | #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ |
| paul@0 | 2228 | #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) |
| paul@0 | 2229 | #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ |
| paul@0 | 2230 | #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ |
| paul@0 | 2231 | #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ |
| paul@0 | 2232 | #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ |
| paul@0 | 2233 | #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) |
| paul@0 | 2234 | #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ |
| paul@0 | 2235 | #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ |
| paul@0 | 2236 | #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ |
| paul@0 | 2237 | #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ |
| paul@0 | 2238 | #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ |
| paul@0 | 2239 | #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ |
| paul@0 | 2240 | #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ |
| paul@0 | 2241 | #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ |
| paul@0 | 2242 | #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ |
| paul@0 | 2243 | #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ |
| paul@0 | 2244 | #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ |
| paul@0 | 2245 | #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ |
| paul@0 | 2246 | #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) |
| paul@0 | 2247 | #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ |
| paul@0 | 2248 | #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ |
| paul@0 | 2249 | #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ |
| paul@0 | 2250 | #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ |
| paul@0 | 2251 | #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ |
| paul@0 | 2252 | #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ |
| paul@0 | 2253 | |
| paul@0 | 2254 | /* LCD Status Register */ |
| paul@0 | 2255 | #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ |
| paul@0 | 2256 | #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ |
| paul@0 | 2257 | #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ |
| paul@0 | 2258 | #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ |
| paul@0 | 2259 | #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ |
| paul@0 | 2260 | #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ |
| paul@0 | 2261 | #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ |
| paul@0 | 2262 | |
| paul@0 | 2263 | /* DMA Command Register */ |
| paul@0 | 2264 | #define LCD_CMD_SOFINT (1 << 31) |
| paul@0 | 2265 | #define LCD_CMD_EOFINT (1 << 30) |
| paul@0 | 2266 | #define LCD_CMD_PAL (1 << 28) |
| paul@0 | 2267 | #define LCD_CMD_LEN_BIT 0 |
| paul@0 | 2268 | #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) |
| paul@0 | 2269 | |
| paul@0 | 2270 | |
| paul@0 | 2271 | /************************************************************************* |
| paul@0 | 2272 | * USB Device |
| paul@0 | 2273 | *************************************************************************/ |
| paul@0 | 2274 | #define USB_BASE UDC_BASE |
| paul@0 | 2275 | |
| paul@0 | 2276 | #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ |
| paul@0 | 2277 | #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ |
| paul@0 | 2278 | #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ |
| paul@0 | 2279 | #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ |
| paul@0 | 2280 | #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ |
| paul@0 | 2281 | #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ |
| paul@0 | 2282 | #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ |
| paul@0 | 2283 | #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ |
| paul@0 | 2284 | #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ |
| paul@0 | 2285 | #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ |
| paul@0 | 2286 | #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ |
| paul@0 | 2287 | |
| paul@0 | 2288 | #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ |
| paul@0 | 2289 | #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ |
| paul@0 | 2290 | #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ |
| paul@0 | 2291 | #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ |
| paul@0 | 2292 | #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ |
| paul@0 | 2293 | #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ |
| paul@0 | 2294 | #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ |
| paul@0 | 2295 | #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ |
| paul@0 | 2296 | |
| paul@0 | 2297 | #define USB_FIFO_EP0 (USB_BASE + 0x20) |
| paul@0 | 2298 | #define USB_FIFO_EP1 (USB_BASE + 0x24) |
| paul@0 | 2299 | #define USB_FIFO_EP2 (USB_BASE + 0x28) |
| paul@0 | 2300 | |
| paul@0 | 2301 | #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ |
| paul@0 | 2302 | #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ |
| paul@0 | 2303 | |
| paul@0 | 2304 | #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ |
| paul@0 | 2305 | #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ |
| paul@0 | 2306 | #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ |
| paul@0 | 2307 | #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ |
| paul@0 | 2308 | #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ |
| paul@0 | 2309 | #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ |
| paul@0 | 2310 | #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ |
| paul@0 | 2311 | |
| paul@0 | 2312 | |
| paul@0 | 2313 | /* Power register bit masks */ |
| paul@0 | 2314 | #define USB_POWER_SUSPENDM 0x01 |
| paul@0 | 2315 | #define USB_POWER_RESUME 0x04 |
| paul@0 | 2316 | #define USB_POWER_HSMODE 0x10 |
| paul@0 | 2317 | #define USB_POWER_HSENAB 0x20 |
| paul@0 | 2318 | #define USB_POWER_SOFTCONN 0x40 |
| paul@0 | 2319 | |
| paul@0 | 2320 | /* Interrupt register bit masks */ |
| paul@0 | 2321 | #define USB_INTR_SUSPEND 0x01 |
| paul@0 | 2322 | #define USB_INTR_RESUME 0x02 |
| paul@0 | 2323 | #define USB_INTR_RESET 0x04 |
| paul@0 | 2324 | |
| paul@0 | 2325 | #define USB_INTR_EP0 0x0001 |
| paul@0 | 2326 | #define USB_INTR_INEP1 0x0002 |
| paul@0 | 2327 | #define USB_INTR_INEP2 0x0004 |
| paul@0 | 2328 | #define USB_INTR_OUTEP1 0x0002 |
| paul@0 | 2329 | |
| paul@0 | 2330 | /* CSR0 bit masks */ |
| paul@0 | 2331 | #define USB_CSR0_OUTPKTRDY 0x01 |
| paul@0 | 2332 | #define USB_CSR0_INPKTRDY 0x02 |
| paul@0 | 2333 | #define USB_CSR0_SENTSTALL 0x04 |
| paul@0 | 2334 | #define USB_CSR0_DATAEND 0x08 |
| paul@0 | 2335 | #define USB_CSR0_SETUPEND 0x10 |
| paul@0 | 2336 | #define USB_CSR0_SENDSTALL 0x20 |
| paul@0 | 2337 | #define USB_CSR0_SVDOUTPKTRDY 0x40 |
| paul@0 | 2338 | #define USB_CSR0_SVDSETUPEND 0x80 |
| paul@0 | 2339 | |
| paul@0 | 2340 | /* Endpoint CSR register bits */ |
| paul@0 | 2341 | #define USB_INCSRH_AUTOSET 0x80 |
| paul@0 | 2342 | #define USB_INCSRH_ISO 0x40 |
| paul@0 | 2343 | #define USB_INCSRH_MODE 0x20 |
| paul@0 | 2344 | #define USB_INCSRH_DMAREQENAB 0x10 |
| paul@0 | 2345 | #define USB_INCSRH_DMAREQMODE 0x04 |
| paul@0 | 2346 | #define USB_INCSR_CDT 0x40 |
| paul@0 | 2347 | #define USB_INCSR_SENTSTALL 0x20 |
| paul@0 | 2348 | #define USB_INCSR_SENDSTALL 0x10 |
| paul@0 | 2349 | #define USB_INCSR_FF 0x08 |
| paul@0 | 2350 | #define USB_INCSR_UNDERRUN 0x04 |
| paul@0 | 2351 | #define USB_INCSR_FFNOTEMPT 0x02 |
| paul@0 | 2352 | #define USB_INCSR_INPKTRDY 0x01 |
| paul@0 | 2353 | #define USB_OUTCSRH_AUTOCLR 0x80 |
| paul@0 | 2354 | #define USB_OUTCSRH_ISO 0x40 |
| paul@0 | 2355 | #define USB_OUTCSRH_DMAREQENAB 0x20 |
| paul@0 | 2356 | #define USB_OUTCSRH_DNYT 0x10 |
| paul@0 | 2357 | #define USB_OUTCSRH_DMAREQMODE 0x08 |
| paul@0 | 2358 | #define USB_OUTCSR_CDT 0x80 |
| paul@0 | 2359 | #define USB_OUTCSR_SENTSTALL 0x40 |
| paul@0 | 2360 | #define USB_OUTCSR_SENDSTALL 0x20 |
| paul@0 | 2361 | #define USB_OUTCSR_FF 0x10 |
| paul@0 | 2362 | #define USB_OUTCSR_DATAERR 0x08 |
| paul@0 | 2363 | #define USB_OUTCSR_OVERRUN 0x04 |
| paul@0 | 2364 | #define USB_OUTCSR_FFFULL 0x02 |
| paul@0 | 2365 | #define USB_OUTCSR_OUTPKTRDY 0x01 |
| paul@0 | 2366 | |
| paul@0 | 2367 | /* Testmode register bits */ |
| paul@0 | 2368 | #define USB_TEST_SE0NAK 0x01 |
| paul@0 | 2369 | #define USB_TEST_J 0x02 |
| paul@0 | 2370 | #define USB_TEST_K 0x04 |
| paul@0 | 2371 | #define USB_TEST_PACKET 0x08 |
| paul@0 | 2372 | |
| paul@0 | 2373 | /* DMA control bits */ |
| paul@0 | 2374 | #define USB_CNTL_ENA 0x01 |
| paul@0 | 2375 | #define USB_CNTL_DIR_IN 0x02 |
| paul@0 | 2376 | #define USB_CNTL_MODE_1 0x04 |
| paul@0 | 2377 | #define USB_CNTL_INTR_EN 0x08 |
| paul@0 | 2378 | #define USB_CNTL_EP(n) ((n) << 4) |
| paul@0 | 2379 | #define USB_CNTL_BURST_0 (0 << 9) |
| paul@0 | 2380 | #define USB_CNTL_BURST_4 (1 << 9) |
| paul@0 | 2381 | #define USB_CNTL_BURST_8 (2 << 9) |
| paul@0 | 2382 | #define USB_CNTL_BURST_16 (3 << 9) |
| paul@0 | 2383 | |
| paul@0 | 2384 | |
| paul@1 | 2385 | |
| paul@0 | 2386 | /* Module Operation Definitions */ |
| paul@0 | 2387 | #ifndef __ASSEMBLY__ |
| paul@0 | 2388 | |
| paul@1 | 2389 | |
| paul@1 | 2390 | /* GPIO Pins Description */ |
| paul@1 | 2391 | /* PORT 0: */ |
| paul@1 | 2392 | /* PIN/BIT N FUNC0 FUNC1 */ |
| paul@1 | 2393 | /* 0 D0 - */ |
| paul@1 | 2394 | /* 1 D1 - */ |
| paul@1 | 2395 | /* 2 D2 - */ |
| paul@1 | 2396 | /* 3 D3 - */ |
| paul@1 | 2397 | /* 4 D4 - */ |
| paul@1 | 2398 | /* 5 D5 - */ |
| paul@1 | 2399 | /* 6 D6 - */ |
| paul@1 | 2400 | /* 7 D7 - */ |
| paul@1 | 2401 | /* 8 D8 - */ |
| paul@1 | 2402 | /* 9 D9 - */ |
| paul@1 | 2403 | /* 10 D10 - */ |
| paul@1 | 2404 | /* 11 D11 - */ |
| paul@1 | 2405 | /* 12 D12 - */ |
| paul@1 | 2406 | /* 13 D13 - */ |
| paul@1 | 2407 | /* 14 D14 - */ |
| paul@1 | 2408 | /* 15 D15 - */ |
| paul@1 | 2409 | /* 16 D16 - */ |
| paul@1 | 2410 | /* 17 D17 - */ |
| paul@1 | 2411 | /* 18 D18 - */ |
| paul@1 | 2412 | /* 19 D19 - */ |
| paul@1 | 2413 | /* 20 D20 - */ |
| paul@1 | 2414 | /* 21 D21 - */ |
| paul@1 | 2415 | /* 22 D22 - */ |
| paul@1 | 2416 | /* 23 D23 - */ |
| paul@1 | 2417 | /* 24 D24 - */ |
| paul@1 | 2418 | /* 25 D25 - */ |
| paul@1 | 2419 | /* 26 D26 - */ |
| paul@1 | 2420 | /* 27 D27 - */ |
| paul@1 | 2421 | /* 28 D28 - */ |
| paul@1 | 2422 | /* 29 D29 - */ |
| paul@1 | 2423 | /* 30 D30 - */ |
| paul@1 | 2424 | /* 31 D31 - */ |
| paul@1 | 2425 | /*------------------------------------------------------ */ |
| paul@1 | 2426 | /* PORT 1: */ |
| paul@1 | 2427 | /* */ |
| paul@1 | 2428 | /* PIN/BIT N FUNC0 FUNC1 */ |
| paul@1 | 2429 | /* 0 A0 - */ |
| paul@1 | 2430 | /* 1 A1 - */ |
| paul@1 | 2431 | /* 2 A2 - */ |
| paul@1 | 2432 | /* 3 A3 - */ |
| paul@1 | 2433 | /* 4 A4 - */ |
| paul@1 | 2434 | /* 5 A5 - */ |
| paul@1 | 2435 | /* 6 A6 - */ |
| paul@1 | 2436 | /* 7 A7 - */ |
| paul@1 | 2437 | /* 8 A8 - */ |
| paul@1 | 2438 | /* 9 A9 - */ |
| paul@1 | 2439 | /* 10 A10 - */ |
| paul@1 | 2440 | /* 11 A11 - */ |
| paul@1 | 2441 | /* 12 A12 - */ |
| paul@1 | 2442 | /* 13 A13 - */ |
| paul@1 | 2443 | /* 14 A14 - */ |
| paul@1 | 2444 | /* 15 A15/CL - */ |
| paul@1 | 2445 | /* 16 A16/AL - */ |
| paul@1 | 2446 | /* 17 LCD_CLS A21 */ |
| paul@1 | 2447 | /* 18 LCD_SPL A22 */ |
| paul@1 | 2448 | /* 19 DCS# - */ |
| paul@1 | 2449 | /* 20 RAS# - */ |
| paul@1 | 2450 | /* 21 CAS# - */ |
| paul@1 | 2451 | /* 22 RDWE#/BUFD# - */ |
| paul@1 | 2452 | /* 23 CKE - */ |
| paul@1 | 2453 | /* 24 CKO - */ |
| paul@1 | 2454 | /* 25 CS1# - */ |
| paul@1 | 2455 | /* 26 CS2# - */ |
| paul@1 | 2456 | /* 27 CS3# - */ |
| paul@1 | 2457 | /* 28 CS4# - */ |
| paul@1 | 2458 | /* 29 RD# - */ |
| paul@1 | 2459 | /* 30 WR# - */ |
| paul@1 | 2460 | /* 31 WE0# - */ |
| paul@1 | 2461 | /* Note: PIN15&16 are CL&AL when connecting to NAND flash. */ |
| paul@1 | 2462 | /*------------------------------------------------------ */ |
| paul@1 | 2463 | /* PORT 2: */ |
| paul@1 | 2464 | /* */ |
| paul@1 | 2465 | /* PIN/BIT N FUNC0 FUNC1 */ |
| paul@1 | 2466 | /* 0 LCD_D0 - */ |
| paul@1 | 2467 | /* 1 LCD_D1 - */ |
| paul@1 | 2468 | /* 2 LCD_D2 - */ |
| paul@1 | 2469 | /* 3 LCD_D3 - */ |
| paul@1 | 2470 | /* 4 LCD_D4 - */ |
| paul@1 | 2471 | /* 5 LCD_D5 - */ |
| paul@1 | 2472 | /* 6 LCD_D6 - */ |
| paul@1 | 2473 | /* 7 LCD_D7 - */ |
| paul@1 | 2474 | /* 8 LCD_D8 - */ |
| paul@1 | 2475 | /* 9 LCD_D9 - */ |
| paul@1 | 2476 | /* 10 LCD_D10 - */ |
| paul@1 | 2477 | /* 11 LCD_D11 - */ |
| paul@1 | 2478 | /* 12 LCD_D12 - */ |
| paul@1 | 2479 | /* 13 LCD_D13 - */ |
| paul@1 | 2480 | /* 14 LCD_D14 - */ |
| paul@1 | 2481 | /* 15 LCD_D15 - */ |
| paul@1 | 2482 | /* 16 LCD_D16 - */ |
| paul@1 | 2483 | /* 17 LCD_D17 - */ |
| paul@1 | 2484 | /* 18 LCD_PCLK - */ |
| paul@1 | 2485 | /* 19 LCD_HSYNC - */ |
| paul@1 | 2486 | /* 20 LCD_VSYNC - */ |
| paul@1 | 2487 | /* 21 LCD_DE - */ |
| paul@1 | 2488 | /* 22 LCD_PS A19 */ |
| paul@1 | 2489 | /* 23 LCD_REV A20 */ |
| paul@1 | 2490 | /* 24 WE1# - */ |
| paul@1 | 2491 | /* 25 WE2# - */ |
| paul@1 | 2492 | /* 26 WE3# - */ |
| paul@1 | 2493 | /* 27 WAIT# - */ |
| paul@1 | 2494 | /* 28 FRE# - */ |
| paul@1 | 2495 | /* 29 FWE# - */ |
| paul@1 | 2496 | /* 30(NOTE:FRB#) - - */ |
| paul@1 | 2497 | /* 31 - - */ |
| paul@1 | 2498 | /* NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. */ |
| paul@1 | 2499 | /*------------------------------------------------------ */ |
| paul@1 | 2500 | /* PORT 3: */ |
| paul@1 | 2501 | /* */ |
| paul@1 | 2502 | /* PIN/BIT N FUNC0 FUNC1 */ |
| paul@1 | 2503 | /* 0 CIM_D0 - */ |
| paul@1 | 2504 | /* 1 CIM_D1 - */ |
| paul@1 | 2505 | /* 2 CIM_D2 - */ |
| paul@1 | 2506 | /* 3 CIM_D3 - */ |
| paul@1 | 2507 | /* 4 CIM_D4 - */ |
| paul@1 | 2508 | /* 5 CIM_D5 - */ |
| paul@1 | 2509 | /* 6 CIM_D6 - */ |
| paul@1 | 2510 | /* 7 CIM_D7 - */ |
| paul@1 | 2511 | /* 8 MSC_CMD - */ |
| paul@1 | 2512 | /* 9 MSC_CLK - */ |
| paul@1 | 2513 | /* 10 MSC_D0 - */ |
| paul@1 | 2514 | /* 11 MSC_D1 - */ |
| paul@1 | 2515 | /* 12 MSC_D2 - */ |
| paul@1 | 2516 | /* 13 MSC_D3 - */ |
| paul@1 | 2517 | /* 14 CIM_MCLK - */ |
| paul@1 | 2518 | /* 15 CIM_PCLK - */ |
| paul@1 | 2519 | /* 16 CIM_VSYNC - */ |
| paul@1 | 2520 | /* 17 CIM_HSYNC - */ |
| paul@1 | 2521 | /* 18 SSI_CLK SCLK_RSTN */ |
| paul@1 | 2522 | /* 19 SSI_CE0# BIT_CLK(AIC) */ |
| paul@1 | 2523 | /* 20 SSI_DT SDATA_OUT(AIC) */ |
| paul@1 | 2524 | /* 21 SSI_DR SDATA_IN(AIC) */ |
| paul@1 | 2525 | /* 22 SSI_CE1#&GPC SYNC(AIC) */ |
| paul@1 | 2526 | /* 23 PWM0 I2C_SDA */ |
| paul@1 | 2527 | /* 24 PWM1 I2C_SCK */ |
| paul@1 | 2528 | /* 25 PWM2 UART0_TxD */ |
| paul@1 | 2529 | /* 26 PWM3 UART0_RxD */ |
| paul@1 | 2530 | /* 27 PWM4 A17 */ |
| paul@1 | 2531 | /* 28 PWM5 A18 */ |
| paul@1 | 2532 | /* 29 - - */ |
| paul@1 | 2533 | /* 30 PWM6 UART0_CTS/UART1_RxD */ |
| paul@1 | 2534 | /* 31 PWM7 UART0_RTS/UART1_TxD */ |
| paul@0 | 2535 | /* |
| paul@0 | 2536 | * p is the port number (0,1,2,3) |
| paul@0 | 2537 | * o is the pin offset (0-31) inside the port |
| paul@0 | 2538 | * n is the absolute number of a pin (0-127), regardless of the port |
| paul@0 | 2539 | */ |
| paul@0 | 2540 | |
| paul@1 | 2541 | /* Function Pins Mode */ |
| paul@0 | 2542 | |
| paul@0 | 2543 | #define __gpio_as_func0(n) \ |
| paul@0 | 2544 | do { \ |
| paul@0 | 2545 | unsigned int p, o; \ |
| paul@0 | 2546 | p = (n) / 32; \ |
| paul@0 | 2547 | o = (n) % 32; \ |
| paul@0 | 2548 | REG_GPIO_PXFUNS(p) = (1 << o); \ |
| paul@0 | 2549 | REG_GPIO_PXSELC(p) = (1 << o); \ |
| paul@0 | 2550 | } while (0) |
| paul@0 | 2551 | |
| paul@0 | 2552 | #define __gpio_as_func1(n) \ |
| paul@0 | 2553 | do { \ |
| paul@0 | 2554 | unsigned int p, o; \ |
| paul@0 | 2555 | p = (n) / 32; \ |
| paul@0 | 2556 | o = (n) % 32; \ |
| paul@0 | 2557 | REG_GPIO_PXFUNS(p) = (1 << o); \ |
| paul@0 | 2558 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| paul@0 | 2559 | } while (0) |
| paul@0 | 2560 | |
| paul@0 | 2561 | /* |
| paul@0 | 2562 | * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, |
| paul@0 | 2563 | * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# |
| paul@0 | 2564 | */ |
| paul@0 | 2565 | #define __gpio_as_sdram_32bit() \ |
| paul@0 | 2566 | do { \ |
| paul@0 | 2567 | REG_GPIO_PXFUNS(0) = 0xffffffff; \ |
| paul@0 | 2568 | REG_GPIO_PXSELC(0) = 0xffffffff; \ |
| paul@0 | 2569 | REG_GPIO_PXPES(0) = 0xffffffff; \ |
| paul@0 | 2570 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ |
| paul@0 | 2571 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ |
| paul@0 | 2572 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ |
| paul@0 | 2573 | REG_GPIO_PXFUNS(2) = 0x07000000; \ |
| paul@0 | 2574 | REG_GPIO_PXSELC(2) = 0x07000000; \ |
| paul@0 | 2575 | REG_GPIO_PXPES(2) = 0x07000000; \ |
| paul@0 | 2576 | } while (0) |
| paul@0 | 2577 | |
| paul@0 | 2578 | /* |
| paul@0 | 2579 | * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, |
| paul@1 | 2580 | * RDWE#, CKO#, WE0#, WE1# |
| paul@0 | 2581 | */ |
| paul@1 | 2582 | #define __gpio_as_sdram_16bit_4720() \ |
| paul@0 | 2583 | do { \ |
| paul@0 | 2584 | REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ |
| paul@0 | 2585 | REG_GPIO_PXSELC(0) = 0x5442bfaa; \ |
| paul@0 | 2586 | REG_GPIO_PXPES(0) = 0x5442bfaa; \ |
| paul@0 | 2587 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ |
| paul@0 | 2588 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ |
| paul@0 | 2589 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ |
| paul@0 | 2590 | REG_GPIO_PXFUNS(2) = 0x01000000; \ |
| paul@0 | 2591 | REG_GPIO_PXSELC(2) = 0x01000000; \ |
| paul@0 | 2592 | REG_GPIO_PXPES(2) = 0x01000000; \ |
| paul@0 | 2593 | } while (0) |
| paul@0 | 2594 | |
| paul@0 | 2595 | /* |
| paul@1 | 2596 | * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, |
| paul@1 | 2597 | * RDWE#, CKO#, WE0#, WE1# |
| paul@1 | 2598 | */ |
| paul@1 | 2599 | #define __gpio_as_sdram_16bit_4725() \ |
| paul@1 | 2600 | do { \ |
| paul@1 | 2601 | REG_GPIO_PXFUNS(0) = 0x0000ffff; \ |
| paul@1 | 2602 | REG_GPIO_PXSELC(0) = 0x0000ffff; \ |
| paul@1 | 2603 | REG_GPIO_PXPES(0) = 0x0000ffff; \ |
| paul@1 | 2604 | REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ |
| paul@1 | 2605 | REG_GPIO_PXSELC(1) = 0x81f9ffff; \ |
| paul@1 | 2606 | REG_GPIO_PXPES(1) = 0x81f9ffff; \ |
| paul@1 | 2607 | REG_GPIO_PXFUNS(2) = 0x01000000; \ |
| paul@1 | 2608 | REG_GPIO_PXSELC(2) = 0x01000000; \ |
| paul@1 | 2609 | REG_GPIO_PXPES(2) = 0x01000000; \ |
| paul@1 | 2610 | } while (0) |
| paul@1 | 2611 | |
| paul@1 | 2612 | |
| paul@1 | 2613 | /* |
| paul@0 | 2614 | * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# |
| paul@0 | 2615 | */ |
| paul@0 | 2616 | #define __gpio_as_nand() \ |
| paul@0 | 2617 | do { \ |
| paul@0 | 2618 | REG_GPIO_PXFUNS(1) = 0x02018000; \ |
| paul@0 | 2619 | REG_GPIO_PXSELC(1) = 0x02018000; \ |
| paul@0 | 2620 | REG_GPIO_PXPES(1) = 0x02018000; \ |
| paul@0 | 2621 | REG_GPIO_PXFUNS(2) = 0x30000000; \ |
| paul@0 | 2622 | REG_GPIO_PXSELC(2) = 0x30000000; \ |
| paul@0 | 2623 | REG_GPIO_PXPES(2) = 0x30000000; \ |
| paul@0 | 2624 | REG_GPIO_PXFUNC(2) = 0x40000000; \ |
| paul@0 | 2625 | REG_GPIO_PXSELC(2) = 0x40000000; \ |
| paul@0 | 2626 | REG_GPIO_PXDIRC(2) = 0x40000000; \ |
| paul@0 | 2627 | REG_GPIO_PXPES(2) = 0x40000000; \ |
| paul@0 | 2628 | REG_GPIO_PXFUNS(1) = 0x00400000; \ |
| paul@0 | 2629 | REG_GPIO_PXSELC(1) = 0x00400000; \ |
| paul@0 | 2630 | } while (0) |
| paul@0 | 2631 | |
| paul@0 | 2632 | /* |
| paul@0 | 2633 | * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 |
| paul@0 | 2634 | */ |
| paul@0 | 2635 | #define __gpio_as_nor_8bit() \ |
| paul@0 | 2636 | do { \ |
| paul@0 | 2637 | REG_GPIO_PXFUNS(0) = 0x000000ff; \ |
| paul@0 | 2638 | REG_GPIO_PXSELC(0) = 0x000000ff; \ |
| paul@0 | 2639 | REG_GPIO_PXPES(0) = 0x000000ff; \ |
| paul@0 | 2640 | REG_GPIO_PXFUNS(1) = 0x7041ffff; \ |
| paul@0 | 2641 | REG_GPIO_PXSELC(1) = 0x7041ffff; \ |
| paul@0 | 2642 | REG_GPIO_PXPES(1) = 0x7041ffff; \ |
| paul@0 | 2643 | REG_GPIO_PXFUNS(1) = 0x00060000; \ |
| paul@0 | 2644 | REG_GPIO_PXSELS(1) = 0x00060000; \ |
| paul@0 | 2645 | REG_GPIO_PXPES(1) = 0x00060000; \ |
| paul@0 | 2646 | REG_GPIO_PXFUNS(2) = 0x08000000; \ |
| paul@0 | 2647 | REG_GPIO_PXSELC(2) = 0x08000000; \ |
| paul@0 | 2648 | REG_GPIO_PXPES(2) = 0x08000000; \ |
| paul@0 | 2649 | REG_GPIO_PXFUNS(2) = 0x00c00000; \ |
| paul@0 | 2650 | REG_GPIO_PXSELS(2) = 0x00c00000; \ |
| paul@0 | 2651 | REG_GPIO_PXPES(2) = 0x00c00000; \ |
| paul@0 | 2652 | REG_GPIO_PXFUNS(3) = 0x18000000; \ |
| paul@0 | 2653 | REG_GPIO_PXSELS(3) = 0x18000000; \ |
| paul@0 | 2654 | REG_GPIO_PXPES(3) = 0x18000000; \ |
| paul@0 | 2655 | } while (0) |
| paul@0 | 2656 | |
| paul@0 | 2657 | /* |
| paul@0 | 2658 | * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 |
| paul@0 | 2659 | */ |
| paul@0 | 2660 | #define __gpio_as_nor_16bit() \ |
| paul@0 | 2661 | do { \ |
| paul@0 | 2662 | REG_GPIO_PXFUNS(0) = 0x0000ffff; \ |
| paul@0 | 2663 | REG_GPIO_PXSELC(0) = 0x0000ffff; \ |
| paul@0 | 2664 | REG_GPIO_PXPES(0) = 0x0000ffff; \ |
| paul@0 | 2665 | REG_GPIO_PXFUNS(1) = 0x7041ffff; \ |
| paul@0 | 2666 | REG_GPIO_PXSELC(1) = 0x7041ffff; \ |
| paul@0 | 2667 | REG_GPIO_PXPES(1) = 0x7041ffff; \ |
| paul@0 | 2668 | REG_GPIO_PXFUNS(1) = 0x00060000; \ |
| paul@0 | 2669 | REG_GPIO_PXSELS(1) = 0x00060000; \ |
| paul@0 | 2670 | REG_GPIO_PXPES(1) = 0x00060000; \ |
| paul@0 | 2671 | REG_GPIO_PXFUNS(2) = 0x08000000; \ |
| paul@0 | 2672 | REG_GPIO_PXSELC(2) = 0x08000000; \ |
| paul@0 | 2673 | REG_GPIO_PXPES(2) = 0x08000000; \ |
| paul@0 | 2674 | REG_GPIO_PXFUNS(2) = 0x00c00000; \ |
| paul@0 | 2675 | REG_GPIO_PXSELS(2) = 0x00c00000; \ |
| paul@0 | 2676 | REG_GPIO_PXPES(2) = 0x00c00000; \ |
| paul@0 | 2677 | REG_GPIO_PXFUNS(3) = 0x18000000; \ |
| paul@0 | 2678 | REG_GPIO_PXSELS(3) = 0x18000000; \ |
| paul@0 | 2679 | REG_GPIO_PXPES(3) = 0x18000000; \ |
| paul@0 | 2680 | } while (0) |
| paul@0 | 2681 | |
| paul@0 | 2682 | /* |
| paul@0 | 2683 | * UART0_TxD, UART_RxD0 |
| paul@0 | 2684 | */ |
| paul@0 | 2685 | #define __gpio_as_uart0() \ |
| paul@0 | 2686 | do { \ |
| paul@0 | 2687 | REG_GPIO_PXFUNS(3) = 0x06000000; \ |
| paul@0 | 2688 | REG_GPIO_PXSELS(3) = 0x06000000; \ |
| paul@0 | 2689 | REG_GPIO_PXPES(3) = 0x06000000; \ |
| paul@0 | 2690 | } while (0) |
| paul@0 | 2691 | |
| paul@1 | 2692 | #define __gpio_jtag_to_uart0() \ |
| paul@1 | 2693 | do { \ |
| paul@1 | 2694 | REG_GPIO_PXSELS(2) = 0x80000000; \ |
| paul@1 | 2695 | } while (0) |
| paul@1 | 2696 | |
| paul@0 | 2697 | /* |
| paul@0 | 2698 | * UART0_CTS, UART0_RTS |
| paul@0 | 2699 | */ |
| paul@0 | 2700 | #define __gpio_as_ctsrts() \ |
| paul@0 | 2701 | do { \ |
| paul@0 | 2702 | REG_GPIO_PXFUNS(3) = 0xc0000000; \ |
| paul@0 | 2703 | REG_GPIO_PXSELS(3) = 0xc0000000; \ |
| paul@0 | 2704 | REG_GPIO_PXTRGC(3) = 0xc0000000; \ |
| paul@0 | 2705 | REG_GPIO_PXPES(3) = 0xc0000000; \ |
| paul@0 | 2706 | } while (0) |
| paul@0 | 2707 | |
| paul@0 | 2708 | /* |
| paul@0 | 2709 | * UART1_TxD, UART1_RxD1 |
| paul@0 | 2710 | */ |
| paul@0 | 2711 | #define __gpio_as_uart1() \ |
| paul@0 | 2712 | do { \ |
| paul@0 | 2713 | REG_GPIO_PXFUNS(3) = 0xc0000000; \ |
| paul@0 | 2714 | REG_GPIO_PXSELC(3) = 0xc0000000; \ |
| paul@0 | 2715 | REG_GPIO_PXTRGS(3) = 0xc0000000; \ |
| paul@0 | 2716 | REG_GPIO_PXPES(3) = 0xc0000000; \ |
| paul@0 | 2717 | } while (0) |
| paul@0 | 2718 | |
| paul@0 | 2719 | /* |
| paul@0 | 2720 | * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE |
| paul@0 | 2721 | */ |
| paul@0 | 2722 | #define __gpio_as_lcd_16bit() \ |
| paul@0 | 2723 | do { \ |
| paul@0 | 2724 | REG_GPIO_PXFUNS(2) = 0x003cffff; \ |
| paul@0 | 2725 | REG_GPIO_PXSELC(2) = 0x003cffff; \ |
| paul@0 | 2726 | REG_GPIO_PXPES(2) = 0x003cffff; \ |
| paul@0 | 2727 | } while (0) |
| paul@0 | 2728 | |
| paul@0 | 2729 | /* |
| paul@0 | 2730 | * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE |
| paul@0 | 2731 | */ |
| paul@0 | 2732 | #define __gpio_as_lcd_18bit() \ |
| paul@0 | 2733 | do { \ |
| paul@0 | 2734 | REG_GPIO_PXFUNS(2) = 0x003fffff; \ |
| paul@0 | 2735 | REG_GPIO_PXSELC(2) = 0x003fffff; \ |
| paul@0 | 2736 | REG_GPIO_PXPES(2) = 0x003fffff; \ |
| paul@0 | 2737 | } while (0) |
| paul@0 | 2738 | |
| paul@1 | 2739 | |
| paul@1 | 2740 | /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ |
| paul@1 | 2741 | #define __gpio_as_slcd_8bit() \ |
| paul@1 | 2742 | do { \ |
| paul@22 | 2743 | REG_GPIO_PXFUNS(2) = 0x001c00ff; \ |
| paul@22 | 2744 | REG_GPIO_PXSELC(2) = 0x001c00ff; \ |
| paul@1 | 2745 | } while (0) |
| paul@1 | 2746 | |
| paul@1 | 2747 | /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ |
| paul@1 | 2748 | #define __gpio_as_slcd_9bit() \ |
| paul@1 | 2749 | do { \ |
| paul@1 | 2750 | REG_GPIO_PXFUNS(2) = 0x001801ff; \ |
| paul@1 | 2751 | REG_GPIO_PXSELC(2) = 0x001801ff; \ |
| paul@1 | 2752 | } while (0) |
| paul@1 | 2753 | |
| paul@1 | 2754 | /* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */ |
| paul@1 | 2755 | #define __gpio_as_slcd_16bit() \ |
| paul@1 | 2756 | do { \ |
| paul@1 | 2757 | REG_GPIO_PXFUNS(2) = 0x0018ffff; \ |
| paul@1 | 2758 | REG_GPIO_PXSELC(2) = 0x0018ffff; \ |
| paul@1 | 2759 | } while (0) |
| paul@1 | 2760 | |
| paul@1 | 2761 | /* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */ |
| paul@1 | 2762 | #define __gpio_as_slcd_18bit() \ |
| paul@1 | 2763 | do { \ |
| paul@1 | 2764 | REG_GPIO_PXFUNS(2) = 0x001bffff; \ |
| paul@1 | 2765 | REG_GPIO_PXSELC(2) = 0x001bffff; \ |
| paul@1 | 2766 | } while (0) |
| paul@0 | 2767 | /* |
| paul@0 | 2768 | * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC |
| paul@0 | 2769 | */ |
| paul@0 | 2770 | #define __gpio_as_cim() \ |
| paul@0 | 2771 | do { \ |
| paul@0 | 2772 | REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ |
| paul@0 | 2773 | REG_GPIO_PXSELC(3) = 0x0003c0ff; \ |
| paul@0 | 2774 | REG_GPIO_PXPES(3) = 0x0003c0ff; \ |
| paul@0 | 2775 | } while (0) |
| paul@0 | 2776 | |
| paul@0 | 2777 | /* |
| paul@0 | 2778 | * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET |
| paul@0 | 2779 | */ |
| paul@0 | 2780 | #define __gpio_as_aic() \ |
| paul@0 | 2781 | do { \ |
| paul@0 | 2782 | REG_GPIO_PXFUNS(3) = 0x007c0000; \ |
| paul@0 | 2783 | REG_GPIO_PXSELS(3) = 0x007c0000; \ |
| paul@0 | 2784 | REG_GPIO_PXPES(3) = 0x007c0000; \ |
| paul@0 | 2785 | } while (0) |
| paul@0 | 2786 | |
| paul@0 | 2787 | /* |
| paul@0 | 2788 | * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 |
| paul@0 | 2789 | */ |
| paul@0 | 2790 | #define __gpio_as_msc() \ |
| paul@0 | 2791 | do { \ |
| paul@0 | 2792 | REG_GPIO_PXFUNS(3) = 0x00003f00; \ |
| paul@0 | 2793 | REG_GPIO_PXSELC(3) = 0x00003f00; \ |
| paul@0 | 2794 | REG_GPIO_PXPES(3) = 0x00003f00; \ |
| paul@0 | 2795 | } while (0) |
| paul@0 | 2796 | |
| paul@0 | 2797 | /* |
| paul@0 | 2798 | * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR |
| paul@0 | 2799 | */ |
| paul@0 | 2800 | #define __gpio_as_ssi() \ |
| paul@0 | 2801 | do { \ |
| paul@0 | 2802 | REG_GPIO_PXFUNS(3) = 0x003c0000; \ |
| paul@0 | 2803 | REG_GPIO_PXSELC(3) = 0x003c0000; \ |
| paul@0 | 2804 | REG_GPIO_PXPES(3) = 0x003c0000; \ |
| paul@0 | 2805 | } while (0) |
| paul@0 | 2806 | |
| paul@0 | 2807 | /* |
| paul@0 | 2808 | * I2C_SCK, I2C_SDA |
| paul@0 | 2809 | */ |
| paul@0 | 2810 | #define __gpio_as_i2c() \ |
| paul@0 | 2811 | do { \ |
| paul@0 | 2812 | REG_GPIO_PXFUNS(3) = 0x01800000; \ |
| paul@0 | 2813 | REG_GPIO_PXSELS(3) = 0x01800000; \ |
| paul@0 | 2814 | REG_GPIO_PXPES(3) = 0x01800000; \ |
| paul@0 | 2815 | } while (0) |
| paul@0 | 2816 | |
| paul@0 | 2817 | /* |
| paul@0 | 2818 | * PWM0 |
| paul@0 | 2819 | */ |
| paul@0 | 2820 | #define __gpio_as_pwm0() \ |
| paul@0 | 2821 | do { \ |
| paul@0 | 2822 | REG_GPIO_PXFUNS(3) = 0x00800000; \ |
| paul@0 | 2823 | REG_GPIO_PXSELC(3) = 0x00800000; \ |
| paul@0 | 2824 | REG_GPIO_PXPES(3) = 0x00800000; \ |
| paul@0 | 2825 | } while (0) |
| paul@0 | 2826 | |
| paul@0 | 2827 | /* |
| paul@0 | 2828 | * PWM1 |
| paul@0 | 2829 | */ |
| paul@0 | 2830 | #define __gpio_as_pwm1() \ |
| paul@0 | 2831 | do { \ |
| paul@0 | 2832 | REG_GPIO_PXFUNS(3) = 0x01000000; \ |
| paul@0 | 2833 | REG_GPIO_PXSELC(3) = 0x01000000; \ |
| paul@0 | 2834 | REG_GPIO_PXPES(3) = 0x01000000; \ |
| paul@0 | 2835 | } while (0) |
| paul@0 | 2836 | |
| paul@0 | 2837 | /* |
| paul@0 | 2838 | * PWM2 |
| paul@0 | 2839 | */ |
| paul@0 | 2840 | #define __gpio_as_pwm2() \ |
| paul@0 | 2841 | do { \ |
| paul@0 | 2842 | REG_GPIO_PXFUNS(3) = 0x02000000; \ |
| paul@0 | 2843 | REG_GPIO_PXSELC(3) = 0x02000000; \ |
| paul@0 | 2844 | REG_GPIO_PXPES(3) = 0x02000000; \ |
| paul@0 | 2845 | } while (0) |
| paul@0 | 2846 | |
| paul@0 | 2847 | /* |
| paul@0 | 2848 | * PWM3 |
| paul@0 | 2849 | */ |
| paul@0 | 2850 | #define __gpio_as_pwm3() \ |
| paul@0 | 2851 | do { \ |
| paul@0 | 2852 | REG_GPIO_PXFUNS(3) = 0x04000000; \ |
| paul@0 | 2853 | REG_GPIO_PXSELC(3) = 0x04000000; \ |
| paul@0 | 2854 | REG_GPIO_PXPES(3) = 0x04000000; \ |
| paul@0 | 2855 | } while (0) |
| paul@0 | 2856 | |
| paul@0 | 2857 | /* |
| paul@0 | 2858 | * PWM4 |
| paul@0 | 2859 | */ |
| paul@0 | 2860 | #define __gpio_as_pwm4() \ |
| paul@0 | 2861 | do { \ |
| paul@0 | 2862 | REG_GPIO_PXFUNS(3) = 0x08000000; \ |
| paul@0 | 2863 | REG_GPIO_PXSELC(3) = 0x08000000; \ |
| paul@0 | 2864 | REG_GPIO_PXPES(3) = 0x08000000; \ |
| paul@0 | 2865 | } while (0) |
| paul@0 | 2866 | |
| paul@0 | 2867 | /* |
| paul@0 | 2868 | * PWM5 |
| paul@0 | 2869 | */ |
| paul@0 | 2870 | #define __gpio_as_pwm5() \ |
| paul@0 | 2871 | do { \ |
| paul@0 | 2872 | REG_GPIO_PXFUNS(3) = 0x10000000; \ |
| paul@0 | 2873 | REG_GPIO_PXSELC(3) = 0x10000000; \ |
| paul@0 | 2874 | REG_GPIO_PXPES(3) = 0x10000000; \ |
| paul@0 | 2875 | } while (0) |
| paul@0 | 2876 | |
| paul@0 | 2877 | /* |
| paul@0 | 2878 | * PWM6 |
| paul@0 | 2879 | */ |
| paul@0 | 2880 | #define __gpio_as_pwm6() \ |
| paul@0 | 2881 | do { \ |
| paul@0 | 2882 | REG_GPIO_PXFUNS(3) = 0x40000000; \ |
| paul@0 | 2883 | REG_GPIO_PXSELC(3) = 0x40000000; \ |
| paul@0 | 2884 | REG_GPIO_PXPES(3) = 0x40000000; \ |
| paul@0 | 2885 | } while (0) |
| paul@0 | 2886 | |
| paul@0 | 2887 | /* |
| paul@0 | 2888 | * PWM7 |
| paul@0 | 2889 | */ |
| paul@0 | 2890 | #define __gpio_as_pwm7() \ |
| paul@0 | 2891 | do { \ |
| paul@0 | 2892 | REG_GPIO_PXFUNS(3) = 0x80000000; \ |
| paul@0 | 2893 | REG_GPIO_PXSELC(3) = 0x80000000; \ |
| paul@0 | 2894 | REG_GPIO_PXPES(3) = 0x80000000; \ |
| paul@0 | 2895 | } while (0) |
| paul@0 | 2896 | |
| paul@0 | 2897 | /* |
| paul@0 | 2898 | * n = 0 ~ 7 |
| paul@0 | 2899 | */ |
| paul@0 | 2900 | #define __gpio_as_pwm(n) __gpio_as_pwm##n() |
| paul@0 | 2901 | |
| paul@1 | 2902 | /* GPIO or Interrupt Mode */ |
| paul@0 | 2903 | |
| paul@0 | 2904 | #define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) |
| paul@0 | 2905 | |
| paul@0 | 2906 | #define __gpio_port_as_output(p, o) \ |
| paul@0 | 2907 | do { \ |
| paul@0 | 2908 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ |
| paul@0 | 2909 | REG_GPIO_PXSELC(p) = (1 << (o)); \ |
| paul@0 | 2910 | REG_GPIO_PXDIRS(p) = (1 << (o)); \ |
| paul@0 | 2911 | } while (0) |
| paul@0 | 2912 | |
| paul@0 | 2913 | #define __gpio_port_as_input(p, o) \ |
| paul@0 | 2914 | do { \ |
| paul@0 | 2915 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ |
| paul@0 | 2916 | REG_GPIO_PXSELC(p) = (1 << (o)); \ |
| paul@0 | 2917 | REG_GPIO_PXDIRC(p) = (1 << (o)); \ |
| paul@0 | 2918 | } while (0) |
| paul@0 | 2919 | |
| paul@0 | 2920 | #define __gpio_as_output(n) \ |
| paul@0 | 2921 | do { \ |
| paul@0 | 2922 | unsigned int p, o; \ |
| paul@0 | 2923 | p = (n) / 32; \ |
| paul@0 | 2924 | o = (n) % 32; \ |
| paul@0 | 2925 | __gpio_port_as_output(p, o); \ |
| paul@0 | 2926 | } while (0) |
| paul@0 | 2927 | |
| paul@0 | 2928 | #define __gpio_as_input(n) \ |
| paul@0 | 2929 | do { \ |
| paul@0 | 2930 | unsigned int p, o; \ |
| paul@0 | 2931 | p = (n) / 32; \ |
| paul@0 | 2932 | o = (n) % 32; \ |
| paul@0 | 2933 | __gpio_port_as_input(p, o); \ |
| paul@0 | 2934 | } while (0) |
| paul@0 | 2935 | |
| paul@0 | 2936 | #define __gpio_set_pin(n) \ |
| paul@0 | 2937 | do { \ |
| paul@0 | 2938 | unsigned int p, o; \ |
| paul@0 | 2939 | p = (n) / 32; \ |
| paul@0 | 2940 | o = (n) % 32; \ |
| paul@0 | 2941 | REG_GPIO_PXDATS(p) = (1 << o); \ |
| paul@0 | 2942 | } while (0) |
| paul@0 | 2943 | |
| paul@0 | 2944 | #define __gpio_clear_pin(n) \ |
| paul@0 | 2945 | do { \ |
| paul@0 | 2946 | unsigned int p, o; \ |
| paul@0 | 2947 | p = (n) / 32; \ |
| paul@0 | 2948 | o = (n) % 32; \ |
| paul@0 | 2949 | REG_GPIO_PXDATC(p) = (1 << o); \ |
| paul@0 | 2950 | } while (0) |
| paul@0 | 2951 | |
| paul@0 | 2952 | #define __gpio_get_pin(n) \ |
| paul@0 | 2953 | ({ \ |
| paul@0 | 2954 | unsigned int p, o, v; \ |
| paul@0 | 2955 | p = (n) / 32; \ |
| paul@0 | 2956 | o = (n) % 32; \ |
| paul@0 | 2957 | if (__gpio_get_port(p) & (1 << o)) \ |
| paul@0 | 2958 | v = 1; \ |
| paul@0 | 2959 | else \ |
| paul@0 | 2960 | v = 0; \ |
| paul@0 | 2961 | v; \ |
| paul@0 | 2962 | }) |
| paul@0 | 2963 | |
| paul@0 | 2964 | #define __gpio_as_irq_high_level(n) \ |
| paul@0 | 2965 | do { \ |
| paul@0 | 2966 | unsigned int p, o; \ |
| paul@0 | 2967 | p = (n) / 32; \ |
| paul@0 | 2968 | o = (n) % 32; \ |
| paul@0 | 2969 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| paul@0 | 2970 | REG_GPIO_PXTRGC(p) = (1 << o); \ |
| paul@0 | 2971 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| paul@0 | 2972 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| paul@0 | 2973 | REG_GPIO_PXDIRS(p) = (1 << o); \ |
| paul@0 | 2974 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| paul@0 | 2975 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| paul@0 | 2976 | } while (0) |
| paul@0 | 2977 | |
| paul@0 | 2978 | #define __gpio_as_irq_low_level(n) \ |
| paul@0 | 2979 | do { \ |
| paul@0 | 2980 | unsigned int p, o; \ |
| paul@0 | 2981 | p = (n) / 32; \ |
| paul@0 | 2982 | o = (n) % 32; \ |
| paul@0 | 2983 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| paul@0 | 2984 | REG_GPIO_PXTRGC(p) = (1 << o); \ |
| paul@0 | 2985 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| paul@0 | 2986 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| paul@0 | 2987 | REG_GPIO_PXDIRC(p) = (1 << o); \ |
| paul@0 | 2988 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| paul@0 | 2989 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| paul@0 | 2990 | } while (0) |
| paul@0 | 2991 | |
| paul@0 | 2992 | #define __gpio_as_irq_rise_edge(n) \ |
| paul@0 | 2993 | do { \ |
| paul@0 | 2994 | unsigned int p, o; \ |
| paul@0 | 2995 | p = (n) / 32; \ |
| paul@0 | 2996 | o = (n) % 32; \ |
| paul@0 | 2997 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| paul@0 | 2998 | REG_GPIO_PXTRGS(p) = (1 << o); \ |
| paul@0 | 2999 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| paul@0 | 3000 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| paul@0 | 3001 | REG_GPIO_PXDIRS(p) = (1 << o); \ |
| paul@0 | 3002 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| paul@0 | 3003 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| paul@0 | 3004 | } while (0) |
| paul@0 | 3005 | |
| paul@0 | 3006 | #define __gpio_as_irq_fall_edge(n) \ |
| paul@0 | 3007 | do { \ |
| paul@0 | 3008 | unsigned int p, o; \ |
| paul@0 | 3009 | p = (n) / 32; \ |
| paul@0 | 3010 | o = (n) % 32; \ |
| paul@0 | 3011 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| paul@0 | 3012 | REG_GPIO_PXTRGS(p) = (1 << o); \ |
| paul@0 | 3013 | REG_GPIO_PXFUNC(p) = (1 << o); \ |
| paul@0 | 3014 | REG_GPIO_PXSELS(p) = (1 << o); \ |
| paul@0 | 3015 | REG_GPIO_PXDIRC(p) = (1 << o); \ |
| paul@0 | 3016 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| paul@0 | 3017 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| paul@0 | 3018 | } while (0) |
| paul@0 | 3019 | |
| paul@0 | 3020 | #define __gpio_mask_irq(n) \ |
| paul@0 | 3021 | do { \ |
| paul@0 | 3022 | unsigned int p, o; \ |
| paul@0 | 3023 | p = (n) / 32; \ |
| paul@0 | 3024 | o = (n) % 32; \ |
| paul@0 | 3025 | REG_GPIO_PXIMS(p) = (1 << o); \ |
| paul@0 | 3026 | } while (0) |
| paul@0 | 3027 | |
| paul@0 | 3028 | #define __gpio_unmask_irq(n) \ |
| paul@0 | 3029 | do { \ |
| paul@0 | 3030 | unsigned int p, o; \ |
| paul@0 | 3031 | p = (n) / 32; \ |
| paul@0 | 3032 | o = (n) % 32; \ |
| paul@0 | 3033 | REG_GPIO_PXIMC(p) = (1 << o); \ |
| paul@0 | 3034 | } while (0) |
| paul@0 | 3035 | |
| paul@0 | 3036 | #define __gpio_ack_irq(n) \ |
| paul@0 | 3037 | do { \ |
| paul@0 | 3038 | unsigned int p, o; \ |
| paul@0 | 3039 | p = (n) / 32; \ |
| paul@0 | 3040 | o = (n) % 32; \ |
| paul@0 | 3041 | REG_GPIO_PXFLGC(p) = (1 << o); \ |
| paul@0 | 3042 | } while (0) |
| paul@0 | 3043 | |
| paul@0 | 3044 | #define __gpio_get_irq() \ |
| paul@0 | 3045 | ({ \ |
| paul@0 | 3046 | unsigned int p, i, tmp, v = 0; \ |
| paul@0 | 3047 | for (p = 3; p >= 0; p--) { \ |
| paul@0 | 3048 | tmp = REG_GPIO_PXFLG(p); \ |
| paul@0 | 3049 | for (i = 0; i < 32; i++) \ |
| paul@0 | 3050 | if (tmp & (1 << i)) \ |
| paul@0 | 3051 | v = (32*p + i); \ |
| paul@0 | 3052 | } \ |
| paul@0 | 3053 | v; \ |
| paul@0 | 3054 | }) |
| paul@0 | 3055 | |
| paul@0 | 3056 | #define __gpio_group_irq(n) \ |
| paul@0 | 3057 | ({ \ |
| paul@0 | 3058 | register int tmp, i; \ |
| paul@0 | 3059 | tmp = REG_GPIO_PXFLG((n)); \ |
| paul@0 | 3060 | for (i=31;i>=0;i--) \ |
| paul@0 | 3061 | if (tmp & (1 << i)) \ |
| paul@0 | 3062 | break; \ |
| paul@0 | 3063 | i; \ |
| paul@0 | 3064 | }) |
| paul@0 | 3065 | |
| paul@0 | 3066 | #define __gpio_enable_pull(n) \ |
| paul@0 | 3067 | do { \ |
| paul@0 | 3068 | unsigned int p, o; \ |
| paul@0 | 3069 | p = (n) / 32; \ |
| paul@0 | 3070 | o = (n) % 32; \ |
| paul@0 | 3071 | REG_GPIO_PXPEC(p) = (1 << o); \ |
| paul@0 | 3072 | } while (0) |
| paul@0 | 3073 | |
| paul@0 | 3074 | #define __gpio_disable_pull(n) \ |
| paul@0 | 3075 | do { \ |
| paul@0 | 3076 | unsigned int p, o; \ |
| paul@0 | 3077 | p = (n) / 32; \ |
| paul@0 | 3078 | o = (n) % 32; \ |
| paul@0 | 3079 | REG_GPIO_PXPES(p) = (1 << o); \ |
| paul@0 | 3080 | } while (0) |
| paul@0 | 3081 | |
| paul@0 | 3082 | |
| paul@0 | 3083 | /*************************************************************************** |
| paul@0 | 3084 | * CPM |
| paul@0 | 3085 | ***************************************************************************/ |
| paul@0 | 3086 | #define __cpm_get_pllm() \ |
| paul@0 | 3087 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) |
| paul@0 | 3088 | #define __cpm_get_plln() \ |
| paul@0 | 3089 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) |
| paul@0 | 3090 | #define __cpm_get_pllod() \ |
| paul@0 | 3091 | ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) |
| paul@0 | 3092 | |
| paul@0 | 3093 | #define __cpm_get_cdiv() \ |
| paul@0 | 3094 | ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) |
| paul@0 | 3095 | #define __cpm_get_hdiv() \ |
| paul@0 | 3096 | ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) |
| paul@0 | 3097 | #define __cpm_get_pdiv() \ |
| paul@0 | 3098 | ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) |
| paul@0 | 3099 | #define __cpm_get_mdiv() \ |
| paul@0 | 3100 | ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) |
| paul@0 | 3101 | #define __cpm_get_ldiv() \ |
| paul@0 | 3102 | ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) |
| paul@0 | 3103 | #define __cpm_get_udiv() \ |
| paul@0 | 3104 | ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) |
| paul@0 | 3105 | #define __cpm_get_i2sdiv() \ |
| paul@0 | 3106 | ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) |
| paul@0 | 3107 | #define __cpm_get_pixdiv() \ |
| paul@0 | 3108 | ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) |
| paul@0 | 3109 | #define __cpm_get_mscdiv() \ |
| paul@0 | 3110 | ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) |
| paul@0 | 3111 | |
| paul@0 | 3112 | #define __cpm_set_cdiv(v) \ |
| paul@0 | 3113 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) |
| paul@0 | 3114 | #define __cpm_set_hdiv(v) \ |
| paul@0 | 3115 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) |
| paul@0 | 3116 | #define __cpm_set_pdiv(v) \ |
| paul@0 | 3117 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) |
| paul@0 | 3118 | #define __cpm_set_mdiv(v) \ |
| paul@0 | 3119 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) |
| paul@0 | 3120 | #define __cpm_set_ldiv(v) \ |
| paul@0 | 3121 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) |
| paul@0 | 3122 | #define __cpm_set_udiv(v) \ |
| paul@0 | 3123 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) |
| paul@0 | 3124 | #define __cpm_set_i2sdiv(v) \ |
| paul@0 | 3125 | (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) |
| paul@0 | 3126 | #define __cpm_set_pixdiv(v) \ |
| paul@0 | 3127 | (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) |
| paul@0 | 3128 | #define __cpm_set_mscdiv(v) \ |
| paul@0 | 3129 | (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) |
| paul@0 | 3130 | |
| paul@0 | 3131 | #define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) |
| paul@0 | 3132 | #define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) |
| paul@0 | 3133 | #define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) |
| paul@0 | 3134 | #define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) |
| paul@0 | 3135 | #define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) |
| paul@0 | 3136 | #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) |
| paul@0 | 3137 | #define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) |
| paul@0 | 3138 | #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) |
| paul@0 | 3139 | |
| paul@0 | 3140 | #define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) |
| paul@0 | 3141 | #define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) |
| paul@0 | 3142 | #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) |
| paul@0 | 3143 | |
| paul@0 | 3144 | #define __cpm_get_cclk_doze_duty() \ |
| paul@0 | 3145 | ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) |
| paul@0 | 3146 | #define __cpm_set_cclk_doze_duty(v) \ |
| paul@0 | 3147 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) |
| paul@0 | 3148 | |
| paul@0 | 3149 | #define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) |
| paul@0 | 3150 | #define __cpm_idle_mode() \ |
| paul@0 | 3151 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) |
| paul@0 | 3152 | #define __cpm_sleep_mode() \ |
| paul@0 | 3153 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) |
| paul@0 | 3154 | |
| paul@0 | 3155 | #define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) |
| paul@0 | 3156 | #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) |
| paul@0 | 3157 | #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) |
| paul@0 | 3158 | #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) |
| paul@0 | 3159 | #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) |
| paul@0 | 3160 | #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) |
| paul@0 | 3161 | #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) |
| paul@0 | 3162 | #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) |
| paul@0 | 3163 | #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) |
| paul@0 | 3164 | #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) |
| paul@0 | 3165 | #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) |
| paul@0 | 3166 | #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) |
| paul@0 | 3167 | #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) |
| paul@0 | 3168 | #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) |
| paul@0 | 3169 | #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) |
| paul@0 | 3170 | #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) |
| paul@0 | 3171 | #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) |
| paul@0 | 3172 | |
| paul@0 | 3173 | #define __cpm_start_all() (REG_CPM_CLKGR = 0x0) |
| paul@0 | 3174 | #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) |
| paul@0 | 3175 | #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) |
| paul@0 | 3176 | #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) |
| paul@0 | 3177 | #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) |
| paul@0 | 3178 | #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) |
| paul@0 | 3179 | #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) |
| paul@0 | 3180 | #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) |
| paul@0 | 3181 | #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) |
| paul@0 | 3182 | #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) |
| paul@0 | 3183 | #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) |
| paul@0 | 3184 | #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) |
| paul@0 | 3185 | #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) |
| paul@0 | 3186 | #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) |
| paul@0 | 3187 | #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) |
| paul@0 | 3188 | #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) |
| paul@0 | 3189 | #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) |
| paul@0 | 3190 | |
| paul@0 | 3191 | #define __cpm_get_o1st() \ |
| paul@0 | 3192 | ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) |
| paul@0 | 3193 | #define __cpm_set_o1st(v) \ |
| paul@0 | 3194 | (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) |
| paul@1 | 3195 | #define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE) |
| paul@1 | 3196 | #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE) |
| paul@0 | 3197 | #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) |
| paul@0 | 3198 | |
| paul@9 | 3199 | /* NOTE: Independent of usbboot parameters. */ |
| paul@9 | 3200 | |
| paul@9 | 3201 | #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ |
| paul@9 | 3202 | #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ |
| paul@9 | 3203 | #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ |
| paul@1 | 3204 | #define JZ_EXTAL CONFIG_SYS_EXTAL |
| paul@0 | 3205 | #define JZ_EXTAL2 32768 /* RTC clock */ |
| paul@0 | 3206 | |
| paul@0 | 3207 | /* PLL output frequency */ |
| paul@0 | 3208 | static __inline__ unsigned int __cpm_get_pllout(void) |
| paul@0 | 3209 | { |
| paul@0 | 3210 | unsigned long m, n, no, pllout; |
| paul@0 | 3211 | unsigned long cppcr = REG_CPM_CPPCR; |
| paul@0 | 3212 | unsigned long od[4] = {1, 2, 2, 4}; |
| paul@0 | 3213 | if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { |
| paul@0 | 3214 | m = __cpm_get_pllm() + 2; |
| paul@0 | 3215 | n = __cpm_get_plln() + 2; |
| paul@0 | 3216 | no = od[__cpm_get_pllod()]; |
| paul@0 | 3217 | pllout = ((JZ_EXTAL) / (n * no)) * m; |
| paul@0 | 3218 | } else |
| paul@0 | 3219 | pllout = JZ_EXTAL; |
| paul@0 | 3220 | return pllout; |
| paul@0 | 3221 | } |
| paul@0 | 3222 | |
| paul@0 | 3223 | /* PLL output frequency for MSC/I2S/LCD/USB */ |
| paul@0 | 3224 | static __inline__ unsigned int __cpm_get_pllout2(void) |
| paul@0 | 3225 | { |
| paul@0 | 3226 | if (REG_CPM_CPCCR & CPM_CPCCR_PCS) |
| paul@0 | 3227 | return __cpm_get_pllout(); |
| paul@0 | 3228 | else |
| paul@0 | 3229 | return __cpm_get_pllout()/2; |
| paul@0 | 3230 | } |
| paul@0 | 3231 | |
| paul@0 | 3232 | /* CPU core clock */ |
| paul@0 | 3233 | static __inline__ unsigned int __cpm_get_cclk(void) |
| paul@0 | 3234 | { |
| paul@0 | 3235 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| paul@0 | 3236 | |
| paul@0 | 3237 | return __cpm_get_pllout() / div[__cpm_get_cdiv()]; |
| paul@0 | 3238 | } |
| paul@0 | 3239 | |
| paul@0 | 3240 | /* AHB system bus clock */ |
| paul@0 | 3241 | static __inline__ unsigned int __cpm_get_hclk(void) |
| paul@0 | 3242 | { |
| paul@0 | 3243 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| paul@0 | 3244 | |
| paul@0 | 3245 | return __cpm_get_pllout() / div[__cpm_get_hdiv()]; |
| paul@0 | 3246 | } |
| paul@0 | 3247 | |
| paul@0 | 3248 | /* Memory bus clock */ |
| paul@0 | 3249 | static __inline__ unsigned int __cpm_get_mclk(void) |
| paul@0 | 3250 | { |
| paul@0 | 3251 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| paul@0 | 3252 | |
| paul@0 | 3253 | return __cpm_get_pllout() / div[__cpm_get_mdiv()]; |
| paul@0 | 3254 | } |
| paul@0 | 3255 | |
| paul@0 | 3256 | /* APB peripheral bus clock */ |
| paul@0 | 3257 | static __inline__ unsigned int __cpm_get_pclk(void) |
| paul@0 | 3258 | { |
| paul@0 | 3259 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| paul@0 | 3260 | |
| paul@0 | 3261 | return __cpm_get_pllout() / div[__cpm_get_pdiv()]; |
| paul@0 | 3262 | } |
| paul@0 | 3263 | |
| paul@0 | 3264 | /* LCDC module clock */ |
| paul@0 | 3265 | static __inline__ unsigned int __cpm_get_lcdclk(void) |
| paul@0 | 3266 | { |
| paul@0 | 3267 | return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); |
| paul@0 | 3268 | } |
| paul@0 | 3269 | |
| paul@0 | 3270 | /* LCD pixel clock */ |
| paul@0 | 3271 | static __inline__ unsigned int __cpm_get_pixclk(void) |
| paul@0 | 3272 | { |
| paul@0 | 3273 | return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); |
| paul@0 | 3274 | } |
| paul@0 | 3275 | |
| paul@0 | 3276 | /* I2S clock */ |
| paul@0 | 3277 | static __inline__ unsigned int __cpm_get_i2sclk(void) |
| paul@0 | 3278 | { |
| paul@0 | 3279 | if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { |
| paul@0 | 3280 | return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); |
| paul@0 | 3281 | } |
| paul@0 | 3282 | else { |
| paul@0 | 3283 | return JZ_EXTAL; |
| paul@0 | 3284 | } |
| paul@0 | 3285 | } |
| paul@0 | 3286 | |
| paul@0 | 3287 | /* USB clock */ |
| paul@0 | 3288 | static __inline__ unsigned int __cpm_get_usbclk(void) |
| paul@0 | 3289 | { |
| paul@0 | 3290 | if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { |
| paul@0 | 3291 | return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); |
| paul@0 | 3292 | } |
| paul@0 | 3293 | else { |
| paul@0 | 3294 | return JZ_EXTAL; |
| paul@0 | 3295 | } |
| paul@0 | 3296 | } |
| paul@0 | 3297 | |
| paul@0 | 3298 | /* MSC clock */ |
| paul@0 | 3299 | static __inline__ unsigned int __cpm_get_mscclk(void) |
| paul@0 | 3300 | { |
| paul@0 | 3301 | return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); |
| paul@0 | 3302 | } |
| paul@0 | 3303 | |
| paul@0 | 3304 | /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ |
| paul@0 | 3305 | static __inline__ unsigned int __cpm_get_extalclk(void) |
| paul@0 | 3306 | { |
| paul@0 | 3307 | return JZ_EXTAL; |
| paul@0 | 3308 | } |
| paul@0 | 3309 | |
| paul@0 | 3310 | /* RTC clock for CPM,INTC,RTC,TCU,WDT */ |
| paul@0 | 3311 | static __inline__ unsigned int __cpm_get_rtcclk(void) |
| paul@0 | 3312 | { |
| paul@0 | 3313 | return JZ_EXTAL2; |
| paul@0 | 3314 | } |
| paul@0 | 3315 | |
| paul@0 | 3316 | /* |
| paul@0 | 3317 | * Output 24MHz for SD and 16MHz for MMC. |
| paul@0 | 3318 | */ |
| paul@0 | 3319 | static inline void __cpm_select_msc_clk(int sd) |
| paul@0 | 3320 | { |
| paul@0 | 3321 | unsigned int pllout2 = __cpm_get_pllout2(); |
| paul@0 | 3322 | unsigned int div = 0; |
| paul@0 | 3323 | |
| paul@0 | 3324 | if (sd) { |
| paul@0 | 3325 | div = pllout2 / 24000000; |
| paul@0 | 3326 | } |
| paul@0 | 3327 | else { |
| paul@0 | 3328 | div = pllout2 / 16000000; |
| paul@0 | 3329 | } |
| paul@0 | 3330 | |
| paul@0 | 3331 | REG_CPM_MSCCDR = div - 1; |
| paul@0 | 3332 | } |
| paul@0 | 3333 | |
| paul@1 | 3334 | /* |
| paul@0 | 3335 | * TCU |
| paul@1 | 3336 | */ |
| paul@1 | 3337 | /* where 'n' is the TCU channel */ |
| paul@0 | 3338 | #define __tcu_select_extalclk(n) \ |
| paul@0 | 3339 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) |
| paul@0 | 3340 | #define __tcu_select_rtcclk(n) \ |
| paul@0 | 3341 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) |
| paul@0 | 3342 | #define __tcu_select_pclk(n) \ |
| paul@0 | 3343 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) |
| paul@0 | 3344 | |
| paul@0 | 3345 | #define __tcu_select_clk_div1(n) \ |
| paul@0 | 3346 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) |
| paul@0 | 3347 | #define __tcu_select_clk_div4(n) \ |
| paul@0 | 3348 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) |
| paul@0 | 3349 | #define __tcu_select_clk_div16(n) \ |
| paul@0 | 3350 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) |
| paul@0 | 3351 | #define __tcu_select_clk_div64(n) \ |
| paul@0 | 3352 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) |
| paul@0 | 3353 | #define __tcu_select_clk_div256(n) \ |
| paul@0 | 3354 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) |
| paul@0 | 3355 | #define __tcu_select_clk_div1024(n) \ |
| paul@0 | 3356 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) |
| paul@0 | 3357 | |
| paul@0 | 3358 | #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) |
| paul@0 | 3359 | #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) |
| paul@0 | 3360 | |
| paul@0 | 3361 | #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) |
| paul@0 | 3362 | #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) |
| paul@0 | 3363 | |
| paul@0 | 3364 | #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) |
| paul@0 | 3365 | #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) |
| paul@0 | 3366 | |
| paul@0 | 3367 | #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) |
| paul@0 | 3368 | #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) |
| paul@0 | 3369 | |
| paul@0 | 3370 | #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) |
| paul@0 | 3371 | #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) |
| paul@0 | 3372 | #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) |
| paul@0 | 3373 | #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) |
| paul@0 | 3374 | #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) |
| paul@0 | 3375 | #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) |
| paul@0 | 3376 | #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) |
| paul@0 | 3377 | #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) |
| paul@0 | 3378 | #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) |
| paul@0 | 3379 | #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) |
| paul@0 | 3380 | |
| paul@0 | 3381 | #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) |
| paul@0 | 3382 | #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) |
| paul@0 | 3383 | |
| paul@0 | 3384 | #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) |
| paul@0 | 3385 | #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) |
| paul@0 | 3386 | |
| paul@0 | 3387 | #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) |
| paul@0 | 3388 | #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) |
| paul@0 | 3389 | |
| paul@0 | 3390 | #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) |
| paul@0 | 3391 | #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) |
| paul@0 | 3392 | #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) |
| paul@0 | 3393 | #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) |
| paul@0 | 3394 | |
| paul@0 | 3395 | |
| paul@0 | 3396 | /*************************************************************************** |
| paul@0 | 3397 | * WDT |
| paul@0 | 3398 | ***************************************************************************/ |
| paul@0 | 3399 | #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) |
| paul@0 | 3400 | #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) |
| paul@0 | 3401 | #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) |
| paul@0 | 3402 | #define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) |
| paul@0 | 3403 | |
| paul@0 | 3404 | #define __wdt_select_extalclk() \ |
| paul@0 | 3405 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) |
| paul@0 | 3406 | #define __wdt_select_rtcclk() \ |
| paul@0 | 3407 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) |
| paul@0 | 3408 | #define __wdt_select_pclk() \ |
| paul@0 | 3409 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) |
| paul@0 | 3410 | |
| paul@0 | 3411 | #define __wdt_select_clk_div1() \ |
| paul@0 | 3412 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) |
| paul@0 | 3413 | #define __wdt_select_clk_div4() \ |
| paul@0 | 3414 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) |
| paul@0 | 3415 | #define __wdt_select_clk_div16() \ |
| paul@0 | 3416 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) |
| paul@0 | 3417 | #define __wdt_select_clk_div64() \ |
| paul@0 | 3418 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) |
| paul@0 | 3419 | #define __wdt_select_clk_div256() \ |
| paul@0 | 3420 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) |
| paul@0 | 3421 | #define __wdt_select_clk_div1024() \ |
| paul@0 | 3422 | (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) |
| paul@0 | 3423 | |
| paul@0 | 3424 | |
| paul@0 | 3425 | /*************************************************************************** |
| paul@0 | 3426 | * UART |
| paul@0 | 3427 | ***************************************************************************/ |
| paul@0 | 3428 | |
| paul@0 | 3429 | #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) |
| paul@0 | 3430 | #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) |
| paul@0 | 3431 | |
| paul@0 | 3432 | #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) |
| paul@0 | 3433 | #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) |
| paul@0 | 3434 | |
| paul@0 | 3435 | #define __uart_enable_receive_irq() \ |
| paul@0 | 3436 | ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) |
| paul@0 | 3437 | #define __uart_disable_receive_irq() \ |
| paul@0 | 3438 | ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) |
| paul@0 | 3439 | |
| paul@0 | 3440 | #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) |
| paul@0 | 3441 | #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) |
| paul@0 | 3442 | |
| paul@0 | 3443 | #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) |
| paul@0 | 3444 | |
| paul@0 | 3445 | #define __uart_set_baud(devclk, baud) \ |
| paul@0 | 3446 | do { \ |
| paul@0 | 3447 | REG8(UART0_LCR) |= UARTLCR_DLAB; \ |
| paul@0 | 3448 | REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ |
| paul@0 | 3449 | REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ |
| paul@0 | 3450 | REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ |
| paul@0 | 3451 | } while (0) |
| paul@0 | 3452 | |
| paul@0 | 3453 | #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) |
| paul@0 | 3454 | #define __uart_clear_errors() \ |
| paul@0 | 3455 | ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) |
| paul@0 | 3456 | |
| paul@0 | 3457 | #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) |
| paul@0 | 3458 | #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) |
| paul@0 | 3459 | #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) |
| paul@0 | 3460 | #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) |
| paul@0 | 3461 | #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) |
| paul@0 | 3462 | #define __uart_receive_char() REG8(UART0_RDR) |
| paul@0 | 3463 | #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) |
| paul@0 | 3464 | #define __uart_enable_irda() \ |
| paul@0 | 3465 | /* Tx high pulse as 0, Rx low pulse as 0 */ \ |
| paul@0 | 3466 | ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) |
| paul@0 | 3467 | |
| paul@0 | 3468 | |
| paul@0 | 3469 | /*************************************************************************** |
| paul@0 | 3470 | * DMAC |
| paul@0 | 3471 | ***************************************************************************/ |
| paul@0 | 3472 | |
| paul@0 | 3473 | /* n is the DMA channel (0 - 5) */ |
| paul@0 | 3474 | |
| paul@0 | 3475 | #define __dmac_enable_module() \ |
| paul@0 | 3476 | ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) |
| paul@0 | 3477 | #define __dmac_disable_module() \ |
| paul@0 | 3478 | ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) |
| paul@0 | 3479 | |
| paul@0 | 3480 | /* p=0,1,2,3 */ |
| paul@0 | 3481 | #define __dmac_set_priority(p) \ |
| paul@0 | 3482 | do { \ |
| paul@0 | 3483 | REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ |
| paul@0 | 3484 | REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ |
| paul@0 | 3485 | } while (0) |
| paul@0 | 3486 | |
| paul@0 | 3487 | #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) |
| paul@0 | 3488 | #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) |
| paul@0 | 3489 | |
| paul@0 | 3490 | #define __dmac_enable_descriptor(n) \ |
| paul@0 | 3491 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) |
| paul@0 | 3492 | #define __dmac_disable_descriptor(n) \ |
| paul@0 | 3493 | ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) |
| paul@0 | 3494 | |
| paul@0 | 3495 | #define __dmac_enable_channel(n) \ |
| paul@0 | 3496 | ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) |
| paul@0 | 3497 | #define __dmac_disable_channel(n) \ |
| paul@0 | 3498 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) |
| paul@0 | 3499 | #define __dmac_channel_enabled(n) \ |
| paul@0 | 3500 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) |
| paul@0 | 3501 | |
| paul@0 | 3502 | #define __dmac_channel_enable_irq(n) \ |
| paul@0 | 3503 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) |
| paul@0 | 3504 | #define __dmac_channel_disable_irq(n) \ |
| paul@0 | 3505 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) |
| paul@0 | 3506 | |
| paul@0 | 3507 | #define __dmac_channel_transmit_halt_detected(n) \ |
| paul@0 | 3508 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) |
| paul@0 | 3509 | #define __dmac_channel_transmit_end_detected(n) \ |
| paul@0 | 3510 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) |
| paul@0 | 3511 | #define __dmac_channel_address_error_detected(n) \ |
| paul@0 | 3512 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) |
| paul@0 | 3513 | #define __dmac_channel_count_terminated_detected(n) \ |
| paul@0 | 3514 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) |
| paul@0 | 3515 | #define __dmac_channel_descriptor_invalid_detected(n) \ |
| paul@0 | 3516 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) |
| paul@0 | 3517 | |
| paul@0 | 3518 | #define __dmac_channel_clear_transmit_halt(n) \ |
| paul@0 | 3519 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) |
| paul@0 | 3520 | #define __dmac_channel_clear_transmit_end(n) \ |
| paul@0 | 3521 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) |
| paul@0 | 3522 | #define __dmac_channel_clear_address_error(n) \ |
| paul@0 | 3523 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) |
| paul@0 | 3524 | #define __dmac_channel_clear_count_terminated(n) \ |
| paul@0 | 3525 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) |
| paul@0 | 3526 | #define __dmac_channel_clear_descriptor_invalid(n) \ |
| paul@0 | 3527 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) |
| paul@0 | 3528 | |
| paul@0 | 3529 | #define __dmac_channel_set_single_mode(n) \ |
| paul@0 | 3530 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) |
| paul@0 | 3531 | #define __dmac_channel_set_block_mode(n) \ |
| paul@0 | 3532 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) |
| paul@0 | 3533 | |
| paul@0 | 3534 | #define __dmac_channel_set_transfer_unit_32bit(n) \ |
| paul@0 | 3535 | do { \ |
| paul@0 | 3536 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| paul@0 | 3537 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ |
| paul@0 | 3538 | } while (0) |
| paul@0 | 3539 | |
| paul@0 | 3540 | #define __dmac_channel_set_transfer_unit_16bit(n) \ |
| paul@0 | 3541 | do { \ |
| paul@0 | 3542 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| paul@0 | 3543 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ |
| paul@0 | 3544 | } while (0) |
| paul@0 | 3545 | |
| paul@0 | 3546 | #define __dmac_channel_set_transfer_unit_8bit(n) \ |
| paul@0 | 3547 | do { \ |
| paul@0 | 3548 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| paul@0 | 3549 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ |
| paul@0 | 3550 | } while (0) |
| paul@0 | 3551 | |
| paul@0 | 3552 | #define __dmac_channel_set_transfer_unit_16byte(n) \ |
| paul@0 | 3553 | do { \ |
| paul@0 | 3554 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| paul@0 | 3555 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ |
| paul@0 | 3556 | } while (0) |
| paul@0 | 3557 | |
| paul@0 | 3558 | #define __dmac_channel_set_transfer_unit_32byte(n) \ |
| paul@0 | 3559 | do { \ |
| paul@0 | 3560 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ |
| paul@0 | 3561 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ |
| paul@0 | 3562 | } while (0) |
| paul@0 | 3563 | |
| paul@0 | 3564 | /* w=8,16,32 */ |
| paul@0 | 3565 | #define __dmac_channel_set_dest_port_width(n,w) \ |
| paul@0 | 3566 | do { \ |
| paul@0 | 3567 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ |
| paul@0 | 3568 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ |
| paul@0 | 3569 | } while (0) |
| paul@0 | 3570 | |
| paul@0 | 3571 | /* w=8,16,32 */ |
| paul@0 | 3572 | #define __dmac_channel_set_src_port_width(n,w) \ |
| paul@0 | 3573 | do { \ |
| paul@0 | 3574 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ |
| paul@0 | 3575 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ |
| paul@0 | 3576 | } while (0) |
| paul@0 | 3577 | |
| paul@0 | 3578 | /* v=0-15 */ |
| paul@0 | 3579 | #define __dmac_channel_set_rdil(n,v) \ |
| paul@0 | 3580 | do { \ |
| paul@0 | 3581 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ |
| paul@0 | 3582 | REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ |
| paul@0 | 3583 | } while (0) |
| paul@0 | 3584 | |
| paul@0 | 3585 | #define __dmac_channel_dest_addr_fixed(n) \ |
| paul@0 | 3586 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) |
| paul@0 | 3587 | #define __dmac_channel_dest_addr_increment(n) \ |
| paul@0 | 3588 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) |
| paul@0 | 3589 | |
| paul@0 | 3590 | #define __dmac_channel_src_addr_fixed(n) \ |
| paul@0 | 3591 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) |
| paul@0 | 3592 | #define __dmac_channel_src_addr_increment(n) \ |
| paul@0 | 3593 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) |
| paul@0 | 3594 | |
| paul@0 | 3595 | #define __dmac_channel_set_doorbell(n) \ |
| paul@0 | 3596 | ( REG_DMAC_DMADBSR = (1 << (n)) ) |
| paul@0 | 3597 | |
| paul@0 | 3598 | #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) |
| paul@0 | 3599 | #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) |
| paul@0 | 3600 | |
| paul@0 | 3601 | static __inline__ int __dmac_get_irq(void) |
| paul@0 | 3602 | { |
| paul@0 | 3603 | int i; |
| paul@0 | 3604 | for (i = 0; i < MAX_DMA_NUM; i++) |
| paul@0 | 3605 | if (__dmac_channel_irq_detected(i)) |
| paul@0 | 3606 | return i; |
| paul@0 | 3607 | return -1; |
| paul@0 | 3608 | } |
| paul@0 | 3609 | |
| paul@0 | 3610 | |
| paul@0 | 3611 | /*************************************************************************** |
| paul@0 | 3612 | * AIC (AC'97 & I2S Controller) |
| paul@0 | 3613 | ***************************************************************************/ |
| paul@0 | 3614 | |
| paul@0 | 3615 | #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) |
| paul@0 | 3616 | #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) |
| paul@0 | 3617 | |
| paul@0 | 3618 | #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) |
| paul@0 | 3619 | #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) |
| paul@0 | 3620 | |
| paul@0 | 3621 | #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) |
| paul@0 | 3622 | #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) |
| paul@0 | 3623 | #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) |
| paul@0 | 3624 | |
| paul@0 | 3625 | #define __aic_reset() \ |
| paul@0 | 3626 | do { \ |
| paul@0 | 3627 | REG_AIC_FR |= AIC_FR_RST; \ |
| paul@0 | 3628 | } while(0) |
| paul@0 | 3629 | |
| paul@0 | 3630 | |
| paul@0 | 3631 | #define __aic_set_transmit_trigger(n) \ |
| paul@0 | 3632 | do { \ |
| paul@0 | 3633 | REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ |
| paul@0 | 3634 | REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ |
| paul@0 | 3635 | } while(0) |
| paul@0 | 3636 | |
| paul@0 | 3637 | #define __aic_set_receive_trigger(n) \ |
| paul@0 | 3638 | do { \ |
| paul@0 | 3639 | REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ |
| paul@0 | 3640 | REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ |
| paul@0 | 3641 | } while(0) |
| paul@0 | 3642 | |
| paul@0 | 3643 | #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) |
| paul@0 | 3644 | #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) |
| paul@0 | 3645 | #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) |
| paul@0 | 3646 | #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) |
| paul@0 | 3647 | #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) |
| paul@0 | 3648 | #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) |
| paul@0 | 3649 | |
| paul@0 | 3650 | #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) |
| paul@0 | 3651 | #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) |
| paul@0 | 3652 | |
| paul@0 | 3653 | #define __aic_enable_transmit_intr() \ |
| paul@0 | 3654 | ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) |
| paul@0 | 3655 | #define __aic_disable_transmit_intr() \ |
| paul@0 | 3656 | ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) |
| paul@0 | 3657 | #define __aic_enable_receive_intr() \ |
| paul@0 | 3658 | ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) |
| paul@0 | 3659 | #define __aic_disable_receive_intr() \ |
| paul@0 | 3660 | ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) |
| paul@0 | 3661 | |
| paul@0 | 3662 | #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) |
| paul@0 | 3663 | #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) |
| paul@0 | 3664 | #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) |
| paul@0 | 3665 | #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) |
| paul@0 | 3666 | |
| paul@0 | 3667 | #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) |
| paul@0 | 3668 | #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) |
| paul@0 | 3669 | #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) |
| paul@0 | 3670 | #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) |
| paul@0 | 3671 | #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) |
| paul@0 | 3672 | #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) |
| paul@0 | 3673 | |
| paul@0 | 3674 | #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 |
| paul@0 | 3675 | #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 |
| paul@0 | 3676 | #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 |
| paul@0 | 3677 | #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 |
| paul@0 | 3678 | #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 |
| paul@0 | 3679 | #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 |
| paul@0 | 3680 | |
| paul@0 | 3681 | #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 |
| paul@0 | 3682 | #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 |
| paul@0 | 3683 | #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 |
| paul@0 | 3684 | #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 |
| paul@0 | 3685 | #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 |
| paul@0 | 3686 | #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 |
| paul@0 | 3687 | |
| paul@0 | 3688 | #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) |
| paul@0 | 3689 | #define __ac97_set_xs_mono() \ |
| paul@0 | 3690 | do { \ |
| paul@0 | 3691 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
| paul@0 | 3692 | REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ |
| paul@0 | 3693 | } while(0) |
| paul@0 | 3694 | #define __ac97_set_xs_stereo() \ |
| paul@0 | 3695 | do { \ |
| paul@0 | 3696 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
| paul@0 | 3697 | REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ |
| paul@0 | 3698 | } while(0) |
| paul@0 | 3699 | |
| paul@0 | 3700 | /* In fact, only stereo is support now. */ |
| paul@0 | 3701 | #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) |
| paul@0 | 3702 | #define __ac97_set_rs_mono() \ |
| paul@0 | 3703 | do { \ |
| paul@0 | 3704 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
| paul@0 | 3705 | REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ |
| paul@0 | 3706 | } while(0) |
| paul@0 | 3707 | #define __ac97_set_rs_stereo() \ |
| paul@0 | 3708 | do { \ |
| paul@0 | 3709 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
| paul@0 | 3710 | REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ |
| paul@0 | 3711 | } while(0) |
| paul@0 | 3712 | |
| paul@0 | 3713 | #define __ac97_warm_reset_codec() \ |
| paul@0 | 3714 | do { \ |
| paul@0 | 3715 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ |
| paul@0 | 3716 | REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ |
| paul@0 | 3717 | udelay(2); \ |
| paul@0 | 3718 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ |
| paul@0 | 3719 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ |
| paul@0 | 3720 | } while (0) |
| paul@0 | 3721 | |
| paul@0 | 3722 | #define __ac97_cold_reset_codec() \ |
| paul@0 | 3723 | do { \ |
| paul@0 | 3724 | REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ |
| paul@0 | 3725 | udelay(2); \ |
| paul@0 | 3726 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ |
| paul@0 | 3727 | } while (0) |
| paul@0 | 3728 | |
| paul@0 | 3729 | /* n=8,16,18,20 */ |
| paul@0 | 3730 | #define __ac97_set_iass(n) \ |
| paul@0 | 3731 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) |
| paul@0 | 3732 | #define __ac97_set_oass(n) \ |
| paul@0 | 3733 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) |
| paul@0 | 3734 | |
| paul@0 | 3735 | #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) |
| paul@0 | 3736 | #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) |
| paul@0 | 3737 | |
| paul@0 | 3738 | /* n=8,16,18,20,24 */ |
| paul@0 | 3739 | /*#define __i2s_set_sample_size(n) \ |
| paul@0 | 3740 | ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ |
| paul@0 | 3741 | |
| paul@0 | 3742 | #define __i2s_set_oss_sample_size(n) \ |
| paul@0 | 3743 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) |
| paul@0 | 3744 | #define __i2s_set_iss_sample_size(n) \ |
| paul@0 | 3745 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) |
| paul@0 | 3746 | |
| paul@0 | 3747 | #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) |
| paul@0 | 3748 | #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) |
| paul@0 | 3749 | |
| paul@0 | 3750 | #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) |
| paul@0 | 3751 | #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) |
| paul@0 | 3752 | #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) |
| paul@0 | 3753 | #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) |
| paul@0 | 3754 | |
| paul@0 | 3755 | #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) |
| paul@0 | 3756 | |
| paul@0 | 3757 | #define __aic_get_transmit_resident() \ |
| paul@0 | 3758 | ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) |
| paul@0 | 3759 | #define __aic_get_receive_count() \ |
| paul@0 | 3760 | ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) |
| paul@0 | 3761 | |
| paul@0 | 3762 | #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) |
| paul@0 | 3763 | #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) |
| paul@0 | 3764 | #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) |
| paul@0 | 3765 | #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) |
| paul@0 | 3766 | #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) |
| paul@0 | 3767 | #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) |
| paul@0 | 3768 | #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) |
| paul@0 | 3769 | |
| paul@0 | 3770 | #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) |
| paul@0 | 3771 | |
| paul@0 | 3772 | #define CODEC_READ_CMD (1 << 19) |
| paul@0 | 3773 | #define CODEC_WRITE_CMD (0 << 19) |
| paul@0 | 3774 | #define CODEC_REG_INDEX_BIT 12 |
| paul@0 | 3775 | #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ |
| paul@0 | 3776 | #define CODEC_REG_DATA_BIT 4 |
| paul@0 | 3777 | #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ |
| paul@0 | 3778 | |
| paul@0 | 3779 | #define __ac97_out_rcmd_addr(reg) \ |
| paul@0 | 3780 | do { \ |
| paul@0 | 3781 | REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
| paul@0 | 3782 | } while (0) |
| paul@0 | 3783 | |
| paul@0 | 3784 | #define __ac97_out_wcmd_addr(reg) \ |
| paul@0 | 3785 | do { \ |
| paul@0 | 3786 | REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
| paul@0 | 3787 | } while (0) |
| paul@0 | 3788 | |
| paul@0 | 3789 | #define __ac97_out_data(value) \ |
| paul@0 | 3790 | do { \ |
| paul@0 | 3791 | REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ |
| paul@0 | 3792 | } while (0) |
| paul@0 | 3793 | |
| paul@0 | 3794 | #define __ac97_in_data() \ |
| paul@0 | 3795 | ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) |
| paul@0 | 3796 | |
| paul@0 | 3797 | #define __ac97_in_status_addr() \ |
| paul@0 | 3798 | ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) |
| paul@0 | 3799 | |
| paul@0 | 3800 | #define __i2s_set_sample_rate(i2sclk, sync) \ |
| paul@0 | 3801 | ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) |
| paul@0 | 3802 | |
| paul@0 | 3803 | #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) |
| paul@0 | 3804 | #define __aic_read_rfifo() ( REG_AIC_DR ) |
| paul@0 | 3805 | |
| paul@0 | 3806 | #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) |
| paul@0 | 3807 | #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) |
| paul@0 | 3808 | |
| paul@1 | 3809 | /* Define next ops for AC97 compatible */ |
| paul@0 | 3810 | |
| paul@0 | 3811 | #define AC97_ACSR AIC_ACSR |
| paul@0 | 3812 | |
| paul@0 | 3813 | #define __ac97_enable() __aic_enable(); __aic_select_ac97() |
| paul@0 | 3814 | #define __ac97_disable() __aic_disable() |
| paul@0 | 3815 | #define __ac97_reset() __aic_reset() |
| paul@0 | 3816 | |
| paul@0 | 3817 | #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
| paul@0 | 3818 | #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) |
| paul@0 | 3819 | |
| paul@0 | 3820 | #define __ac97_enable_record() __aic_enable_record() |
| paul@0 | 3821 | #define __ac97_disable_record() __aic_disable_record() |
| paul@0 | 3822 | #define __ac97_enable_replay() __aic_enable_replay() |
| paul@0 | 3823 | #define __ac97_disable_replay() __aic_disable_replay() |
| paul@0 | 3824 | #define __ac97_enable_loopback() __aic_enable_loopback() |
| paul@0 | 3825 | #define __ac97_disable_loopback() __aic_disable_loopback() |
| paul@0 | 3826 | |
| paul@0 | 3827 | #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() |
| paul@0 | 3828 | #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() |
| paul@0 | 3829 | #define __ac97_enable_receive_dma() __aic_enable_receive_dma() |
| paul@0 | 3830 | #define __ac97_disable_receive_dma() __aic_disable_receive_dma() |
| paul@0 | 3831 | |
| paul@0 | 3832 | #define __ac97_transmit_request() __aic_transmit_request() |
| paul@0 | 3833 | #define __ac97_receive_request() __aic_receive_request() |
| paul@0 | 3834 | #define __ac97_transmit_underrun() __aic_transmit_underrun() |
| paul@0 | 3835 | #define __ac97_receive_overrun() __aic_receive_overrun() |
| paul@0 | 3836 | |
| paul@0 | 3837 | #define __ac97_clear_errors() __aic_clear_errors() |
| paul@0 | 3838 | |
| paul@0 | 3839 | #define __ac97_get_transmit_resident() __aic_get_transmit_resident() |
| paul@0 | 3840 | #define __ac97_get_receive_count() __aic_get_receive_count() |
| paul@0 | 3841 | |
| paul@0 | 3842 | #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() |
| paul@0 | 3843 | #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() |
| paul@0 | 3844 | #define __ac97_enable_receive_intr() __aic_enable_receive_intr() |
| paul@0 | 3845 | #define __ac97_disable_receive_intr() __aic_disable_receive_intr() |
| paul@0 | 3846 | |
| paul@0 | 3847 | #define __ac97_write_tfifo(v) __aic_write_tfifo(v) |
| paul@0 | 3848 | #define __ac97_read_rfifo() __aic_read_rfifo() |
| paul@0 | 3849 | |
| paul@1 | 3850 | /* Define next ops for I2S compatible */ |
| paul@0 | 3851 | |
| paul@0 | 3852 | #define I2S_ACSR AIC_I2SSR |
| paul@0 | 3853 | |
| paul@0 | 3854 | #define __i2s_enable() __aic_enable(); __aic_select_i2s() |
| paul@0 | 3855 | #define __i2s_disable() __aic_disable() |
| paul@0 | 3856 | #define __i2s_reset() __aic_reset() |
| paul@0 | 3857 | |
| paul@0 | 3858 | #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
| paul@0 | 3859 | #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) |
| paul@0 | 3860 | |
| paul@0 | 3861 | #define __i2s_enable_record() __aic_enable_record() |
| paul@0 | 3862 | #define __i2s_disable_record() __aic_disable_record() |
| paul@0 | 3863 | #define __i2s_enable_replay() __aic_enable_replay() |
| paul@0 | 3864 | #define __i2s_disable_replay() __aic_disable_replay() |
| paul@0 | 3865 | #define __i2s_enable_loopback() __aic_enable_loopback() |
| paul@0 | 3866 | #define __i2s_disable_loopback() __aic_disable_loopback() |
| paul@0 | 3867 | |
| paul@0 | 3868 | #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() |
| paul@0 | 3869 | #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() |
| paul@0 | 3870 | #define __i2s_enable_receive_dma() __aic_enable_receive_dma() |
| paul@0 | 3871 | #define __i2s_disable_receive_dma() __aic_disable_receive_dma() |
| paul@0 | 3872 | |
| paul@0 | 3873 | #define __i2s_transmit_request() __aic_transmit_request() |
| paul@0 | 3874 | #define __i2s_receive_request() __aic_receive_request() |
| paul@0 | 3875 | #define __i2s_transmit_underrun() __aic_transmit_underrun() |
| paul@0 | 3876 | #define __i2s_receive_overrun() __aic_receive_overrun() |
| paul@0 | 3877 | |
| paul@0 | 3878 | #define __i2s_clear_errors() __aic_clear_errors() |
| paul@0 | 3879 | |
| paul@0 | 3880 | #define __i2s_get_transmit_resident() __aic_get_transmit_resident() |
| paul@0 | 3881 | #define __i2s_get_receive_count() __aic_get_receive_count() |
| paul@0 | 3882 | |
| paul@0 | 3883 | #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() |
| paul@0 | 3884 | #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() |
| paul@0 | 3885 | #define __i2s_enable_receive_intr() __aic_enable_receive_intr() |
| paul@0 | 3886 | #define __i2s_disable_receive_intr() __aic_disable_receive_intr() |
| paul@0 | 3887 | |
| paul@0 | 3888 | #define __i2s_write_tfifo(v) __aic_write_tfifo(v) |
| paul@0 | 3889 | #define __i2s_read_rfifo() __aic_read_rfifo() |
| paul@0 | 3890 | |
| paul@0 | 3891 | #define __i2s_reset_codec() \ |
| paul@0 | 3892 | do { \ |
| paul@0 | 3893 | } while (0) |
| paul@0 | 3894 | |
| paul@0 | 3895 | |
| paul@0 | 3896 | /*************************************************************************** |
| paul@0 | 3897 | * ICDC |
| paul@0 | 3898 | ***************************************************************************/ |
| paul@0 | 3899 | #define __i2s_internal_codec() __aic_internal_codec() |
| paul@0 | 3900 | #define __i2s_external_codec() __aic_external_codec() |
| paul@0 | 3901 | |
| paul@0 | 3902 | /*************************************************************************** |
| paul@0 | 3903 | * INTC |
| paul@0 | 3904 | ***************************************************************************/ |
| paul@0 | 3905 | #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) |
| paul@0 | 3906 | #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) |
| paul@0 | 3907 | #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) |
| paul@0 | 3908 | |
| paul@0 | 3909 | |
| paul@0 | 3910 | /*************************************************************************** |
| paul@0 | 3911 | * I2C |
| paul@0 | 3912 | ***************************************************************************/ |
| paul@0 | 3913 | |
| paul@0 | 3914 | #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) |
| paul@0 | 3915 | #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) |
| paul@0 | 3916 | |
| paul@0 | 3917 | #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) |
| paul@0 | 3918 | #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) |
| paul@0 | 3919 | #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) |
| paul@0 | 3920 | #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) |
| paul@0 | 3921 | |
| paul@0 | 3922 | #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) |
| paul@0 | 3923 | #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) |
| paul@0 | 3924 | #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) |
| paul@0 | 3925 | |
| paul@0 | 3926 | #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) |
| paul@0 | 3927 | #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) |
| paul@0 | 3928 | #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) |
| paul@0 | 3929 | |
| paul@0 | 3930 | #define __i2c_set_clk(dev_clk, i2c_clk) \ |
| paul@0 | 3931 | ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) |
| paul@0 | 3932 | |
| paul@0 | 3933 | #define __i2c_read() ( REG_I2C_DR ) |
| paul@0 | 3934 | #define __i2c_write(val) ( REG_I2C_DR = (val) ) |
| paul@0 | 3935 | |
| paul@0 | 3936 | |
| paul@0 | 3937 | /*************************************************************************** |
| paul@0 | 3938 | * MSC |
| paul@0 | 3939 | ***************************************************************************/ |
| paul@0 | 3940 | |
| paul@0 | 3941 | #define __msc_start_op() \ |
| paul@0 | 3942 | ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) |
| paul@0 | 3943 | |
| paul@0 | 3944 | #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) |
| paul@0 | 3945 | #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) |
| paul@0 | 3946 | #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) |
| paul@0 | 3947 | #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) |
| paul@0 | 3948 | #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) |
| paul@0 | 3949 | #define __msc_get_nob() ( REG_MSC_NOB ) |
| paul@0 | 3950 | #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) |
| paul@0 | 3951 | #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) |
| paul@0 | 3952 | #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) |
| paul@0 | 3953 | #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) |
| paul@0 | 3954 | |
| paul@0 | 3955 | #define __msc_set_cmdat_bus_width1() \ |
| paul@0 | 3956 | do { \ |
| paul@0 | 3957 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
| paul@0 | 3958 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ |
| paul@0 | 3959 | } while(0) |
| paul@0 | 3960 | |
| paul@0 | 3961 | #define __msc_set_cmdat_bus_width4() \ |
| paul@0 | 3962 | do { \ |
| paul@0 | 3963 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
| paul@0 | 3964 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ |
| paul@0 | 3965 | } while(0) |
| paul@0 | 3966 | |
| paul@0 | 3967 | #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) |
| paul@0 | 3968 | #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) |
| paul@0 | 3969 | #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) |
| paul@0 | 3970 | #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) |
| paul@0 | 3971 | #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) |
| paul@0 | 3972 | #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) |
| paul@0 | 3973 | #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) |
| paul@0 | 3974 | #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) |
| paul@0 | 3975 | |
| paul@0 | 3976 | /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ |
| paul@0 | 3977 | #define __msc_set_cmdat_res_format(r) \ |
| paul@0 | 3978 | do { \ |
| paul@0 | 3979 | REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ |
| paul@0 | 3980 | REG_MSC_CMDAT |= (r); \ |
| paul@0 | 3981 | } while(0) |
| paul@0 | 3982 | |
| paul@0 | 3983 | #define __msc_clear_cmdat() \ |
| paul@0 | 3984 | REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ |
| paul@0 | 3985 | MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ |
| paul@0 | 3986 | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) |
| paul@0 | 3987 | |
| paul@0 | 3988 | #define __msc_get_imask() ( REG_MSC_IMASK ) |
| paul@0 | 3989 | #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) |
| paul@0 | 3990 | #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) |
| paul@0 | 3991 | #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) |
| paul@0 | 3992 | #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) |
| paul@0 | 3993 | #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) |
| paul@0 | 3994 | #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) |
| paul@0 | 3995 | #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) |
| paul@0 | 3996 | #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) |
| paul@0 | 3997 | #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) |
| paul@0 | 3998 | #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) |
| paul@0 | 3999 | #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) |
| paul@0 | 4000 | #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) |
| paul@0 | 4001 | |
| paul@0 | 4002 | /* n=0,1,2,3,4,5,6,7 */ |
| paul@0 | 4003 | #define __msc_set_clkrt(n) \ |
| paul@0 | 4004 | do { \ |
| paul@0 | 4005 | REG_MSC_CLKRT = n; \ |
| paul@0 | 4006 | } while(0) |
| paul@0 | 4007 | |
| paul@0 | 4008 | #define __msc_get_ireg() ( REG_MSC_IREG ) |
| paul@0 | 4009 | #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) |
| paul@0 | 4010 | #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) |
| paul@0 | 4011 | #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) |
| paul@0 | 4012 | #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) |
| paul@0 | 4013 | #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) |
| paul@0 | 4014 | #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) |
| paul@0 | 4015 | #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) |
| paul@0 | 4016 | #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) |
| paul@0 | 4017 | |
| paul@0 | 4018 | #define __msc_get_stat() ( REG_MSC_STAT ) |
| paul@0 | 4019 | #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) |
| paul@0 | 4020 | #define __msc_stat_crc_err() \ |
| paul@0 | 4021 | ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) |
| paul@0 | 4022 | #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) |
| paul@0 | 4023 | #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) |
| paul@0 | 4024 | #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) |
| paul@0 | 4025 | #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) |
| paul@0 | 4026 | #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) |
| paul@0 | 4027 | |
| paul@0 | 4028 | #define __msc_rd_resfifo() ( REG_MSC_RES ) |
| paul@0 | 4029 | #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) |
| paul@0 | 4030 | #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) |
| paul@0 | 4031 | |
| paul@0 | 4032 | #define __msc_reset() \ |
| paul@0 | 4033 | do { \ |
| paul@0 | 4034 | REG_MSC_STRPCL = MSC_STRPCL_RESET; \ |
| paul@0 | 4035 | while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ |
| paul@0 | 4036 | } while (0) |
| paul@0 | 4037 | |
| paul@0 | 4038 | #define __msc_start_clk() \ |
| paul@0 | 4039 | do { \ |
| paul@0 | 4040 | REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ |
| paul@0 | 4041 | } while (0) |
| paul@0 | 4042 | |
| paul@0 | 4043 | #define __msc_stop_clk() \ |
| paul@0 | 4044 | do { \ |
| paul@0 | 4045 | REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ |
| paul@0 | 4046 | } while (0) |
| paul@0 | 4047 | |
| paul@0 | 4048 | #define MMC_CLK 19169200 |
| paul@0 | 4049 | #define SD_CLK 24576000 |
| paul@0 | 4050 | |
| paul@0 | 4051 | /* msc_clk should little than pclk and little than clk retrieve from card */ |
| paul@0 | 4052 | #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ |
| paul@0 | 4053 | do { \ |
| paul@0 | 4054 | unsigned int rate, pclk, i; \ |
| paul@0 | 4055 | pclk = dev_clk; \ |
| paul@0 | 4056 | rate = type?SD_CLK:MMC_CLK; \ |
| paul@0 | 4057 | if (msc_clk && msc_clk < pclk) \ |
| paul@0 | 4058 | pclk = msc_clk; \ |
| paul@0 | 4059 | i = 0; \ |
| paul@0 | 4060 | while (pclk < rate) \ |
| paul@0 | 4061 | { \ |
| paul@0 | 4062 | i ++; \ |
| paul@0 | 4063 | rate >>= 1; \ |
| paul@0 | 4064 | } \ |
| paul@0 | 4065 | lv = i; \ |
| paul@0 | 4066 | } while(0) |
| paul@0 | 4067 | |
| paul@0 | 4068 | /* divide rate to little than or equal to 400kHz */ |
| paul@0 | 4069 | #define __msc_calc_slow_clk_divisor(type, lv) \ |
| paul@0 | 4070 | do { \ |
| paul@0 | 4071 | unsigned int rate, i; \ |
| paul@0 | 4072 | rate = (type?SD_CLK:MMC_CLK)/1000/400; \ |
| paul@0 | 4073 | i = 0; \ |
| paul@0 | 4074 | while (rate > 0) \ |
| paul@0 | 4075 | { \ |
| paul@0 | 4076 | rate >>= 1; \ |
| paul@0 | 4077 | i ++; \ |
| paul@0 | 4078 | } \ |
| paul@0 | 4079 | lv = i; \ |
| paul@0 | 4080 | } while(0) |
| paul@0 | 4081 | |
| paul@0 | 4082 | |
| paul@0 | 4083 | /*************************************************************************** |
| paul@0 | 4084 | * SSI |
| paul@0 | 4085 | ***************************************************************************/ |
| paul@0 | 4086 | |
| paul@0 | 4087 | #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) |
| paul@0 | 4088 | #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) |
| paul@0 | 4089 | #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) |
| paul@0 | 4090 | |
| paul@0 | 4091 | #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) |
| paul@0 | 4092 | |
| paul@0 | 4093 | #define __ssi_select_ce2() \ |
| paul@0 | 4094 | do { \ |
| paul@0 | 4095 | REG_SSI_CR0 |= SSI_CR0_FSEL; \ |
| paul@0 | 4096 | REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ |
| paul@0 | 4097 | } while (0) |
| paul@0 | 4098 | |
| paul@0 | 4099 | #define __ssi_select_gpc() \ |
| paul@0 | 4100 | do { \ |
| paul@0 | 4101 | REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ |
| paul@0 | 4102 | REG_SSI_CR1 |= SSI_CR1_MULTS; \ |
| paul@0 | 4103 | } while (0) |
| paul@0 | 4104 | |
| paul@0 | 4105 | #define __ssi_enable_tx_intr() \ |
| paul@0 | 4106 | ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) |
| paul@0 | 4107 | |
| paul@0 | 4108 | #define __ssi_disable_tx_intr() \ |
| paul@0 | 4109 | ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) |
| paul@0 | 4110 | |
| paul@0 | 4111 | #define __ssi_enable_rx_intr() \ |
| paul@0 | 4112 | ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) |
| paul@0 | 4113 | |
| paul@0 | 4114 | #define __ssi_disable_rx_intr() \ |
| paul@0 | 4115 | ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) |
| paul@0 | 4116 | |
| paul@0 | 4117 | #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) |
| paul@0 | 4118 | #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) |
| paul@0 | 4119 | |
| paul@0 | 4120 | #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) |
| paul@0 | 4121 | #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) |
| paul@0 | 4122 | |
| paul@0 | 4123 | #define __ssi_finish_receive() \ |
| paul@0 | 4124 | ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| paul@0 | 4125 | |
| paul@0 | 4126 | #define __ssi_disable_recvfinish() \ |
| paul@0 | 4127 | ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| paul@0 | 4128 | |
| paul@0 | 4129 | #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) |
| paul@0 | 4130 | #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) |
| paul@0 | 4131 | |
| paul@0 | 4132 | #define __ssi_flush_fifo() \ |
| paul@0 | 4133 | ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) |
| paul@0 | 4134 | |
| paul@0 | 4135 | #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) |
| paul@0 | 4136 | |
| paul@0 | 4137 | #define __ssi_spi_format() \ |
| paul@0 | 4138 | do { \ |
| paul@0 | 4139 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
| paul@0 | 4140 | REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ |
| paul@0 | 4141 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
| paul@0 | 4142 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ |
| paul@0 | 4143 | } while (0) |
| paul@0 | 4144 | |
| paul@0 | 4145 | /* TI's SSP format, must clear SSI_CR1.UNFIN */ |
| paul@0 | 4146 | #define __ssi_ssp_format() \ |
| paul@0 | 4147 | do { \ |
| paul@0 | 4148 | REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ |
| paul@0 | 4149 | REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ |
| paul@0 | 4150 | } while (0) |
| paul@0 | 4151 | |
| paul@0 | 4152 | /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ |
| paul@0 | 4153 | #define __ssi_microwire_format() \ |
| paul@0 | 4154 | do { \ |
| paul@0 | 4155 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
| paul@0 | 4156 | REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ |
| paul@0 | 4157 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
| paul@0 | 4158 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ |
| paul@0 | 4159 | REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ |
| paul@0 | 4160 | } while (0) |
| paul@0 | 4161 | |
| paul@0 | 4162 | /* CE# level (FRMHL), CE# in interval time (ITFRM), |
| paul@0 | 4163 | clock phase and polarity (PHA POL), |
| paul@0 | 4164 | interval time (SSIITR), interval characters/frame (SSIICR) */ |
| paul@0 | 4165 | |
| paul@0 | 4166 | /* frmhl,endian,mcom,flen,pha,pol MASK */ |
| paul@0 | 4167 | #define SSICR1_MISC_MASK \ |
| paul@0 | 4168 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ |
| paul@0 | 4169 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ |
| paul@0 | 4170 | |
| paul@0 | 4171 | #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ |
| paul@0 | 4172 | do { \ |
| paul@0 | 4173 | REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ |
| paul@0 | 4174 | REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ |
| paul@0 | 4175 | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ |
| paul@0 | 4176 | ((pha) << 1) | (pol); \ |
| paul@0 | 4177 | } while(0) |
| paul@0 | 4178 | |
| paul@0 | 4179 | /* Transfer with MSB or LSB first */ |
| paul@0 | 4180 | #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) |
| paul@0 | 4181 | #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) |
| paul@0 | 4182 | |
| paul@0 | 4183 | #define __ssi_set_frame_length(n) \ |
| paul@0 | 4184 | REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) |
| paul@0 | 4185 | |
| paul@0 | 4186 | /* n = 1 - 16 */ |
| paul@0 | 4187 | #define __ssi_set_microwire_command_length(n) \ |
| paul@0 | 4188 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) |
| paul@0 | 4189 | |
| paul@0 | 4190 | /* Set the clock phase for SPI */ |
| paul@0 | 4191 | #define __ssi_set_spi_clock_phase(n) \ |
| paul@0 | 4192 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) |
| paul@0 | 4193 | |
| paul@0 | 4194 | /* Set the clock polarity for SPI */ |
| paul@0 | 4195 | #define __ssi_set_spi_clock_polarity(n) \ |
| paul@0 | 4196 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) |
| paul@0 | 4197 | |
| paul@0 | 4198 | /* n = ix8 */ |
| paul@0 | 4199 | #define __ssi_set_tx_trigger(n) \ |
| paul@0 | 4200 | do { \ |
| paul@0 | 4201 | REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ |
| paul@0 | 4202 | REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ |
| paul@0 | 4203 | } while (0) |
| paul@0 | 4204 | |
| paul@0 | 4205 | /* n = ix8 */ |
| paul@0 | 4206 | #define __ssi_set_rx_trigger(n) \ |
| paul@0 | 4207 | do { \ |
| paul@0 | 4208 | REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ |
| paul@0 | 4209 | REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ |
| paul@0 | 4210 | } while (0) |
| paul@0 | 4211 | |
| paul@0 | 4212 | #define __ssi_get_txfifo_count() \ |
| paul@0 | 4213 | ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) |
| paul@0 | 4214 | |
| paul@0 | 4215 | #define __ssi_get_rxfifo_count() \ |
| paul@0 | 4216 | ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) |
| paul@0 | 4217 | |
| paul@0 | 4218 | #define __ssi_clear_errors() \ |
| paul@0 | 4219 | ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) |
| paul@0 | 4220 | |
| paul@0 | 4221 | #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) |
| paul@0 | 4222 | #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) |
| paul@0 | 4223 | |
| paul@0 | 4224 | #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) |
| paul@0 | 4225 | #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) |
| paul@0 | 4226 | #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) |
| paul@0 | 4227 | |
| paul@0 | 4228 | #define __ssi_set_clk(dev_clk, ssi_clk) \ |
| paul@0 | 4229 | ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) |
| paul@0 | 4230 | |
| paul@0 | 4231 | #define __ssi_receive_data() REG_SSI_DR |
| paul@0 | 4232 | #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) |
| paul@0 | 4233 | |
| paul@0 | 4234 | |
| paul@0 | 4235 | /*************************************************************************** |
| paul@0 | 4236 | * CIM |
| paul@0 | 4237 | ***************************************************************************/ |
| paul@0 | 4238 | |
| paul@0 | 4239 | #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) |
| paul@0 | 4240 | #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) |
| paul@0 | 4241 | |
| paul@0 | 4242 | #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) |
| paul@0 | 4243 | #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) |
| paul@0 | 4244 | |
| paul@0 | 4245 | #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) |
| paul@0 | 4246 | #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) |
| paul@0 | 4247 | |
| paul@0 | 4248 | #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) |
| paul@0 | 4249 | #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) |
| paul@0 | 4250 | |
| paul@0 | 4251 | #define __cim_sample_data_at_pclk_falling_edge() \ |
| paul@0 | 4252 | ( REG_CIM_CFG |= CIM_CFG_PCP ) |
| paul@0 | 4253 | #define __cim_sample_data_at_pclk_rising_edge() \ |
| paul@0 | 4254 | ( REG_CIM_CFG &= ~CIM_CFG_PCP ) |
| paul@0 | 4255 | |
| paul@0 | 4256 | #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) |
| paul@0 | 4257 | #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) |
| paul@0 | 4258 | |
| paul@0 | 4259 | #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) |
| paul@0 | 4260 | #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) |
| paul@0 | 4261 | |
| paul@0 | 4262 | /* n=0-7 */ |
| paul@0 | 4263 | #define __cim_set_data_packing_mode(n) \ |
| paul@0 | 4264 | do { \ |
| paul@0 | 4265 | REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ |
| paul@0 | 4266 | REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ |
| paul@0 | 4267 | } while (0) |
| paul@0 | 4268 | |
| paul@0 | 4269 | #define __cim_enable_ccir656_progressive_mode() \ |
| paul@0 | 4270 | do { \ |
| paul@0 | 4271 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| paul@0 | 4272 | REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ |
| paul@0 | 4273 | } while (0) |
| paul@0 | 4274 | |
| paul@0 | 4275 | #define __cim_enable_ccir656_interlace_mode() \ |
| paul@0 | 4276 | do { \ |
| paul@0 | 4277 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| paul@0 | 4278 | REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ |
| paul@0 | 4279 | } while (0) |
| paul@0 | 4280 | |
| paul@0 | 4281 | #define __cim_enable_gated_clock_mode() \ |
| paul@0 | 4282 | do { \ |
| paul@0 | 4283 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| paul@0 | 4284 | REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ |
| paul@0 | 4285 | } while (0) |
| paul@0 | 4286 | |
| paul@0 | 4287 | #define __cim_enable_nongated_clock_mode() \ |
| paul@0 | 4288 | do { \ |
| paul@0 | 4289 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| paul@0 | 4290 | REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ |
| paul@0 | 4291 | } while (0) |
| paul@0 | 4292 | |
| paul@0 | 4293 | /* sclk:system bus clock |
| paul@0 | 4294 | * mclk: CIM master clock |
| paul@0 | 4295 | */ |
| paul@0 | 4296 | #define __cim_set_master_clk(sclk, mclk) \ |
| paul@0 | 4297 | do { \ |
| paul@0 | 4298 | REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ |
| paul@0 | 4299 | REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ |
| paul@0 | 4300 | } while (0) |
| paul@0 | 4301 | |
| paul@0 | 4302 | #define __cim_enable_sof_intr() \ |
| paul@0 | 4303 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) |
| paul@0 | 4304 | #define __cim_disable_sof_intr() \ |
| paul@0 | 4305 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) |
| paul@0 | 4306 | |
| paul@0 | 4307 | #define __cim_enable_eof_intr() \ |
| paul@0 | 4308 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) |
| paul@0 | 4309 | #define __cim_disable_eof_intr() \ |
| paul@0 | 4310 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) |
| paul@0 | 4311 | |
| paul@0 | 4312 | #define __cim_enable_stop_intr() \ |
| paul@0 | 4313 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) |
| paul@0 | 4314 | #define __cim_disable_stop_intr() \ |
| paul@0 | 4315 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) |
| paul@0 | 4316 | |
| paul@0 | 4317 | #define __cim_enable_trig_intr() \ |
| paul@0 | 4318 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) |
| paul@0 | 4319 | #define __cim_disable_trig_intr() \ |
| paul@0 | 4320 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) |
| paul@0 | 4321 | |
| paul@0 | 4322 | #define __cim_enable_rxfifo_overflow_intr() \ |
| paul@0 | 4323 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) |
| paul@0 | 4324 | #define __cim_disable_rxfifo_overflow_intr() \ |
| paul@0 | 4325 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) |
| paul@0 | 4326 | |
| paul@0 | 4327 | /* n=1-16 */ |
| paul@0 | 4328 | #define __cim_set_frame_rate(n) \ |
| paul@0 | 4329 | do { \ |
| paul@0 | 4330 | REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ |
| paul@0 | 4331 | REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ |
| paul@0 | 4332 | } while (0) |
| paul@0 | 4333 | |
| paul@0 | 4334 | #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) |
| paul@0 | 4335 | #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) |
| paul@0 | 4336 | |
| paul@0 | 4337 | #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) |
| paul@0 | 4338 | #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) |
| paul@0 | 4339 | |
| paul@0 | 4340 | /* n=4,8,12,16,20,24,28,32 */ |
| paul@0 | 4341 | #define __cim_set_rxfifo_trigger(n) \ |
| paul@0 | 4342 | do { \ |
| paul@0 | 4343 | REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ |
| paul@0 | 4344 | REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ |
| paul@0 | 4345 | } while (0) |
| paul@0 | 4346 | |
| paul@0 | 4347 | #define __cim_clear_state() ( REG_CIM_STATE = 0 ) |
| paul@0 | 4348 | |
| paul@0 | 4349 | #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) |
| paul@0 | 4350 | #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) |
| paul@0 | 4351 | #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) |
| paul@0 | 4352 | #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) |
| paul@0 | 4353 | #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) |
| paul@0 | 4354 | #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) |
| paul@0 | 4355 | #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) |
| paul@0 | 4356 | #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) |
| paul@0 | 4357 | |
| paul@0 | 4358 | #define __cim_get_iid() ( REG_CIM_IID ) |
| paul@0 | 4359 | #define __cim_get_image_data() ( REG_CIM_RXFIFO ) |
| paul@0 | 4360 | #define __cim_get_dam_cmd() ( REG_CIM_CMD ) |
| paul@0 | 4361 | |
| paul@0 | 4362 | #define __cim_set_da(a) ( REG_CIM_DA = (a) ) |
| paul@0 | 4363 | |
| paul@0 | 4364 | /*************************************************************************** |
| paul@0 | 4365 | * LCD |
| paul@0 | 4366 | ***************************************************************************/ |
| paul@0 | 4367 | #define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) ) |
| paul@0 | 4368 | #define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) ) |
| paul@0 | 4369 | |
| paul@0 | 4370 | #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) |
| paul@0 | 4371 | #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) |
| paul@0 | 4372 | |
| paul@0 | 4373 | #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) |
| paul@0 | 4374 | #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) |
| paul@0 | 4375 | |
| paul@0 | 4376 | /* n=1,2,4,8,16 */ |
| paul@0 | 4377 | #define __lcd_set_bpp(n) \ |
| paul@0 | 4378 | ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) |
| paul@0 | 4379 | |
| paul@0 | 4380 | /* n=4,8,16 */ |
| paul@0 | 4381 | #define __lcd_set_burst_length(n) \ |
| paul@0 | 4382 | do { \ |
| paul@0 | 4383 | REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ |
| paul@0 | 4384 | REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ |
| paul@0 | 4385 | } while (0) |
| paul@0 | 4386 | |
| paul@0 | 4387 | #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) |
| paul@0 | 4388 | #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) |
| paul@0 | 4389 | |
| paul@0 | 4390 | #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) |
| paul@0 | 4391 | #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) |
| paul@0 | 4392 | |
| paul@0 | 4393 | /* n=2,4,16 */ |
| paul@0 | 4394 | #define __lcd_set_stn_frc(n) \ |
| paul@0 | 4395 | do { \ |
| paul@0 | 4396 | REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ |
| paul@0 | 4397 | REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ |
| paul@0 | 4398 | } while (0) |
| paul@0 | 4399 | |
| paul@0 | 4400 | |
| paul@0 | 4401 | #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) |
| paul@0 | 4402 | #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) |
| paul@0 | 4403 | |
| paul@0 | 4404 | #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) |
| paul@0 | 4405 | #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) |
| paul@0 | 4406 | |
| paul@0 | 4407 | #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) |
| paul@0 | 4408 | #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) |
| paul@0 | 4409 | |
| paul@0 | 4410 | #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) |
| paul@0 | 4411 | #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) |
| paul@0 | 4412 | |
| paul@0 | 4413 | #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) |
| paul@0 | 4414 | #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) |
| paul@0 | 4415 | |
| paul@0 | 4416 | #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) |
| paul@0 | 4417 | #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) |
| paul@0 | 4418 | |
| paul@0 | 4419 | #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) |
| paul@0 | 4420 | #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) |
| paul@0 | 4421 | |
| paul@0 | 4422 | #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) |
| paul@0 | 4423 | #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) |
| paul@0 | 4424 | |
| paul@0 | 4425 | #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) |
| paul@0 | 4426 | #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) |
| paul@0 | 4427 | |
| paul@0 | 4428 | |
| paul@0 | 4429 | /* LCD status register indication */ |
| paul@0 | 4430 | |
| paul@0 | 4431 | #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) |
| paul@0 | 4432 | #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) |
| paul@0 | 4433 | #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) |
| paul@0 | 4434 | #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) |
| paul@0 | 4435 | #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) |
| paul@0 | 4436 | #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) |
| paul@0 | 4437 | #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) |
| paul@0 | 4438 | |
| paul@0 | 4439 | #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) |
| paul@0 | 4440 | #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) |
| paul@0 | 4441 | #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) |
| paul@0 | 4442 | |
| paul@0 | 4443 | #define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE ) |
| paul@0 | 4444 | #define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE ) |
| paul@0 | 4445 | |
| paul@0 | 4446 | /* n=1,2,4,8 for single mono-STN |
| paul@0 | 4447 | * n=4,8 for dual mono-STN |
| paul@0 | 4448 | */ |
| paul@0 | 4449 | #define __lcd_set_panel_datawidth(n) \ |
| paul@0 | 4450 | do { \ |
| paul@0 | 4451 | REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \ |
| paul@0 | 4452 | REG_LCD_CFG |= LCD_CFG_PDW_n##; \ |
| paul@0 | 4453 | } while (0) |
| paul@0 | 4454 | |
| paul@0 | 4455 | /* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */ |
| paul@0 | 4456 | #define __lcd_set_panel_mode(m) \ |
| paul@0 | 4457 | do { \ |
| paul@0 | 4458 | REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \ |
| paul@0 | 4459 | REG_LCD_CFG |= (m); \ |
| paul@0 | 4460 | } while(0) |
| paul@0 | 4461 | |
| paul@0 | 4462 | /* n = 0-255 */ |
| paul@0 | 4463 | #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) |
| paul@0 | 4464 | #define __lcd_set_ac_bias(n) \ |
| paul@0 | 4465 | do { \ |
| paul@0 | 4466 | REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ |
| paul@0 | 4467 | REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ |
| paul@0 | 4468 | } while(0) |
| paul@0 | 4469 | |
| paul@0 | 4470 | #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) |
| paul@0 | 4471 | #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) |
| paul@0 | 4472 | |
| paul@0 | 4473 | #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) |
| paul@0 | 4474 | #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) |
| paul@0 | 4475 | |
| paul@0 | 4476 | #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) |
| paul@0 | 4477 | #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) |
| paul@0 | 4478 | |
| paul@0 | 4479 | #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) |
| paul@0 | 4480 | #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) |
| paul@0 | 4481 | |
| paul@0 | 4482 | #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) |
| paul@0 | 4483 | #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) |
| paul@0 | 4484 | |
| paul@0 | 4485 | #define __lcd_vsync_get_vps() \ |
| paul@0 | 4486 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) |
| paul@0 | 4487 | |
| paul@0 | 4488 | #define __lcd_vsync_get_vpe() \ |
| paul@0 | 4489 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) |
| paul@0 | 4490 | #define __lcd_vsync_set_vpe(n) \ |
| paul@0 | 4491 | do { \ |
| paul@0 | 4492 | REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ |
| paul@0 | 4493 | REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ |
| paul@0 | 4494 | } while (0) |
| paul@0 | 4495 | |
| paul@0 | 4496 | #define __lcd_hsync_get_hps() \ |
| paul@0 | 4497 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) |
| paul@0 | 4498 | #define __lcd_hsync_set_hps(n) \ |
| paul@0 | 4499 | do { \ |
| paul@0 | 4500 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ |
| paul@0 | 4501 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ |
| paul@0 | 4502 | } while (0) |
| paul@0 | 4503 | |
| paul@0 | 4504 | #define __lcd_hsync_get_hpe() \ |
| paul@0 | 4505 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) |
| paul@0 | 4506 | #define __lcd_hsync_set_hpe(n) \ |
| paul@0 | 4507 | do { \ |
| paul@0 | 4508 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ |
| paul@0 | 4509 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ |
| paul@0 | 4510 | } while (0) |
| paul@0 | 4511 | |
| paul@0 | 4512 | #define __lcd_vat_get_ht() \ |
| paul@0 | 4513 | ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) |
| paul@0 | 4514 | #define __lcd_vat_set_ht(n) \ |
| paul@0 | 4515 | do { \ |
| paul@0 | 4516 | REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ |
| paul@0 | 4517 | REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ |
| paul@0 | 4518 | } while (0) |
| paul@0 | 4519 | |
| paul@0 | 4520 | #define __lcd_vat_get_vt() \ |
| paul@0 | 4521 | ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) |
| paul@0 | 4522 | #define __lcd_vat_set_vt(n) \ |
| paul@0 | 4523 | do { \ |
| paul@0 | 4524 | REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ |
| paul@0 | 4525 | REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ |
| paul@0 | 4526 | } while (0) |
| paul@0 | 4527 | |
| paul@0 | 4528 | #define __lcd_dah_get_hds() \ |
| paul@0 | 4529 | ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) |
| paul@0 | 4530 | #define __lcd_dah_set_hds(n) \ |
| paul@0 | 4531 | do { \ |
| paul@0 | 4532 | REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ |
| paul@0 | 4533 | REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ |
| paul@0 | 4534 | } while (0) |
| paul@0 | 4535 | |
| paul@0 | 4536 | #define __lcd_dah_get_hde() \ |
| paul@0 | 4537 | ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) |
| paul@0 | 4538 | #define __lcd_dah_set_hde(n) \ |
| paul@0 | 4539 | do { \ |
| paul@0 | 4540 | REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ |
| paul@0 | 4541 | REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ |
| paul@0 | 4542 | } while (0) |
| paul@0 | 4543 | |
| paul@0 | 4544 | #define __lcd_dav_get_vds() \ |
| paul@0 | 4545 | ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) |
| paul@0 | 4546 | #define __lcd_dav_set_vds(n) \ |
| paul@0 | 4547 | do { \ |
| paul@0 | 4548 | REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ |
| paul@0 | 4549 | REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ |
| paul@0 | 4550 | } while (0) |
| paul@0 | 4551 | |
| paul@0 | 4552 | #define __lcd_dav_get_vde() \ |
| paul@0 | 4553 | ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) |
| paul@0 | 4554 | #define __lcd_dav_set_vde(n) \ |
| paul@0 | 4555 | do { \ |
| paul@0 | 4556 | REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ |
| paul@0 | 4557 | REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ |
| paul@0 | 4558 | } while (0) |
| paul@0 | 4559 | |
| paul@0 | 4560 | #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) |
| paul@0 | 4561 | #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) |
| paul@0 | 4562 | #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) |
| paul@0 | 4563 | #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) |
| paul@0 | 4564 | |
| paul@0 | 4565 | #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) |
| paul@0 | 4566 | #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) |
| paul@0 | 4567 | #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) |
| paul@0 | 4568 | #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) |
| paul@0 | 4569 | |
| paul@0 | 4570 | #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) |
| paul@0 | 4571 | #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) |
| paul@0 | 4572 | |
| paul@0 | 4573 | #define __lcd_cmd0_get_len() \ |
| paul@0 | 4574 | ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| paul@0 | 4575 | #define __lcd_cmd1_get_len() \ |
| paul@0 | 4576 | ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| paul@0 | 4577 | |
| paul@0 | 4578 | /*************************************************************************** |
| paul@0 | 4579 | * RTC ops |
| paul@0 | 4580 | ***************************************************************************/ |
| paul@0 | 4581 | |
| paul@0 | 4582 | #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) |
| paul@0 | 4583 | #define __rtc_enabled() \ |
| paul@0 | 4584 | do{ \ |
| paul@0 | 4585 | while(!__rtc_write_ready()); \ |
| paul@0 | 4586 | REG_RTC_RCR |= RTC_RCR_RTCE ; \ |
| paul@0 | 4587 | }while(0) \ |
| paul@0 | 4588 | |
| paul@0 | 4589 | #define __rtc_disabled() \ |
| paul@0 | 4590 | do{ \ |
| paul@0 | 4591 | while(!__rtc_write_ready()); \ |
| paul@0 | 4592 | REG_RTC_RCR &= ~RTC_RCR_RTCE; \ |
| paul@0 | 4593 | }while(0) |
| paul@0 | 4594 | #define __rtc_enable_alarm() \ |
| paul@0 | 4595 | do{ \ |
| paul@0 | 4596 | while(!__rtc_write_ready()); \ |
| paul@0 | 4597 | REG_RTC_RCR |= RTC_RCR_AE; \ |
| paul@0 | 4598 | }while(0) |
| paul@0 | 4599 | |
| paul@0 | 4600 | #define __rtc_disable_alarm() \ |
| paul@0 | 4601 | do{ \ |
| paul@0 | 4602 | while(!__rtc_write_ready()); \ |
| paul@0 | 4603 | REG_RTC_RCR &= ~RTC_RCR_AE; \ |
| paul@0 | 4604 | }while(0) |
| paul@0 | 4605 | |
| paul@0 | 4606 | #define __rtc_enable_alarm_irq() \ |
| paul@0 | 4607 | do{ \ |
| paul@0 | 4608 | while(!__rtc_write_ready()); \ |
| paul@0 | 4609 | REG_RTC_RCR |= RTC_RCR_AIE; \ |
| paul@0 | 4610 | }while(0) |
| paul@0 | 4611 | |
| paul@0 | 4612 | #define __rtc_disable_alarm_irq() \ |
| paul@0 | 4613 | do{ \ |
| paul@0 | 4614 | while(!__rtc_write_ready()); \ |
| paul@0 | 4615 | REG_RTC_RCR &= ~RTC_RCR_AIE; \ |
| paul@0 | 4616 | }while(0) |
| paul@0 | 4617 | #define __rtc_enable_Hz_irq() \ |
| paul@0 | 4618 | do{ \ |
| paul@0 | 4619 | while(!__rtc_write_ready()); \ |
| paul@0 | 4620 | REG_RTC_RCR |= RTC_RCR_HZIE; \ |
| paul@0 | 4621 | }while(0) |
| paul@0 | 4622 | |
| paul@0 | 4623 | #define __rtc_disable_Hz_irq() \ |
| paul@0 | 4624 | do{ \ |
| paul@0 | 4625 | while(!__rtc_write_ready()); \ |
| paul@0 | 4626 | REG_RTC_RCR &= ~RTC_RCR_HZIE; \ |
| paul@0 | 4627 | }while(0) |
| paul@0 | 4628 | #define __rtc_get_1Hz_flag() \ |
| paul@0 | 4629 | do{ \ |
| paul@0 | 4630 | while(!__rtc_write_ready()); \ |
| paul@0 | 4631 | ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ |
| paul@0 | 4632 | }while(0) |
| paul@0 | 4633 | #define __rtc_clear_1Hz_flag() \ |
| paul@0 | 4634 | do{ \ |
| paul@0 | 4635 | while(!__rtc_write_ready()); \ |
| paul@0 | 4636 | REG_RTC_RCR &= ~RTC_RCR_HZ; \ |
| paul@0 | 4637 | }while(0) |
| paul@0 | 4638 | #define __rtc_get_alarm_flag() \ |
| paul@0 | 4639 | do{ \ |
| paul@0 | 4640 | while(!__rtc_write_ready()); \ |
| paul@0 | 4641 | ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \ |
| paul@0 | 4642 | while(0) |
| paul@0 | 4643 | #define __rtc_clear_alarm_flag() \ |
| paul@0 | 4644 | do{ \ |
| paul@0 | 4645 | while(!__rtc_write_ready()); \ |
| paul@0 | 4646 | REG_RTC_RCR &= ~RTC_RCR_AF; \ |
| paul@0 | 4647 | }while(0) |
| paul@0 | 4648 | #define __rtc_get_second() \ |
| paul@0 | 4649 | do{ \ |
| paul@0 | 4650 | while(!__rtc_write_ready());\ |
| paul@0 | 4651 | REG_RTC_RSR; \ |
| paul@0 | 4652 | }while(0) |
| paul@0 | 4653 | |
| paul@0 | 4654 | #define __rtc_set_second(v) \ |
| paul@0 | 4655 | do{ \ |
| paul@0 | 4656 | while(!__rtc_write_ready()); \ |
| paul@0 | 4657 | REG_RTC_RSR = v; \ |
| paul@0 | 4658 | }while(0) |
| paul@0 | 4659 | |
| paul@0 | 4660 | #define __rtc_get_alarm_second() \ |
| paul@0 | 4661 | do{ \ |
| paul@0 | 4662 | while(!__rtc_write_ready()); \ |
| paul@0 | 4663 | REG_RTC_RSAR; \ |
| paul@0 | 4664 | }while(0) |
| paul@0 | 4665 | |
| paul@1 | 4666 | |
| paul@0 | 4667 | #define __rtc_set_alarm_second(v) \ |
| paul@0 | 4668 | do{ \ |
| paul@0 | 4669 | while(!__rtc_write_ready()); \ |
| paul@0 | 4670 | REG_RTC_RSAR = v; \ |
| paul@0 | 4671 | }while(0) |
| paul@0 | 4672 | |
| paul@0 | 4673 | #define __rtc_RGR_is_locked() \ |
| paul@0 | 4674 | do{ \ |
| paul@0 | 4675 | while(!__rtc_write_ready()); \ |
| paul@0 | 4676 | REG_RTC_RGR >> RTC_RGR_LOCK; \ |
| paul@0 | 4677 | }while(0) |
| paul@0 | 4678 | #define __rtc_lock_RGR() \ |
| paul@0 | 4679 | do{ \ |
| paul@0 | 4680 | while(!__rtc_write_ready()); \ |
| paul@0 | 4681 | REG_RTC_RGR |= RTC_RGR_LOCK; \ |
| paul@0 | 4682 | }while(0) |
| paul@0 | 4683 | |
| paul@0 | 4684 | #define __rtc_unlock_RGR() \ |
| paul@0 | 4685 | do{ \ |
| paul@0 | 4686 | while(!__rtc_write_ready()); \ |
| paul@0 | 4687 | REG_RTC_RGR &= ~RTC_RGR_LOCK; \ |
| paul@0 | 4688 | }while(0) |
| paul@0 | 4689 | |
| paul@0 | 4690 | #define __rtc_get_adjc_val() \ |
| paul@0 | 4691 | do{ \ |
| paul@0 | 4692 | while(!__rtc_write_ready()); \ |
| paul@0 | 4693 | ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ |
| paul@0 | 4694 | }while(0) |
| paul@0 | 4695 | #define __rtc_set_adjc_val(v) \ |
| paul@0 | 4696 | do{ \ |
| paul@0 | 4697 | while(!__rtc_write_ready()); \ |
| paul@0 | 4698 | ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \ |
| paul@0 | 4699 | }while(0) |
| paul@0 | 4700 | |
| paul@0 | 4701 | #define __rtc_get_nc1Hz_val() \ |
| paul@0 | 4702 | while(!__rtc_write_ready()); \ |
| paul@0 | 4703 | ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) |
| paul@1 | 4704 | |
| paul@0 | 4705 | #define __rtc_set_nc1Hz_val(v) \ |
| paul@0 | 4706 | do{ \ |
| paul@0 | 4707 | while(!__rtc_write_ready()); \ |
| paul@0 | 4708 | ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \ |
| paul@0 | 4709 | }while(0) |
| paul@0 | 4710 | #define __rtc_power_down() \ |
| paul@0 | 4711 | do{ \ |
| paul@0 | 4712 | while(!__rtc_write_ready()); \ |
| paul@0 | 4713 | REG_RTC_HCR |= RTC_HCR_PD; \ |
| paul@0 | 4714 | }while(0) |
| paul@0 | 4715 | |
| paul@0 | 4716 | #define __rtc_get_hwfcr_val() \ |
| paul@0 | 4717 | do{ \ |
| paul@0 | 4718 | while(!__rtc_write_ready()); \ |
| paul@0 | 4719 | REG_RTC_HWFCR & RTC_HWFCR_MASK; \ |
| paul@0 | 4720 | }while(0) |
| paul@0 | 4721 | #define __rtc_set_hwfcr_val(v) \ |
| paul@0 | 4722 | do{ \ |
| paul@0 | 4723 | while(!__rtc_write_ready()); \ |
| paul@0 | 4724 | REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ |
| paul@0 | 4725 | }while(0) |
| paul@0 | 4726 | |
| paul@0 | 4727 | #define __rtc_get_hrcr_val() \ |
| paul@0 | 4728 | do{ \ |
| paul@0 | 4729 | while(!__rtc_write_ready()); \ |
| paul@0 | 4730 | ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ |
| paul@0 | 4731 | }while(0) |
| paul@0 | 4732 | #define __rtc_set_hrcr_val(v) \ |
| paul@0 | 4733 | do{ \ |
| paul@0 | 4734 | while(!__rtc_write_ready()); \ |
| paul@0 | 4735 | ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ |
| paul@0 | 4736 | }while(0) |
| paul@0 | 4737 | |
| paul@0 | 4738 | #define __rtc_enable_alarm_wakeup() \ |
| paul@0 | 4739 | do{ \ |
| paul@0 | 4740 | while(!__rtc_write_ready()); \ |
| paul@0 | 4741 | ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ |
| paul@0 | 4742 | }while(0) |
| paul@0 | 4743 | |
| paul@0 | 4744 | #define __rtc_disable_alarm_wakeup() \ |
| paul@0 | 4745 | do{ \ |
| paul@0 | 4746 | while(!__rtc_write_ready()); \ |
| paul@0 | 4747 | ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ |
| paul@0 | 4748 | }while(0) |
| paul@0 | 4749 | |
| paul@0 | 4750 | #define __rtc_status_hib_reset_occur() \ |
| paul@0 | 4751 | do{ \ |
| paul@0 | 4752 | while(!__rtc_write_ready()); \ |
| paul@0 | 4753 | ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \ |
| paul@0 | 4754 | }while(0) |
| paul@0 | 4755 | #define __rtc_status_ppr_reset_occur() \ |
| paul@0 | 4756 | do{ \ |
| paul@0 | 4757 | while(!__rtc_write_ready()); \ |
| paul@0 | 4758 | ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \ |
| paul@0 | 4759 | }while(0) |
| paul@0 | 4760 | #define __rtc_status_wakeup_pin_waken_up() \ |
| paul@0 | 4761 | do{ \ |
| paul@0 | 4762 | while(!__rtc_write_ready()); \ |
| paul@0 | 4763 | ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ |
| paul@0 | 4764 | }while(0) |
| paul@0 | 4765 | #define __rtc_status_alarm_waken_up() \ |
| paul@0 | 4766 | do{ \ |
| paul@0 | 4767 | while(!__rtc_write_ready()); \ |
| paul@0 | 4768 | ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ |
| paul@0 | 4769 | }while(0) |
| paul@0 | 4770 | #define __rtc_clear_hib_stat_all() \ |
| paul@0 | 4771 | do{ \ |
| paul@0 | 4772 | while(!__rtc_write_ready()); \ |
| paul@0 | 4773 | ( REG_RTC_HWRSR = 0 ); \ |
| paul@0 | 4774 | }while(0) |
| paul@0 | 4775 | |
| paul@0 | 4776 | #define __rtc_get_scratch_pattern() \ |
| paul@0 | 4777 | while(!__rtc_write_ready()); \ |
| paul@0 | 4778 | (REG_RTC_HSPR) |
| paul@0 | 4779 | #define __rtc_set_scratch_pattern(n) \ |
| paul@0 | 4780 | do{ \ |
| paul@0 | 4781 | while(!__rtc_write_ready()); \ |
| paul@0 | 4782 | (REG_RTC_HSPR = n ); \ |
| paul@0 | 4783 | }while(0) |
| paul@0 | 4784 | |
| paul@1 | 4785 | |
| paul@0 | 4786 | #endif /* !__ASSEMBLY__ */ |
| paul@0 | 4787 | |
| paul@0 | 4788 | #endif /* __JZ4740_H__ */ |
