paul@0 | 1 | /* |
paul@35 | 2 | * Generic board initialisation, based on uboot-xburst and xburst-tools. |
paul@0 | 3 | * |
paul@35 | 4 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@35 | 5 | * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> |
paul@57 | 6 | * Copyright (C) 2006 Stefan Roese, DENX Software Engineering, sr@denx.de. |
paul@35 | 7 | * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> |
paul@217 | 8 | * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 9 | * |
paul@63 | 10 | * This program is free software: you can redistribute it and/or modify |
paul@63 | 11 | * it under the terms of the GNU General Public License as published by |
paul@63 | 12 | * the Free Software Foundation, either version 3 of the License, or |
paul@63 | 13 | * (at your option) any later version. |
paul@0 | 14 | * |
paul@63 | 15 | * This program is distributed in the hope that it will be useful, |
paul@63 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@63 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@63 | 18 | * GNU General Public License for more details. |
paul@0 | 19 | * |
paul@63 | 20 | * You should have received a copy of the GNU General Public License |
paul@63 | 21 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 22 | */ |
paul@0 | 23 | |
paul@35 | 24 | #ifdef CONFIG_CPU_JZ4730 |
paul@35 | 25 | #include "jz4730.h" |
paul@43 | 26 | #include "jz4730_compat.h" |
paul@35 | 27 | #else |
paul@0 | 28 | #include "jz4740.h" |
paul@35 | 29 | #endif |
paul@35 | 30 | |
paul@194 | 31 | #include "memory.h" |
paul@33 | 32 | #include "sdram.h" |
paul@230 | 33 | #include "cpm.h" |
paul@233 | 34 | #include "gpio.h" |
paul@10 | 35 | #include "usb_boot_defines.h" |
paul@10 | 36 | |
paul@10 | 37 | /* These arguments are initialised by usbboot and are defined in... |
paul@10 | 38 | /etc/xburst-tools/usbboot.cfg. */ |
paul@10 | 39 | |
paul@10 | 40 | struct fw_args *fw_args; |
paul@217 | 41 | volatile uint32_t FW_CPU_ID; |
paul@217 | 42 | volatile uint8_t FW_SDRAM_BW16; |
paul@217 | 43 | volatile uint8_t FW_SDRAM_BANK4; |
paul@217 | 44 | volatile uint8_t FW_SDRAM_ROW; |
paul@217 | 45 | volatile uint8_t FW_SDRAM_COL; |
paul@217 | 46 | volatile uint8_t FW_CONFIG_MOBILE_SDRAM; |
paul@217 | 47 | volatile uint8_t FW_IS_SHARE; |
paul@10 | 48 | |
paul@195 | 49 | void load_args() |
paul@10 | 50 | { |
paul@17 | 51 | /* Get the fw args from memory. See head1.S for the memory layout. */ |
paul@10 | 52 | |
paul@194 | 53 | fw_args = (struct fw_args *) STAGE1_ARGS; |
paul@27 | 54 | FW_CPU_ID = fw_args->cpu_id ; |
paul@60 | 55 | |
paul@60 | 56 | /* Where the arguments have not been initialised, use the defaults. */ |
paul@60 | 57 | |
paul@60 | 58 | FW_SDRAM_BW16 = FW_CPU_ID ? fw_args->bus_width : SDRAM_BW16; |
paul@60 | 59 | FW_SDRAM_BANK4 = FW_CPU_ID ? fw_args->bank_num : SDRAM_BANK4; |
paul@60 | 60 | FW_SDRAM_ROW = FW_CPU_ID ? fw_args->row_addr : SDRAM_ROW; |
paul@60 | 61 | FW_SDRAM_COL = FW_CPU_ID ? fw_args->col_addr : SDRAM_COL; |
paul@27 | 62 | FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; |
paul@27 | 63 | FW_IS_SHARE = fw_args->is_busshare; |
paul@10 | 64 | } |
paul@10 | 65 | |
paul@10 | 66 | /* Initialisation functions. */ |
paul@0 | 67 | |
paul@195 | 68 | void gpio_init() |
paul@0 | 69 | { |
paul@233 | 70 | void *gpio_port_base; |
paul@233 | 71 | |
paul@57 | 72 | #ifdef CONFIG_CPU_JZ4730 |
paul@57 | 73 | /* |
paul@57 | 74 | * Initialize SDRAM pins |
paul@57 | 75 | */ |
paul@233 | 76 | |
paul@233 | 77 | /* gpio_as_emc */ |
paul@233 | 78 | |
paul@233 | 79 | gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, GPIO_PORT_EMC); |
paul@233 | 80 | |
paul@233 | 81 | jz4740_gpio_ctrl_update(gpio_port_base, GPIO_GPALR, 0xC0000000, 0x40000000); |
paul@233 | 82 | jz4740_gpio_ctrl_update(gpio_port_base, GPIO_GPAUR, 0x0000FFFF, 0x00005555); |
paul@57 | 83 | #else |
paul@0 | 84 | /* |
paul@233 | 85 | Initialize NAND Flash Pins (gpio_as_nand) |
paul@233 | 86 | CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# |
paul@233 | 87 | */ |
paul@233 | 88 | |
paul@233 | 89 | gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 1); |
paul@233 | 90 | |
paul@233 | 91 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x02018000); |
paul@233 | 92 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x02018000); |
paul@233 | 93 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x02018000); |
paul@233 | 94 | |
paul@233 | 95 | gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 2); |
paul@233 | 96 | |
paul@233 | 97 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x30000000); |
paul@233 | 98 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x30000000); |
paul@233 | 99 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x30000000); |
paul@233 | 100 | |
paul@233 | 101 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNC, 0x40000000); |
paul@233 | 102 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x40000000); |
paul@233 | 103 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXDIRC, 0x40000000); |
paul@233 | 104 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x40000000); |
paul@233 | 105 | |
paul@233 | 106 | gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 1); |
paul@233 | 107 | |
paul@233 | 108 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x00400000); |
paul@233 | 109 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x00400000); |
paul@0 | 110 | |
paul@0 | 111 | /* |
paul@233 | 112 | Initialize SDRAM pins (gpio_as_sdram_16bit_4720) |
paul@233 | 113 | D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, |
paul@233 | 114 | RDWE#, CKO#, WE0#, WE1# |
paul@233 | 115 | */ |
paul@233 | 116 | |
paul@233 | 117 | gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 0); |
paul@233 | 118 | |
paul@233 | 119 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x5442bfaa); |
paul@233 | 120 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x5442bfaa); |
paul@233 | 121 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x5442bfaa); |
paul@233 | 122 | |
paul@233 | 123 | gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 1); |
paul@233 | 124 | |
paul@233 | 125 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x81f9ffff); |
paul@233 | 126 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x81f9ffff); |
paul@233 | 127 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x81f9ffff); |
paul@233 | 128 | |
paul@233 | 129 | gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 2); |
paul@233 | 130 | |
paul@233 | 131 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x01000000); |
paul@233 | 132 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x01000000); |
paul@233 | 133 | jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x01000000); |
paul@45 | 134 | #endif |
paul@6 | 135 | } |
paul@0 | 136 | |
paul@195 | 137 | void pll_init() |
paul@0 | 138 | { |
paul@0 | 139 | register unsigned int cfcr, plcr1; |
paul@0 | 140 | int nf, pllout2; |
paul@0 | 141 | |
paul@17 | 142 | /* See CPCCR (Clock Control Register). |
paul@17 | 143 | * 0 == same frequency; 2 == f/3 |
paul@17 | 144 | */ |
paul@17 | 145 | |
paul@0 | 146 | cfcr = CPM_CPCCR_CLKOEN | |
paul@17 | 147 | CPM_CPCCR_PCS | |
paul@17 | 148 | (0 << CPM_CPCCR_CDIV_BIT) | |
paul@17 | 149 | (2 << CPM_CPCCR_HDIV_BIT) | |
paul@17 | 150 | (2 << CPM_CPCCR_PDIV_BIT) | |
paul@17 | 151 | (2 << CPM_CPCCR_MDIV_BIT) | |
paul@17 | 152 | (2 << CPM_CPCCR_LDIV_BIT); |
paul@0 | 153 | |
paul@17 | 154 | /* Init USB Host clock. |
paul@17 | 155 | * Desired frequency == 48MHz |
paul@17 | 156 | */ |
paul@17 | 157 | |
paul@33 | 158 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 159 | cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); |
paul@33 | 160 | #else |
paul@33 | 161 | /* Determine the divider clock output based on the PCS bit. */ |
paul@33 | 162 | pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); |
paul@33 | 163 | |
paul@33 | 164 | /* Divisor == UHCCDR + 1 */ |
paul@230 | 165 | jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_UHCCDR, pllout2 / 48000000 - 1); |
paul@33 | 166 | #endif |
paul@0 | 167 | |
paul@17 | 168 | nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; |
paul@17 | 169 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
paul@17 | 170 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
paul@17 | 171 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
paul@17 | 172 | CPM_CPPCR_PLLEN; /* enable PLL */ |
paul@0 | 173 | |
paul@17 | 174 | /* Update PLL and wait. */ |
paul@17 | 175 | |
paul@230 | 176 | jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPCCR, cfcr); |
paul@230 | 177 | jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPPCR, plcr1); |
paul@230 | 178 | while (!jz4740_cpm_have_pll((void *) CPM_BASE)); |
paul@0 | 179 | } |
paul@0 | 180 | |
paul@195 | 181 | void sdram_init() |
paul@0 | 182 | { |
paul@0 | 183 | register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; |
paul@0 | 184 | |
paul@0 | 185 | unsigned int cas_latency_sdmr[2] = { |
paul@0 | 186 | EMC_SDMR_CAS_2, |
paul@0 | 187 | EMC_SDMR_CAS_3, |
paul@0 | 188 | }; |
paul@0 | 189 | |
paul@0 | 190 | unsigned int cas_latency_dmcr[2] = { |
paul@0 | 191 | 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ |
paul@0 | 192 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
paul@0 | 193 | }; |
paul@0 | 194 | |
paul@230 | 195 | cpu_clk = jz4740_cpm_get_cpu_frequency((void *) CPM_BASE); |
paul@230 | 196 | mem_clk = jz4740_cpm_get_memory_frequency((void *) CPM_BASE); |
paul@0 | 197 | |
paul@0 | 198 | REG_EMC_BCR = 0; /* Disable bus release */ |
paul@0 | 199 | REG_EMC_RTCSR = 0; /* Disable clock for counting */ |
paul@0 | 200 | |
paul@0 | 201 | /* Fault DMCR value for mode register setting*/ |
paul@30 | 202 | dmcr0 = (0<<EMC_DMCR_RA_BIT) | |
paul@30 | 203 | (0<<EMC_DMCR_CA_BIT) | |
paul@30 | 204 | (0<<EMC_DMCR_BA_BIT) | |
paul@27 | 205 | (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 206 | EMC_DMCR_EPIN | |
paul@0 | 207 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 208 | |
paul@0 | 209 | /* Basic DMCR value */ |
paul@30 | 210 | dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | |
paul@30 | 211 | ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | |
paul@30 | 212 | ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | |
paul@27 | 213 | (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 214 | EMC_DMCR_EPIN | |
paul@0 | 215 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 216 | |
paul@0 | 217 | /* SDRAM timimg */ |
paul@0 | 218 | ns = 1000000000 / mem_clk; |
paul@0 | 219 | tmp = SDRAM_TRAS/ns; |
paul@0 | 220 | if (tmp < 4) tmp = 4; |
paul@0 | 221 | if (tmp > 11) tmp = 11; |
paul@0 | 222 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); |
paul@0 | 223 | tmp = SDRAM_RCD/ns; |
paul@0 | 224 | if (tmp > 3) tmp = 3; |
paul@0 | 225 | dmcr |= (tmp << EMC_DMCR_RCD_BIT); |
paul@0 | 226 | tmp = SDRAM_TPC/ns; |
paul@0 | 227 | if (tmp > 7) tmp = 7; |
paul@0 | 228 | dmcr |= (tmp << EMC_DMCR_TPC_BIT); |
paul@0 | 229 | tmp = SDRAM_TRWL/ns; |
paul@0 | 230 | if (tmp > 3) tmp = 3; |
paul@0 | 231 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT); |
paul@0 | 232 | tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; |
paul@0 | 233 | if (tmp > 14) tmp = 14; |
paul@0 | 234 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); |
paul@0 | 235 | |
paul@0 | 236 | /* SDRAM mode value */ |
paul@0 | 237 | sdmode = EMC_SDMR_BT_SEQ | |
paul@0 | 238 | EMC_SDMR_OM_NORMAL | |
paul@0 | 239 | EMC_SDMR_BL_4 | |
paul@0 | 240 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 241 | |
paul@33 | 242 | /* jz4730 additional measures */ |
paul@33 | 243 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 244 | if (FW_SDRAM_BW16) |
paul@33 | 245 | sdmode <<= 1; |
paul@33 | 246 | else |
paul@33 | 247 | sdmode <<= 2; |
paul@33 | 248 | #endif |
paul@33 | 249 | |
paul@0 | 250 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
paul@0 | 251 | REG_EMC_DMCR = dmcr; |
paul@0 | 252 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 253 | |
paul@33 | 254 | /* jz4730 additional measures */ |
paul@33 | 255 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 256 | REG8(EMC_SDMR1|sdmode) = 0; |
paul@33 | 257 | #endif |
paul@33 | 258 | |
paul@0 | 259 | /* Wait for precharge, > 200us */ |
paul@0 | 260 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 261 | while (tmp--); |
paul@0 | 262 | |
paul@0 | 263 | /* Stage 2. Enable auto-refresh */ |
paul@0 | 264 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; |
paul@0 | 265 | |
paul@0 | 266 | tmp = SDRAM_TREF/ns; |
paul@0 | 267 | tmp = tmp/64 + 1; |
paul@0 | 268 | if (tmp > 0xff) tmp = 0xff; |
paul@0 | 269 | REG_EMC_RTCOR = tmp; |
paul@0 | 270 | REG_EMC_RTCNT = 0; |
paul@0 | 271 | REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ |
paul@0 | 272 | |
paul@0 | 273 | /* Wait for number of auto-refresh cycles */ |
paul@0 | 274 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 275 | while (tmp--); |
paul@0 | 276 | |
paul@0 | 277 | /* Stage 3. Mode Register Set */ |
paul@0 | 278 | REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 279 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 280 | |
paul@33 | 281 | /* jz4730 additional measures */ |
paul@33 | 282 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 283 | REG8(EMC_SDMR1|sdmode) = 0; |
paul@33 | 284 | #endif |
paul@33 | 285 | |
paul@0 | 286 | /* Set back to basic DMCR value */ |
paul@0 | 287 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 288 | |
paul@0 | 289 | /* everything is ok now */ |
paul@0 | 290 | } |