paul@16 | 1 | /* |
paul@16 | 2 | * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools. |
paul@16 | 3 | * |
paul@16 | 4 | * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> |
paul@16 | 5 | * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> |
paul@16 | 6 | * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> |
paul@16 | 7 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@16 | 8 | * |
paul@16 | 9 | * This program is free software; you can redistribute it and/or modify it under |
paul@16 | 10 | * the terms of the GNU General Public License as published by the Free Software |
paul@16 | 11 | * Foundation; either version 3 of the License, or (at your option) any later |
paul@16 | 12 | * version. |
paul@16 | 13 | * |
paul@16 | 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
paul@16 | 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
paul@16 | 16 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more |
paul@16 | 17 | * details. |
paul@16 | 18 | * |
paul@16 | 19 | * You should have received a copy of the GNU General Public License along with |
paul@16 | 20 | * this program. If not, see <http://www.gnu.org/licenses/>. |
paul@16 | 21 | */ |
paul@16 | 22 | |
paul@16 | 23 | #include "jz4740.h" |
paul@16 | 24 | #include "configs.h" |
paul@16 | 25 | #include "nanonote.h" |
paul@16 | 26 | |
paul@16 | 27 | /* Later initialisation functions. */ |
paul@16 | 28 | |
paul@16 | 29 | void gpio_init2(void) |
paul@16 | 30 | { |
paul@16 | 31 | /* |
paul@16 | 32 | * Initialize LCD pins |
paul@16 | 33 | */ |
paul@16 | 34 | __gpio_as_slcd_8bit(); |
paul@16 | 35 | |
paul@16 | 36 | /* |
paul@16 | 37 | * Initialize MSC pins |
paul@16 | 38 | */ |
paul@16 | 39 | __gpio_as_msc(); |
paul@16 | 40 | |
paul@16 | 41 | /* |
paul@16 | 42 | * Initialize Other pins |
paul@16 | 43 | */ |
paul@16 | 44 | unsigned int i; |
paul@16 | 45 | for (i = 0; i < 7; i++){ |
paul@16 | 46 | __gpio_as_input(GPIO_KEYIN_BASE + i); |
paul@16 | 47 | __gpio_enable_pull(GPIO_KEYIN_BASE + i); |
paul@16 | 48 | } |
paul@16 | 49 | |
paul@16 | 50 | for (i = 0; i < 8; i++) { |
paul@16 | 51 | __gpio_as_output(GPIO_KEYOUT_BASE + i); |
paul@16 | 52 | __gpio_clear_pin(GPIO_KEYOUT_BASE + i); |
paul@16 | 53 | } |
paul@16 | 54 | |
paul@16 | 55 | /* enable the TP4, TP5 as UART0 */ |
paul@16 | 56 | __gpio_jtag_to_uart0(); |
paul@16 | 57 | |
paul@16 | 58 | __gpio_as_input(GPIO_KEYIN_8); |
paul@16 | 59 | __gpio_enable_pull(GPIO_KEYIN_8); |
paul@16 | 60 | |
paul@16 | 61 | __gpio_as_output(GPIO_AUDIO_POP); |
paul@16 | 62 | __gpio_set_pin(GPIO_AUDIO_POP); |
paul@16 | 63 | |
paul@16 | 64 | __gpio_as_output(GPIO_LCD_CS); |
paul@16 | 65 | __gpio_clear_pin(GPIO_LCD_CS); |
paul@16 | 66 | |
paul@16 | 67 | __gpio_as_output(GPIO_AMP_EN); |
paul@16 | 68 | __gpio_clear_pin(GPIO_AMP_EN); |
paul@16 | 69 | |
paul@16 | 70 | __gpio_as_output(GPIO_SDPW_EN); |
paul@16 | 71 | __gpio_disable_pull(GPIO_SDPW_EN); |
paul@16 | 72 | __gpio_clear_pin(GPIO_SDPW_EN); |
paul@16 | 73 | |
paul@16 | 74 | __gpio_as_input(GPIO_SD_DETECT); |
paul@16 | 75 | __gpio_disable_pull(GPIO_SD_DETECT); |
paul@16 | 76 | |
paul@16 | 77 | __gpio_as_input(GPIO_USB_DETECT); |
paul@16 | 78 | __gpio_enable_pull(GPIO_USB_DETECT); |
paul@16 | 79 | } |
paul@16 | 80 | |
paul@16 | 81 | void cpm_init(void) |
paul@16 | 82 | { |
paul@16 | 83 | __cpm_stop_ipu(); |
paul@16 | 84 | __cpm_stop_cim(); |
paul@16 | 85 | __cpm_stop_i2c(); |
paul@16 | 86 | __cpm_stop_ssi(); |
paul@16 | 87 | __cpm_stop_uart1(); |
paul@16 | 88 | __cpm_stop_sadc(); |
paul@16 | 89 | __cpm_stop_uhc(); |
paul@16 | 90 | __cpm_stop_udc(); |
paul@16 | 91 | __cpm_stop_aic1(); |
paul@16 | 92 | /* __cpm_stop_aic2();*/ |
paul@16 | 93 | } |
paul@16 | 94 | |
paul@16 | 95 | void rtc_init(void) |
paul@16 | 96 | { |
paul@16 | 97 | while ( !__rtc_write_ready()); |
paul@16 | 98 | __rtc_enable_alarm(); /* enable alarm */ |
paul@16 | 99 | |
paul@16 | 100 | while ( !__rtc_write_ready()); |
paul@16 | 101 | REG_RTC_RGR = 0x00007fff; /* type value */ |
paul@16 | 102 | |
paul@16 | 103 | while ( !__rtc_write_ready()); |
paul@16 | 104 | REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ |
paul@16 | 105 | |
paul@16 | 106 | while ( !__rtc_write_ready()); |
paul@16 | 107 | REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ |
paul@16 | 108 | } |
paul@16 | 109 | |
paul@16 | 110 | unsigned long get_memory_size(void) |
paul@16 | 111 | { |
paul@16 | 112 | unsigned int dmcr; |
paul@16 | 113 | unsigned int rows, cols, dw, banks; |
paul@16 | 114 | unsigned long size; |
paul@16 | 115 | |
paul@16 | 116 | dmcr = REG_EMC_DMCR; |
paul@16 | 117 | rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); |
paul@16 | 118 | cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); |
paul@16 | 119 | dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; |
paul@16 | 120 | banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; |
paul@16 | 121 | |
paul@16 | 122 | size = (1 << (rows + cols)) * dw * banks; |
paul@16 | 123 | |
paul@16 | 124 | return size; |
paul@16 | 125 | } |
paul@16 | 126 | |
paul@16 | 127 | /* Timer routines. */ |
paul@16 | 128 | |
paul@16 | 129 | #define TIMER_CHAN 0 |
paul@16 | 130 | #define TIMER_FDATA 0xffff /* Timer full data value */ |
paul@16 | 131 | #define TIMER_HZ CONFIG_SYS_HZ |
paul@16 | 132 | |
paul@16 | 133 | #define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ |
paul@16 | 134 | |
paul@16 | 135 | static unsigned long timestamp; |
paul@16 | 136 | static unsigned long lastdec; |
paul@16 | 137 | |
paul@16 | 138 | void reset_timer_masked(void); |
paul@16 | 139 | unsigned long get_timer_masked(void); |
paul@16 | 140 | void udelay_masked(unsigned long usec); |
paul@16 | 141 | |
paul@16 | 142 | /* |
paul@16 | 143 | * timer without interrupts |
paul@16 | 144 | */ |
paul@16 | 145 | |
paul@16 | 146 | int timer_init(void) |
paul@16 | 147 | { |
paul@16 | 148 | REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; |
paul@16 | 149 | REG_TCU_TCNT(TIMER_CHAN) = 0; |
paul@16 | 150 | REG_TCU_TDHR(TIMER_CHAN) = 0; |
paul@16 | 151 | REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; |
paul@16 | 152 | |
paul@16 | 153 | REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ |
paul@16 | 154 | REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ |
paul@16 | 155 | REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ |
paul@16 | 156 | |
paul@16 | 157 | lastdec = 0; |
paul@16 | 158 | timestamp = 0; |
paul@16 | 159 | |
paul@16 | 160 | return 0; |
paul@16 | 161 | } |
paul@16 | 162 | |
paul@16 | 163 | void reset_timer(void) |
paul@16 | 164 | { |
paul@16 | 165 | reset_timer_masked (); |
paul@16 | 166 | } |
paul@16 | 167 | |
paul@16 | 168 | unsigned long get_timer(unsigned long base) |
paul@16 | 169 | { |
paul@16 | 170 | return get_timer_masked () - base; |
paul@16 | 171 | } |
paul@16 | 172 | |
paul@16 | 173 | void set_timer(unsigned long t) |
paul@16 | 174 | { |
paul@16 | 175 | timestamp = t; |
paul@16 | 176 | } |
paul@16 | 177 | |
paul@16 | 178 | void udelay (unsigned long usec) |
paul@16 | 179 | { |
paul@16 | 180 | unsigned long tmo,tmp; |
paul@16 | 181 | |
paul@16 | 182 | /* normalize */ |
paul@16 | 183 | if (usec >= 1000) { |
paul@16 | 184 | tmo = usec / 1000; |
paul@16 | 185 | tmo *= TIMER_HZ; |
paul@16 | 186 | tmo /= 1000; |
paul@16 | 187 | } |
paul@16 | 188 | else { |
paul@16 | 189 | if (usec >= 1) { |
paul@16 | 190 | tmo = usec * TIMER_HZ; |
paul@16 | 191 | tmo /= (1000*1000); |
paul@16 | 192 | } |
paul@16 | 193 | else |
paul@16 | 194 | tmo = 1; |
paul@16 | 195 | } |
paul@16 | 196 | |
paul@16 | 197 | /* check for rollover during this delay */ |
paul@16 | 198 | tmp = get_timer (0); |
paul@16 | 199 | if ((tmp + tmo) < tmp ) |
paul@16 | 200 | reset_timer_masked(); /* timer would roll over */ |
paul@16 | 201 | else |
paul@16 | 202 | tmo += tmp; |
paul@16 | 203 | |
paul@16 | 204 | while (get_timer_masked () < tmo); |
paul@16 | 205 | } |
paul@16 | 206 | |
paul@16 | 207 | void reset_timer_masked (void) |
paul@16 | 208 | { |
paul@16 | 209 | /* reset time */ |
paul@16 | 210 | lastdec = READ_TIMER; |
paul@16 | 211 | timestamp = 0; |
paul@16 | 212 | } |
paul@16 | 213 | |
paul@16 | 214 | unsigned long get_timer_masked (void) |
paul@16 | 215 | { |
paul@16 | 216 | unsigned long now = READ_TIMER; |
paul@16 | 217 | |
paul@16 | 218 | if (lastdec <= now) { |
paul@16 | 219 | /* normal mode */ |
paul@16 | 220 | timestamp += (now - lastdec); |
paul@16 | 221 | } else { |
paul@16 | 222 | /* we have an overflow ... */ |
paul@16 | 223 | timestamp += TIMER_FDATA + now - lastdec; |
paul@16 | 224 | } |
paul@16 | 225 | lastdec = now; |
paul@16 | 226 | |
paul@16 | 227 | return timestamp; |
paul@16 | 228 | } |
paul@16 | 229 | |
paul@16 | 230 | void udelay_masked (unsigned long usec) |
paul@16 | 231 | { |
paul@16 | 232 | unsigned long tmo; |
paul@16 | 233 | unsigned long endtime; |
paul@16 | 234 | signed long diff; |
paul@16 | 235 | |
paul@16 | 236 | /* normalize */ |
paul@16 | 237 | if (usec >= 1000) { |
paul@16 | 238 | tmo = usec / 1000; |
paul@16 | 239 | tmo *= TIMER_HZ; |
paul@16 | 240 | tmo /= 1000; |
paul@16 | 241 | } else { |
paul@16 | 242 | if (usec > 1) { |
paul@16 | 243 | tmo = usec * TIMER_HZ; |
paul@16 | 244 | tmo /= (1000*1000); |
paul@16 | 245 | } else { |
paul@16 | 246 | tmo = 1; |
paul@16 | 247 | } |
paul@16 | 248 | } |
paul@16 | 249 | |
paul@16 | 250 | endtime = get_timer_masked () + tmo; |
paul@16 | 251 | |
paul@16 | 252 | do { |
paul@16 | 253 | unsigned long now = get_timer_masked (); |
paul@16 | 254 | diff = endtime - now; |
paul@16 | 255 | } while (diff >= 0); |
paul@16 | 256 | } |
paul@16 | 257 | |
paul@16 | 258 | /* |
paul@16 | 259 | * This function is derived from PowerPC code (read timebase as long long). |
paul@16 | 260 | * On MIPS it just returns the timer value. |
paul@16 | 261 | */ |
paul@16 | 262 | unsigned long long get_ticks(void) |
paul@16 | 263 | { |
paul@16 | 264 | return get_timer(0); |
paul@16 | 265 | } |
paul@16 | 266 | |
paul@16 | 267 | /* |
paul@16 | 268 | * This function is derived from PowerPC code (timebase clock frequency). |
paul@16 | 269 | * On MIPS it returns the number of timer ticks per second. |
paul@16 | 270 | */ |
paul@16 | 271 | unsigned long get_tbclk (void) |
paul@16 | 272 | { |
paul@16 | 273 | return TIMER_HZ; |
paul@16 | 274 | } |
paul@16 | 275 | |
paul@16 | 276 | /* CPU-specific routines from U-Boot. |
paul@16 | 277 | See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@16 | 278 | See: u-boot/arch/mips/include/asm/cacheops.h |
paul@16 | 279 | */ |
paul@16 | 280 | |
paul@16 | 281 | #define Index_Store_Tag_I 0x08 |
paul@16 | 282 | #define Index_Writeback_Inv_D 0x15 |
paul@16 | 283 | |
paul@16 | 284 | void flush_icache_all(void) |
paul@16 | 285 | { |
paul@16 | 286 | u32 addr, t = 0; |
paul@16 | 287 | |
paul@16 | 288 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
paul@16 | 289 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
paul@16 | 290 | |
paul@16 | 291 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
paul@16 | 292 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@16 | 293 | asm volatile ( |
paul@16 | 294 | ".set mips3\n\t" |
paul@16 | 295 | " cache %0, 0(%1)\n\t" |
paul@16 | 296 | ".set mips2\n\t" |
paul@16 | 297 | : |
paul@16 | 298 | : "I" (Index_Store_Tag_I), "r"(addr)); |
paul@16 | 299 | } |
paul@16 | 300 | |
paul@16 | 301 | /* invalicate btb */ |
paul@16 | 302 | asm volatile ( |
paul@16 | 303 | ".set mips32\n\t" |
paul@16 | 304 | "mfc0 %0, $16, 7\n\t" |
paul@16 | 305 | "nop\n\t" |
paul@16 | 306 | "ori %0,2\n\t" |
paul@16 | 307 | "mtc0 %0, $16, 7\n\t" |
paul@16 | 308 | ".set mips2\n\t" |
paul@16 | 309 | : |
paul@16 | 310 | : "r" (t)); |
paul@16 | 311 | } |
paul@16 | 312 | |
paul@16 | 313 | void flush_dcache_all(void) |
paul@16 | 314 | { |
paul@16 | 315 | u32 addr; |
paul@16 | 316 | |
paul@16 | 317 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
paul@16 | 318 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@16 | 319 | asm volatile ( |
paul@16 | 320 | ".set mips3\n\t" |
paul@16 | 321 | " cache %0, 0(%1)\n\t" |
paul@16 | 322 | ".set mips2\n\t" |
paul@16 | 323 | : |
paul@16 | 324 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
paul@16 | 325 | } |
paul@16 | 326 | |
paul@16 | 327 | asm volatile ("sync"); |
paul@16 | 328 | } |
paul@16 | 329 | |
paul@16 | 330 | void flush_cache_all(void) |
paul@16 | 331 | { |
paul@16 | 332 | flush_dcache_all(); |
paul@16 | 333 | flush_icache_all(); |
paul@16 | 334 | } |