paul@0 | 1 | /* |
paul@0 | 2 | * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> |
paul@0 | 6 | * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> |
paul@0 | 7 | * |
paul@0 | 8 | * This program is free software; you can redistribute it and/or modify it under |
paul@0 | 9 | * the terms of the GNU General Public License as published by the Free Software |
paul@0 | 10 | * Foundation; either version 3 of the License, or (at your option) any later |
paul@0 | 11 | * version. |
paul@0 | 12 | * |
paul@0 | 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
paul@0 | 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
paul@0 | 15 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more |
paul@0 | 16 | * details. |
paul@0 | 17 | * |
paul@0 | 18 | * You should have received a copy of the GNU General Public License along with |
paul@0 | 19 | * this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 20 | */ |
paul@0 | 21 | |
paul@0 | 22 | #include "jz4740.h" |
paul@0 | 23 | #include "configs.h" |
paul@2 | 24 | #include "nanonote.h" |
paul@0 | 25 | |
paul@0 | 26 | void gpio_init(void) |
paul@0 | 27 | { |
paul@0 | 28 | /* |
paul@0 | 29 | * Initialize NAND Flash Pins |
paul@0 | 30 | */ |
paul@0 | 31 | __gpio_as_nand(); |
paul@0 | 32 | |
paul@0 | 33 | /* |
paul@0 | 34 | * Initialize SDRAM pins |
paul@0 | 35 | */ |
paul@0 | 36 | __gpio_as_sdram_32bit(); |
paul@0 | 37 | |
paul@0 | 38 | /* |
paul@0 | 39 | * Initialize LCD pins |
paul@0 | 40 | */ |
paul@2 | 41 | __gpio_as_slcd_8bit(); |
paul@0 | 42 | |
paul@0 | 43 | /* |
paul@0 | 44 | * Initialize MSC pins |
paul@0 | 45 | */ |
paul@0 | 46 | __gpio_as_msc(); |
paul@0 | 47 | |
paul@0 | 48 | /* |
paul@0 | 49 | * Initialize Other pins |
paul@0 | 50 | */ |
paul@0 | 51 | unsigned int i; |
paul@0 | 52 | for (i = 0; i < 7; i++){ |
paul@0 | 53 | __gpio_as_input(GPIO_KEYIN_BASE + i); |
paul@0 | 54 | __gpio_enable_pull(GPIO_KEYIN_BASE + i); |
paul@0 | 55 | } |
paul@0 | 56 | |
paul@0 | 57 | for (i = 0; i < 8; i++) { |
paul@0 | 58 | __gpio_as_output(GPIO_KEYOUT_BASE + i); |
paul@0 | 59 | __gpio_clear_pin(GPIO_KEYOUT_BASE + i); |
paul@0 | 60 | } |
paul@0 | 61 | |
paul@0 | 62 | /* enable the TP4, TP5 as UART0 */ |
paul@0 | 63 | __gpio_jtag_to_uart0(); |
paul@0 | 64 | |
paul@0 | 65 | __gpio_as_input(GPIO_KEYIN_8); |
paul@0 | 66 | __gpio_enable_pull(GPIO_KEYIN_8); |
paul@0 | 67 | |
paul@0 | 68 | __gpio_as_output(GPIO_AUDIO_POP); |
paul@0 | 69 | __gpio_set_pin(GPIO_AUDIO_POP); |
paul@0 | 70 | |
paul@0 | 71 | __gpio_as_output(GPIO_LCD_CS); |
paul@0 | 72 | __gpio_clear_pin(GPIO_LCD_CS); |
paul@0 | 73 | |
paul@0 | 74 | __gpio_as_output(GPIO_AMP_EN); |
paul@0 | 75 | __gpio_clear_pin(GPIO_AMP_EN); |
paul@0 | 76 | |
paul@0 | 77 | __gpio_as_output(GPIO_SDPW_EN); |
paul@0 | 78 | __gpio_disable_pull(GPIO_SDPW_EN); |
paul@0 | 79 | __gpio_clear_pin(GPIO_SDPW_EN); |
paul@0 | 80 | |
paul@0 | 81 | __gpio_as_input(GPIO_SD_DETECT); |
paul@0 | 82 | __gpio_disable_pull(GPIO_SD_DETECT); |
paul@0 | 83 | |
paul@0 | 84 | __gpio_as_input(GPIO_USB_DETECT); |
paul@0 | 85 | __gpio_enable_pull(GPIO_USB_DETECT); |
paul@0 | 86 | } |
paul@0 | 87 | |
paul@0 | 88 | void cpm_init(void) |
paul@0 | 89 | { |
paul@0 | 90 | __cpm_stop_ipu(); |
paul@0 | 91 | __cpm_stop_cim(); |
paul@0 | 92 | __cpm_stop_i2c(); |
paul@0 | 93 | __cpm_stop_ssi(); |
paul@0 | 94 | __cpm_stop_uart1(); |
paul@0 | 95 | __cpm_stop_sadc(); |
paul@0 | 96 | __cpm_stop_uhc(); |
paul@0 | 97 | __cpm_stop_udc(); |
paul@0 | 98 | __cpm_stop_aic1(); |
paul@0 | 99 | /* __cpm_stop_aic2();*/ |
paul@0 | 100 | } |
paul@0 | 101 | |
paul@0 | 102 | void pll_init(void) |
paul@0 | 103 | { |
paul@0 | 104 | register unsigned int cfcr, plcr1; |
paul@0 | 105 | int n2FR[33] = { |
paul@0 | 106 | 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, |
paul@0 | 107 | 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, |
paul@0 | 108 | 9 |
paul@0 | 109 | }; |
paul@0 | 110 | int nf, pllout2; |
paul@0 | 111 | |
paul@0 | 112 | cfcr = CPM_CPCCR_CLKOEN | |
paul@0 | 113 | (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | |
paul@0 | 114 | (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | |
paul@0 | 115 | (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | |
paul@0 | 116 | (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | |
paul@0 | 117 | (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); |
paul@0 | 118 | |
paul@0 | 119 | pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); |
paul@0 | 120 | |
paul@0 | 121 | /* Init USB Host clock, pllout2 must be n*48MHz */ |
paul@0 | 122 | REG_CPM_UHCCDR = pllout2 / 48000000 - 1; |
paul@0 | 123 | |
paul@0 | 124 | nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; |
paul@0 | 125 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
paul@0 | 126 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
paul@0 | 127 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
paul@0 | 128 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
paul@0 | 129 | CPM_CPPCR_PLLEN; /* enable PLL */ |
paul@0 | 130 | |
paul@0 | 131 | /* init PLL */ |
paul@0 | 132 | REG_CPM_CPCCR = cfcr; |
paul@0 | 133 | REG_CPM_CPPCR = plcr1; |
paul@0 | 134 | } |
paul@0 | 135 | |
paul@0 | 136 | void sdram_init(void) |
paul@0 | 137 | { |
paul@0 | 138 | register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; |
paul@0 | 139 | |
paul@0 | 140 | unsigned int cas_latency_sdmr[2] = { |
paul@0 | 141 | EMC_SDMR_CAS_2, |
paul@0 | 142 | EMC_SDMR_CAS_3, |
paul@0 | 143 | }; |
paul@0 | 144 | |
paul@0 | 145 | unsigned int cas_latency_dmcr[2] = { |
paul@0 | 146 | 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ |
paul@0 | 147 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
paul@0 | 148 | }; |
paul@0 | 149 | |
paul@0 | 150 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@0 | 151 | |
paul@0 | 152 | cpu_clk = CFG_CPU_SPEED; |
paul@0 | 153 | mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; |
paul@0 | 154 | |
paul@0 | 155 | REG_EMC_BCR = 0; /* Disable bus release */ |
paul@0 | 156 | REG_EMC_RTCSR = 0; /* Disable clock for counting */ |
paul@0 | 157 | |
paul@0 | 158 | /* Fault DMCR value for mode register setting*/ |
paul@0 | 159 | #define SDRAM_ROW0 11 |
paul@0 | 160 | #define SDRAM_COL0 8 |
paul@0 | 161 | #define SDRAM_BANK40 0 |
paul@0 | 162 | |
paul@0 | 163 | dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | |
paul@0 | 164 | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | |
paul@0 | 165 | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | |
paul@0 | 166 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 167 | EMC_DMCR_EPIN | |
paul@0 | 168 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 169 | |
paul@0 | 170 | /* Basic DMCR value */ |
paul@0 | 171 | dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | |
paul@0 | 172 | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | |
paul@0 | 173 | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | |
paul@0 | 174 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 175 | EMC_DMCR_EPIN | |
paul@0 | 176 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 177 | |
paul@0 | 178 | /* SDRAM timimg */ |
paul@0 | 179 | ns = 1000000000 / mem_clk; |
paul@0 | 180 | tmp = SDRAM_TRAS/ns; |
paul@0 | 181 | if (tmp < 4) tmp = 4; |
paul@0 | 182 | if (tmp > 11) tmp = 11; |
paul@0 | 183 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); |
paul@0 | 184 | tmp = SDRAM_RCD/ns; |
paul@0 | 185 | if (tmp > 3) tmp = 3; |
paul@0 | 186 | dmcr |= (tmp << EMC_DMCR_RCD_BIT); |
paul@0 | 187 | tmp = SDRAM_TPC/ns; |
paul@0 | 188 | if (tmp > 7) tmp = 7; |
paul@0 | 189 | dmcr |= (tmp << EMC_DMCR_TPC_BIT); |
paul@0 | 190 | tmp = SDRAM_TRWL/ns; |
paul@0 | 191 | if (tmp > 3) tmp = 3; |
paul@0 | 192 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT); |
paul@0 | 193 | tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; |
paul@0 | 194 | if (tmp > 14) tmp = 14; |
paul@0 | 195 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); |
paul@0 | 196 | |
paul@0 | 197 | /* SDRAM mode value */ |
paul@0 | 198 | sdmode = EMC_SDMR_BT_SEQ | |
paul@0 | 199 | EMC_SDMR_OM_NORMAL | |
paul@0 | 200 | EMC_SDMR_BL_4 | |
paul@0 | 201 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 202 | |
paul@0 | 203 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
paul@0 | 204 | REG_EMC_DMCR = dmcr; |
paul@0 | 205 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 206 | |
paul@0 | 207 | /* Wait for precharge, > 200us */ |
paul@0 | 208 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 209 | while (tmp--); |
paul@0 | 210 | |
paul@0 | 211 | /* Stage 2. Enable auto-refresh */ |
paul@0 | 212 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; |
paul@0 | 213 | |
paul@0 | 214 | tmp = SDRAM_TREF/ns; |
paul@0 | 215 | tmp = tmp/64 + 1; |
paul@0 | 216 | if (tmp > 0xff) tmp = 0xff; |
paul@0 | 217 | REG_EMC_RTCOR = tmp; |
paul@0 | 218 | REG_EMC_RTCNT = 0; |
paul@0 | 219 | REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ |
paul@0 | 220 | |
paul@0 | 221 | /* Wait for number of auto-refresh cycles */ |
paul@0 | 222 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 223 | while (tmp--); |
paul@0 | 224 | |
paul@0 | 225 | /* Stage 3. Mode Register Set */ |
paul@0 | 226 | REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 227 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 228 | |
paul@0 | 229 | /* Set back to basic DMCR value */ |
paul@0 | 230 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 231 | |
paul@0 | 232 | /* everything is ok now */ |
paul@0 | 233 | } |