NanoPayload

Annotated board-nanonote.c

2:9c7a60352d9e
2015-06-05 Paul Boddie Fixed payload building, header usage, and pin initialisation.
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/*
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 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools.
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 *
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 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
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 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
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 * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
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 *
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 * This program is free software; you can redistribute it and/or modify it under
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 * the terms of the GNU General Public License as published by the Free Software
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 * Foundation; either version 3 of the License, or (at your option) any later
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 * version.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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 * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
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 * details.
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 *
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 * You should have received a copy of the GNU General Public License along with
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 * this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include "jz4740.h"
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#include "configs.h"
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#include "nanonote.h"
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void gpio_init(void)
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{
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	/*
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	 * Initialize NAND Flash Pins
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	 */
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	__gpio_as_nand();
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	/*
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	 * Initialize SDRAM pins
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	 */
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	__gpio_as_sdram_32bit();
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	/*
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	 * Initialize LCD pins
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	 */
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	__gpio_as_slcd_8bit();
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	/*
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	 * Initialize MSC pins
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	 */
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	__gpio_as_msc();
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	/*
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	 * Initialize Other pins
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	 */
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	unsigned int i;
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	for (i = 0; i < 7; i++){
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		__gpio_as_input(GPIO_KEYIN_BASE + i);
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		__gpio_enable_pull(GPIO_KEYIN_BASE + i);
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	}
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	for (i = 0; i < 8; i++) {
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		__gpio_as_output(GPIO_KEYOUT_BASE + i);
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		__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
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	}
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	/* enable the TP4, TP5 as UART0 */
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	__gpio_jtag_to_uart0();
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	__gpio_as_input(GPIO_KEYIN_8);
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	__gpio_enable_pull(GPIO_KEYIN_8);
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	__gpio_as_output(GPIO_AUDIO_POP);
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	__gpio_set_pin(GPIO_AUDIO_POP);
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	__gpio_as_output(GPIO_LCD_CS);
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	__gpio_clear_pin(GPIO_LCD_CS);
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	__gpio_as_output(GPIO_AMP_EN);
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	__gpio_clear_pin(GPIO_AMP_EN);
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	__gpio_as_output(GPIO_SDPW_EN);
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	__gpio_disable_pull(GPIO_SDPW_EN);
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	__gpio_clear_pin(GPIO_SDPW_EN);
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	__gpio_as_input(GPIO_SD_DETECT);
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	__gpio_disable_pull(GPIO_SD_DETECT);
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	__gpio_as_input(GPIO_USB_DETECT);
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	__gpio_enable_pull(GPIO_USB_DETECT);
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}
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void cpm_init(void)
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{
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	__cpm_stop_ipu();
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	__cpm_stop_cim();
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	__cpm_stop_i2c();
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	__cpm_stop_ssi();
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	__cpm_stop_uart1();
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	__cpm_stop_sadc();
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	__cpm_stop_uhc();
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	__cpm_stop_udc();
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	__cpm_stop_aic1();
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/*	__cpm_stop_aic2();*/
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}
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void pll_init(void)
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{
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	register unsigned int cfcr, plcr1;
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	int n2FR[33] = {
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		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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		9
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	};
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	int nf, pllout2;
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	cfcr = CPM_CPCCR_CLKOEN |
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		(n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) |
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		(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
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		(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
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		(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
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		(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
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	pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
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	/* Init USB Host clock, pllout2 must be n*48MHz */
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	REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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	nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
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	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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		(0 << CPM_CPPCR_PLLN_BIT) |	/* RD=0, NR=2 */
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		(0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
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		(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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		CPM_CPPCR_PLLEN;                /* enable PLL */
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	/* init PLL */
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	REG_CPM_CPCCR = cfcr;
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	REG_CPM_CPPCR = plcr1;
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}
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void sdram_init(void)
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{
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	register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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	unsigned int cas_latency_sdmr[2] = {
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		EMC_SDMR_CAS_2,
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		EMC_SDMR_CAS_3,
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	};
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	unsigned int cas_latency_dmcr[2] = {
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		1 << EMC_DMCR_TCL_BIT,	/* CAS latency is 2 */
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		2 << EMC_DMCR_TCL_BIT	/* CAS latency is 3 */
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	};
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	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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	cpu_clk = CFG_CPU_SPEED;
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	mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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	REG_EMC_BCR = 0;	/* Disable bus release */
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	REG_EMC_RTCSR = 0;	/* Disable clock for counting */
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	/* Fault DMCR value for mode register setting*/
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#define SDRAM_ROW0    11
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#define SDRAM_COL0     8
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#define SDRAM_BANK40   0
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	dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
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		((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
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		(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
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		(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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		EMC_DMCR_EPIN |
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		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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	/* Basic DMCR value */
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	dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
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		((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
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		(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
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		(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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		EMC_DMCR_EPIN |
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		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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	/* SDRAM timimg */
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	ns = 1000000000 / mem_clk;
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	tmp = SDRAM_TRAS/ns;
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	if (tmp < 4) tmp = 4;
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	if (tmp > 11) tmp = 11;
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	dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
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	tmp = SDRAM_RCD/ns;
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	if (tmp > 3) tmp = 3;
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	dmcr |= (tmp << EMC_DMCR_RCD_BIT);
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	tmp = SDRAM_TPC/ns;
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	if (tmp > 7) tmp = 7;
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	dmcr |= (tmp << EMC_DMCR_TPC_BIT);
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	tmp = SDRAM_TRWL/ns;
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	if (tmp > 3) tmp = 3;
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	dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
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	tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
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	if (tmp > 14) tmp = 14;
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	dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
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	/* SDRAM mode value */
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	sdmode = EMC_SDMR_BT_SEQ | 
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		 EMC_SDMR_OM_NORMAL |
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		 EMC_SDMR_BL_4 | 
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		 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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	/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
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	REG_EMC_DMCR = dmcr;
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	REG8(EMC_SDMR0|sdmode) = 0;
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	/* Wait for precharge, > 200us */
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	tmp = (cpu_clk / 1000000) * 1000;
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	while (tmp--);
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	/* Stage 2. Enable auto-refresh */
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	REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
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	tmp = SDRAM_TREF/ns;
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	tmp = tmp/64 + 1;
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	if (tmp > 0xff) tmp = 0xff;
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	REG_EMC_RTCOR = tmp;
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	REG_EMC_RTCNT = 0;
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	REG_EMC_RTCSR = EMC_RTCSR_CKS_64;	/* Divisor is 64, CKO/64 */
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	/* Wait for number of auto-refresh cycles */
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	tmp = (cpu_clk / 1000000) * 1000;
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	while (tmp--);
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 	/* Stage 3. Mode Register Set */
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	REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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	REG8(EMC_SDMR0|sdmode) = 0;
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        /* Set back to basic DMCR value */
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	REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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	/* everything is ok now */
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}