NanoPayload

Annotated stage2/head2.S

68:beb796ba8f29
2015-06-23 Paul Boddie Attempted to add support for interrupts, although this does not currently work. Some handlers have been added, and minimal handlers to branch to them should be installed in the appropriate addresses utilised by the CPU. The program itself should gradually plot the test pattern but be interrupted and configured to draw clear regions periodically. stage2-non-pic
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/*
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 * Initialisation code for the stage 2 payload.
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 *
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 * Copyright 2009 (C) Qi Hardware Inc.
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 * Author: Wolfgang Spraul <wolfgang@sharism.cc>
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 *
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 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 3 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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.text
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.extern c_main
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.extern _tlb_entry
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.extern _exc_entry
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.extern _irq_entry
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.extern _end_entries
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.globl _start
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.set noreorder
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_start:
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	/* Initialise the stack. */
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	la $sp, 0x80080000
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	/* Copy TLB handling instructions. */
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	lui $t0, %hi(_tlb_entry)	/* start */
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	ori $t0, $t0, %lo(_tlb_entry)
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	li $t1, 0x80000000
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	lui $t2, %hi(_exc_entry)	/* end */
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	ori $t2, $t2, %lo(_exc_entry)
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_tlb_copy:
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	lw $t3, 0($t0)
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	addiu $t0, $t0, 4
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	sw $t3, 0($t1)
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	bne $t0, $t2, _tlb_copy
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	addiu $t1, $t1, 4		/* executed in delay slot before branch */
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	/* Copy exception handling instructions. */
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	move $t0, $t2			/* start */
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	li $t1, 0x80000180
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	lui $t2, %hi(_irq_entry)	/* end */
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	ori $t2, $t2, %lo(_irq_entry)
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_exc_copy:
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	lw $t3, 0($t0)
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	addiu $t0, $t0, 4
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	sw $t3, 0($t1)
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	bne $t0, $t2, _exc_copy
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	addiu $t1, $t1, 4		/* executed in delay slot before branch */
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	/* Copy IRQ handling instructions. */
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	move $t0, $t2			/* start */
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	li $t1, 0x80000200
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	lui $t2, %hi(_end_entries)	/* end */
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	ori $t2, $t2, %lo(_end_entries)
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_irq_copy:
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	lw $t3, 0($t0)
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	addiu $t0, $t0, 4
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	sw $t3, 0($t1)
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	bne $t0, $t2, _irq_copy
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	addiu $t1, $t1, 4		/* executed in delay slot before branch */
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	/* Initialise interrupts. */
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	mfc0 $t3, $12			/* CP0_STATUS */
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	nop
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	li $t4, 0xffbf00e0		/* BEV = 0 (not bootloader vectors); IM = disable all */
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	and $t3, $t3, $t4		/* ... KSU = 0 (kernel mode); ERL = 0; EXL = 0; IE = 0 */
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	li $t4, 0x0000ff04		/* IM = enable IM7..IM0; ERL = 1 (set by default) */
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	or $t3, $t3, $t4
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	mtc0 $t3, $12
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	nop
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	li $t3, 0x00800000		/* IV = 1 (use 0x80000200 for interrupts) */
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	mtc0 $t3, $13			/* CP0_CAUSE */
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	nop
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	mtc0 $zero, $15			/* CP0_EBASE (should be zero anyway) */
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	nop
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	/* Start the program. */
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	j c_main
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	nop
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.set reorder