paul@33 | 1 | /* |
paul@38 | 2 | * JzRISC LCD controller |
paul@33 | 3 | * |
paul@33 | 4 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
paul@93 | 5 | * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> |
paul@33 | 6 | * |
paul@33 | 7 | * This program is free software; you can redistribute it and/or |
paul@33 | 8 | * modify it under the terms of the GNU General Public License as |
paul@33 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@33 | 10 | * the License, or (at your option) any later version. |
paul@33 | 11 | * |
paul@33 | 12 | * This program is distributed in the hope that it will be useful, |
paul@33 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@33 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@33 | 15 | * GNU General Public License for more details. |
paul@33 | 16 | * |
paul@33 | 17 | * You should have received a copy of the GNU General Public License |
paul@33 | 18 | * along with this program; if not, write to the Free Software |
paul@42 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@42 | 20 | * Boston, MA 02110-1301, USA |
paul@33 | 21 | */ |
paul@33 | 22 | |
paul@33 | 23 | #include "sdram.h" |
paul@33 | 24 | #include "jzlcd.h" |
paul@62 | 25 | #include "cpu.h" |
paul@33 | 26 | #include "board.h" |
paul@33 | 27 | |
paul@48 | 28 | #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) |
paul@48 | 29 | #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) |
paul@48 | 30 | |
paul@33 | 31 | #define align2(n) (n)=((((n)+1)>>1)<<1) |
paul@33 | 32 | #define align4(n) (n)=((((n)+3)>>2)<<2) |
paul@33 | 33 | #define align8(n) (n)=((((n)+7)>>3)<<3) |
paul@33 | 34 | |
paul@33 | 35 | extern struct jzfb_info jzfb; |
paul@34 | 36 | extern vidinfo_t panel_info; |
paul@33 | 37 | |
paul@93 | 38 | static unsigned long lcd_get_size(vidinfo_t *vid) |
paul@33 | 39 | { |
paul@93 | 40 | int line_length = (vid->vl_col * NBITS(vid->vl_bpix)) / 8; |
paul@93 | 41 | return line_length * vid->vl_row; |
paul@33 | 42 | } |
paul@33 | 43 | |
paul@93 | 44 | static unsigned long lcd_get_total_size(vidinfo_t *vid) |
paul@48 | 45 | { |
paul@48 | 46 | /* Round up to nearest full page, or MMU section if defined */ |
paul@93 | 47 | return ALIGN(lcd_get_size(vid), PAGE_SIZE); |
paul@93 | 48 | } |
paul@48 | 49 | |
paul@93 | 50 | static unsigned long lcd_setmem(unsigned long addr) |
paul@93 | 51 | { |
paul@48 | 52 | /* Allocate pages for the frame buffer. */ |
paul@93 | 53 | return ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE) - lcd_get_total_size(&panel_info); |
paul@48 | 54 | } |
paul@48 | 55 | |
paul@95 | 56 | static int jz_lcd_init_mem(unsigned long lcdbase, vidinfo_t *vid); |
paul@33 | 57 | static void jz_lcd_desc_init(vidinfo_t *vid); |
paul@33 | 58 | static int jz_lcd_hw_init(vidinfo_t *vid); |
paul@33 | 59 | |
paul@95 | 60 | void lcd_ctrl_init(unsigned long *lcdbase) |
paul@33 | 61 | { |
paul@48 | 62 | /* Start from the top of memory and obtain a framebuffer region. */ |
paul@95 | 63 | *lcdbase = lcd_setmem(get_memory_size()); |
paul@48 | 64 | |
paul@48 | 65 | jz_lcd_init_mem(*lcdbase, &panel_info); |
paul@33 | 66 | jz_lcd_desc_init(&panel_info); |
paul@33 | 67 | jz_lcd_hw_init(&panel_info); |
paul@33 | 68 | } |
paul@33 | 69 | |
paul@33 | 70 | /* |
paul@93 | 71 | * Before enabling the LCD controller, LCD registers should be configured correctly. |
paul@33 | 72 | */ |
paul@93 | 73 | void lcd_enable(void) |
paul@33 | 74 | { |
paul@33 | 75 | REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ |
paul@33 | 76 | REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ |
paul@33 | 77 | } |
paul@33 | 78 | |
paul@93 | 79 | void lcd_disable(void) |
paul@33 | 80 | { |
paul@33 | 81 | REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ |
paul@33 | 82 | } |
paul@33 | 83 | |
paul@95 | 84 | static int jz_lcd_init_mem(unsigned long lcdbase, vidinfo_t *vid) |
paul@33 | 85 | { |
paul@33 | 86 | unsigned long palette_mem_size; |
paul@33 | 87 | struct jz_fb_info *fbi = &vid->jz_fb; |
paul@95 | 88 | unsigned long fb_size = lcd_get_size(vid); |
paul@33 | 89 | |
paul@95 | 90 | fbi->screen = lcdbase; |
paul@33 | 91 | fbi->palette_size = 256; |
paul@33 | 92 | palette_mem_size = fbi->palette_size * sizeof(u16); |
paul@33 | 93 | |
paul@33 | 94 | /* locate palette and descs at end of page following fb */ |
paul@95 | 95 | fbi->palette = lcdbase + fb_size + PAGE_SIZE - palette_mem_size; |
paul@33 | 96 | |
paul@33 | 97 | return 0; |
paul@33 | 98 | } |
paul@33 | 99 | |
paul@33 | 100 | static void jz_lcd_desc_init(vidinfo_t *vid) |
paul@33 | 101 | { |
paul@94 | 102 | struct jz_fb_dma_descriptor *descriptors; |
paul@33 | 103 | struct jz_fb_info * fbi; |
paul@95 | 104 | |
paul@33 | 105 | fbi = &vid->jz_fb; |
paul@96 | 106 | |
paul@96 | 107 | /* Allocate space for descriptors before the palette entries. */ |
paul@96 | 108 | |
paul@94 | 109 | descriptors = ((struct jz_fb_dma_descriptor *) fbi->palette) - 3; |
paul@94 | 110 | fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *) &descriptors[0]; |
paul@94 | 111 | fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *) &descriptors[1]; |
paul@94 | 112 | fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *) &descriptors[2]; |
paul@33 | 113 | |
paul@96 | 114 | /* Populate descriptors. */ |
paul@96 | 115 | |
paul@95 | 116 | fbi->dmadesc_fblow->fdadr = fbi->dmadesc_fblow; |
paul@95 | 117 | fbi->dmadesc_fblow->fsadr = fbi->screen + lcd_get_size(vid); |
paul@33 | 118 | fbi->dmadesc_fblow->fidr = 0; |
paul@93 | 119 | fbi->dmadesc_fblow->ldcmd = lcd_get_size(vid) / 4 ; |
paul@33 | 120 | |
paul@95 | 121 | fbi->fdadr1 = fbi->dmadesc_fblow; /* only used in dual-panel mode */ |
paul@33 | 122 | |
paul@95 | 123 | fbi->dmadesc_fbhigh->fsadr = fbi->screen; |
paul@33 | 124 | fbi->dmadesc_fbhigh->fidr = 0; |
paul@93 | 125 | fbi->dmadesc_fbhigh->ldcmd = lcd_get_size(vid) / 4; /* length in word */ |
paul@33 | 126 | |
paul@95 | 127 | fbi->dmadesc_palette->fsadr = fbi->palette; |
paul@33 | 128 | fbi->dmadesc_palette->fidr = 0; |
paul@33 | 129 | fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); |
paul@33 | 130 | |
paul@33 | 131 | if(NBITS(vid->vl_bpix) < 12) |
paul@33 | 132 | { |
paul@33 | 133 | /* assume any mode with <12 bpp is palette driven */ |
paul@95 | 134 | fbi->dmadesc_palette->fdadr = fbi->dmadesc_fbhigh; |
paul@95 | 135 | fbi->dmadesc_fbhigh->fdadr = fbi->dmadesc_palette; |
paul@33 | 136 | /* flips back and forth between pal and fbhigh */ |
paul@95 | 137 | fbi->fdadr0 = fbi->dmadesc_palette; |
paul@33 | 138 | } else { |
paul@33 | 139 | /* palette shouldn't be loaded in true-color mode */ |
paul@95 | 140 | fbi->dmadesc_fbhigh->fdadr = fbi->dmadesc_fbhigh; |
paul@95 | 141 | fbi->fdadr0 = fbi->dmadesc_fbhigh; /* no pal just fbhigh */ |
paul@33 | 142 | } |
paul@33 | 143 | |
paul@33 | 144 | flush_cache_all(); |
paul@33 | 145 | } |
paul@33 | 146 | |
paul@96 | 147 | static unsigned int jz_lcd_stn_init(unsigned int stnH) |
paul@96 | 148 | { |
paul@96 | 149 | unsigned int val = 0; |
paul@96 | 150 | |
paul@96 | 151 | switch (jzfb.bpp) { |
paul@96 | 152 | case 1: |
paul@96 | 153 | /* val |= LCD_CTRL_PEDN; */ |
paul@96 | 154 | case 2: |
paul@96 | 155 | val |= LCD_CTRL_FRC_2; |
paul@96 | 156 | break; |
paul@96 | 157 | case 4: |
paul@96 | 158 | val |= LCD_CTRL_FRC_4; |
paul@96 | 159 | break; |
paul@96 | 160 | case 8: |
paul@96 | 161 | default: |
paul@96 | 162 | val |= LCD_CTRL_FRC_16; |
paul@96 | 163 | break; |
paul@96 | 164 | } |
paul@96 | 165 | |
paul@96 | 166 | switch (jzfb.cfg & STN_DAT_PINMASK) { |
paul@96 | 167 | case STN_DAT_PIN1: |
paul@96 | 168 | /* Do not adjust the hori-param value. */ |
paul@96 | 169 | break; |
paul@96 | 170 | case STN_DAT_PIN2: |
paul@96 | 171 | align2(jzfb.hsw); |
paul@96 | 172 | align2(jzfb.elw); |
paul@96 | 173 | align2(jzfb.blw); |
paul@96 | 174 | break; |
paul@96 | 175 | case STN_DAT_PIN4: |
paul@96 | 176 | align4(jzfb.hsw); |
paul@96 | 177 | align4(jzfb.elw); |
paul@96 | 178 | align4(jzfb.blw); |
paul@96 | 179 | break; |
paul@96 | 180 | case STN_DAT_PIN8: |
paul@96 | 181 | align8(jzfb.hsw); |
paul@96 | 182 | align8(jzfb.elw); |
paul@96 | 183 | align8(jzfb.blw); |
paul@96 | 184 | break; |
paul@96 | 185 | } |
paul@96 | 186 | |
paul@96 | 187 | REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; |
paul@96 | 188 | REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); |
paul@96 | 189 | |
paul@96 | 190 | /* Screen setting */ |
paul@96 | 191 | REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); |
paul@96 | 192 | REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); |
paul@96 | 193 | REG_LCD_DAV = (0 << 16) | (stnH); |
paul@96 | 194 | |
paul@96 | 195 | /* AC BIAs signal */ |
paul@96 | 196 | REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); |
paul@96 | 197 | |
paul@96 | 198 | return val; |
paul@96 | 199 | } |
paul@96 | 200 | |
paul@96 | 201 | static void jz_lcd_tft_init() |
paul@96 | 202 | { |
paul@96 | 203 | REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; |
paul@96 | 204 | REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; |
paul@96 | 205 | REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); |
paul@96 | 206 | REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); |
paul@96 | 207 | REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ |
paul@96 | 208 | | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); |
paul@96 | 209 | } |
paul@96 | 210 | |
paul@96 | 211 | static int jz_lcd_hw_init(vidinfo_t *vid) |
paul@33 | 212 | { |
paul@33 | 213 | struct jz_fb_info *fbi = &vid->jz_fb; |
paul@33 | 214 | unsigned int val = 0; |
paul@33 | 215 | unsigned int pclk; |
paul@43 | 216 | #ifndef CONFIG_CPU_JZ4730 |
paul@33 | 217 | int pll_div; |
paul@43 | 218 | #endif |
paul@33 | 219 | |
paul@33 | 220 | /* Setting Control register */ |
paul@33 | 221 | switch (jzfb.bpp) { |
paul@33 | 222 | case 1: |
paul@33 | 223 | val |= LCD_CTRL_BPP_1; |
paul@33 | 224 | break; |
paul@33 | 225 | case 2: |
paul@33 | 226 | val |= LCD_CTRL_BPP_2; |
paul@33 | 227 | break; |
paul@33 | 228 | case 4: |
paul@33 | 229 | val |= LCD_CTRL_BPP_4; |
paul@33 | 230 | break; |
paul@33 | 231 | case 8: |
paul@33 | 232 | val |= LCD_CTRL_BPP_8; |
paul@33 | 233 | break; |
paul@33 | 234 | case 15: |
paul@33 | 235 | val |= LCD_CTRL_RGB555; |
paul@33 | 236 | case 16: |
paul@33 | 237 | val |= LCD_CTRL_BPP_16; |
paul@33 | 238 | break; |
paul@43 | 239 | #ifndef CONFIG_CPU_JZ4730 |
paul@33 | 240 | case 17 ... 32: |
paul@33 | 241 | val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ |
paul@33 | 242 | break; |
paul@43 | 243 | #endif |
paul@33 | 244 | default: |
paul@33 | 245 | /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ |
paul@33 | 246 | val |= LCD_CTRL_BPP_16; |
paul@33 | 247 | break; |
paul@33 | 248 | } |
paul@33 | 249 | |
paul@33 | 250 | switch (jzfb.cfg & MODE_MASK) { |
paul@33 | 251 | case MODE_STN_MONO_DUAL: |
paul@33 | 252 | case MODE_STN_COLOR_DUAL: |
paul@96 | 253 | val |= jz_lcd_stn_init(jzfb.h >> 1); |
paul@33 | 254 | break; |
paul@33 | 255 | |
paul@33 | 256 | case MODE_STN_MONO_SINGLE: |
paul@33 | 257 | case MODE_STN_COLOR_SINGLE: |
paul@96 | 258 | val |= jz_lcd_stn_init(jzfb.h); |
paul@33 | 259 | break; |
paul@33 | 260 | |
paul@33 | 261 | case MODE_TFT_GEN: |
paul@33 | 262 | case MODE_TFT_CASIO: |
paul@33 | 263 | case MODE_8BIT_SERIAL_TFT: |
paul@33 | 264 | case MODE_TFT_18BIT: |
paul@96 | 265 | jz_lcd_tft_init(); |
paul@33 | 266 | break; |
paul@33 | 267 | |
paul@33 | 268 | case MODE_TFT_SAMSUNG: |
paul@33 | 269 | { |
paul@33 | 270 | unsigned int total, tp_s, tp_e, ckv_s, ckv_e; |
paul@33 | 271 | unsigned int rev_s, rev_e, inv_s, inv_e; |
paul@33 | 272 | |
paul@96 | 273 | jz_lcd_tft_init(); |
paul@96 | 274 | |
paul@33 | 275 | pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * |
paul@33 | 276 | (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ |
paul@33 | 277 | |
paul@33 | 278 | total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; |
paul@33 | 279 | tp_s = jzfb.blw + jzfb.w + 1; |
paul@33 | 280 | tp_e = tp_s + 1; |
paul@33 | 281 | /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ |
paul@33 | 282 | ckv_s = tp_s - pclk/(1000000000/4100); |
paul@33 | 283 | ckv_e = tp_s + total; |
paul@33 | 284 | rev_s = tp_s - 11; /* -11.5 clk */ |
paul@33 | 285 | rev_e = rev_s + total; |
paul@33 | 286 | inv_s = tp_s; |
paul@33 | 287 | inv_e = inv_s + total; |
paul@33 | 288 | REG_LCD_CLS = (tp_s << 16) | tp_e; |
paul@33 | 289 | REG_LCD_PS = (ckv_s << 16) | ckv_e; |
paul@33 | 290 | REG_LCD_SPL = (rev_s << 16) | rev_e; |
paul@33 | 291 | REG_LCD_REV = (inv_s << 16) | inv_e; |
paul@33 | 292 | jzfb.cfg |= STFT_REVHI | STFT_SPLHI; |
paul@33 | 293 | break; |
paul@33 | 294 | } |
paul@96 | 295 | |
paul@33 | 296 | case MODE_TFT_SHARP: |
paul@33 | 297 | { |
paul@33 | 298 | unsigned int total, cls_s, cls_e, ps_s, ps_e; |
paul@33 | 299 | unsigned int spl_s, spl_e, rev_s, rev_e; |
paul@96 | 300 | |
paul@96 | 301 | jz_lcd_tft_init(); |
paul@96 | 302 | |
paul@33 | 303 | total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; |
paul@33 | 304 | spl_s = 1; |
paul@33 | 305 | spl_e = spl_s + 1; |
paul@33 | 306 | cls_s = 0; |
paul@33 | 307 | cls_e = total - 60; /* > 4us (pclk = 80ns) */ |
paul@33 | 308 | ps_s = cls_s; |
paul@33 | 309 | ps_e = cls_e; |
paul@33 | 310 | rev_s = total - 40; /* > 3us (pclk = 80ns) */ |
paul@33 | 311 | rev_e = rev_s + total; |
paul@33 | 312 | jzfb.cfg |= STFT_PSHI; |
paul@33 | 313 | REG_LCD_SPL = (spl_s << 16) | spl_e; |
paul@33 | 314 | REG_LCD_CLS = (cls_s << 16) | cls_e; |
paul@33 | 315 | REG_LCD_PS = (ps_s << 16) | ps_e; |
paul@33 | 316 | REG_LCD_REV = (rev_s << 16) | rev_e; |
paul@33 | 317 | break; |
paul@33 | 318 | } |
paul@96 | 319 | |
paul@96 | 320 | default: |
paul@33 | 321 | break; |
paul@33 | 322 | } |
paul@33 | 323 | |
paul@33 | 324 | /* Configure the LCD panel */ |
paul@96 | 325 | |
paul@96 | 326 | val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ |
paul@96 | 327 | val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ |
paul@96 | 328 | REG_LCD_CTRL = val; |
paul@33 | 329 | REG_LCD_CFG = jzfb.cfg; |
paul@33 | 330 | |
paul@33 | 331 | /* Timing setting */ |
paul@33 | 332 | __cpm_stop_lcd(); |
paul@33 | 333 | |
paul@33 | 334 | val = jzfb.fclk; /* frame clk */ |
paul@33 | 335 | if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { |
paul@33 | 336 | pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * |
paul@33 | 337 | (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ |
paul@33 | 338 | } else { |
paul@33 | 339 | /* serial mode: Hsync period = 3*Width_Pixel */ |
paul@33 | 340 | pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * |
paul@33 | 341 | (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ |
paul@33 | 342 | } |
paul@33 | 343 | |
paul@33 | 344 | if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || |
paul@33 | 345 | ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) |
paul@33 | 346 | pclk = (pclk * 3); |
paul@33 | 347 | |
paul@33 | 348 | if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || |
paul@33 | 349 | ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || |
paul@33 | 350 | ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || |
paul@33 | 351 | ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) |
paul@33 | 352 | pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); |
paul@33 | 353 | |
paul@33 | 354 | if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || |
paul@33 | 355 | ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) |
paul@33 | 356 | pclk >>= 1; |
paul@33 | 357 | |
paul@33 | 358 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 359 | val = __cpm_get_pllout() / pclk; |
paul@33 | 360 | REG_CPM_CFCR2 = val - 1; |
paul@33 | 361 | val = pclk * 4 ; |
paul@33 | 362 | if ( val > 150000000 ) { |
paul@33 | 363 | val = 150000000; |
paul@33 | 364 | } |
paul@33 | 365 | val = __cpm_get_pllout() / val; |
paul@33 | 366 | val--; |
paul@33 | 367 | if ( val > 0xF ) |
paul@33 | 368 | val = 0xF; |
paul@33 | 369 | #else |
paul@33 | 370 | pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ |
paul@33 | 371 | pll_div = pll_div ? 1 : 2 ; |
paul@33 | 372 | val = ( __cpm_get_pllout()/pll_div ) / pclk; |
paul@33 | 373 | val--; |
paul@33 | 374 | if ( val > 0x1ff ) { |
paul@33 | 375 | val = 0x1ff; |
paul@33 | 376 | } |
paul@33 | 377 | __cpm_set_pixdiv(val); |
paul@33 | 378 | |
paul@33 | 379 | val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ |
paul@33 | 380 | if ( val > 150000000 ) { |
paul@33 | 381 | val = 150000000; |
paul@33 | 382 | } |
paul@33 | 383 | val = ( __cpm_get_pllout()/pll_div ) / val; |
paul@33 | 384 | val--; |
paul@33 | 385 | if ( val > 0x1f ) { |
paul@33 | 386 | val = 0x1f; |
paul@33 | 387 | } |
paul@74 | 388 | #endif |
paul@33 | 389 | __cpm_set_ldiv( val ); |
paul@33 | 390 | REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ |
paul@74 | 391 | |
paul@33 | 392 | __cpm_start_lcd(); |
paul@33 | 393 | udelay(1000); |
paul@33 | 394 | |
paul@96 | 395 | /* Configure DMA. */ |
paul@96 | 396 | |
paul@95 | 397 | REG_LCD_DA0 = (unsigned long) fbi->fdadr0; /* frame descriptor */ |
paul@33 | 398 | |
paul@33 | 399 | if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || |
paul@33 | 400 | ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) |
paul@95 | 401 | REG_LCD_DA1 = (unsigned long) fbi->fdadr1; /* frame descriptor */ |
paul@33 | 402 | |
paul@33 | 403 | return 0; |
paul@33 | 404 | } |
paul@33 | 405 | |
paul@33 | 406 | void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) |
paul@33 | 407 | { |
paul@33 | 408 | } |
paul@33 | 409 | |
paul@33 | 410 | void lcd_initcolregs (void) |
paul@33 | 411 | { |
paul@33 | 412 | } |