paul@9 | 1 | /* |
paul@9 | 2 | * JzRISC lcd controller |
paul@9 | 3 | * |
paul@9 | 4 | * Xiangfu Liu <xiangfu@sharism.cc> |
paul@9 | 5 | * |
paul@9 | 6 | * This program is free software; you can redistribute it and/or |
paul@9 | 7 | * modify it under the terms of the GNU General Public License as |
paul@9 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@9 | 9 | * the License, or (at your option) any later version. |
paul@9 | 10 | * |
paul@9 | 11 | * This program is distributed in the hope that it will be useful, |
paul@9 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@9 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@9 | 14 | * GNU General Public License for more details. |
paul@9 | 15 | * |
paul@9 | 16 | * You should have received a copy of the GNU General Public License |
paul@9 | 17 | * along with this program; if not, write to the Free Software |
paul@9 | 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
paul@9 | 19 | * MA 02111-1307 USA |
paul@9 | 20 | */ |
paul@9 | 21 | |
paul@9 | 22 | #ifndef __QI_LB60_GPM940B0_H__ |
paul@9 | 23 | #define __QI_LB60_GPM940B0_H__ |
paul@9 | 24 | |
paul@12 | 25 | #include "nanonote.h" |
paul@15 | 26 | #include "jz4740_lcd.h" |
paul@21 | 27 | #include "jz4740.h" |
paul@15 | 28 | |
paul@15 | 29 | unsigned long lcd_get_size(void); |
paul@15 | 30 | void lcd_ctrl_init(void *lcdbase); |
paul@15 | 31 | void lcd_enable(void); |
paul@15 | 32 | void lcd_disable(void); |
paul@12 | 33 | |
paul@9 | 34 | struct lcd_desc{ |
paul@9 | 35 | unsigned int next_desc; /* LCDDAx */ |
paul@9 | 36 | unsigned int databuf; /* LCDSAx */ |
paul@9 | 37 | unsigned int frame_id; /* LCDFIDx */ |
paul@9 | 38 | unsigned int cmd; /* LCDCMDx */ |
paul@9 | 39 | }; |
paul@9 | 40 | |
paul@9 | 41 | #define MODE_MASK 0x0f |
paul@9 | 42 | #define MODE_TFT_GEN 0x00 |
paul@9 | 43 | #define MODE_TFT_SHARP 0x01 |
paul@9 | 44 | #define MODE_TFT_CASIO 0x02 |
paul@9 | 45 | #define MODE_TFT_SAMSUNG 0x03 |
paul@9 | 46 | #define MODE_CCIR656_NONINT 0x04 |
paul@9 | 47 | #define MODE_CCIR656_INT 0x05 |
paul@9 | 48 | #define MODE_STN_COLOR_SINGLE 0x08 |
paul@9 | 49 | #define MODE_STN_MONO_SINGLE 0x09 |
paul@9 | 50 | #define MODE_STN_COLOR_DUAL 0x0a |
paul@9 | 51 | #define MODE_STN_MONO_DUAL 0x0b |
paul@9 | 52 | #define MODE_8BIT_SERIAL_TFT 0x0c |
paul@9 | 53 | |
paul@9 | 54 | #define MODE_TFT_18BIT (1<<7) |
paul@9 | 55 | |
paul@9 | 56 | #define STN_DAT_PIN1 (0x00 << 4) |
paul@9 | 57 | #define STN_DAT_PIN2 (0x01 << 4) |
paul@9 | 58 | #define STN_DAT_PIN4 (0x02 << 4) |
paul@9 | 59 | #define STN_DAT_PIN8 (0x03 << 4) |
paul@9 | 60 | #define STN_DAT_PINMASK STN_DAT_PIN8 |
paul@9 | 61 | |
paul@9 | 62 | #define STFT_PSHI (1 << 15) |
paul@9 | 63 | #define STFT_CLSHI (1 << 14) |
paul@9 | 64 | #define STFT_SPLHI (1 << 13) |
paul@9 | 65 | #define STFT_REVHI (1 << 12) |
paul@9 | 66 | |
paul@9 | 67 | #define SYNC_MASTER (0 << 16) |
paul@9 | 68 | #define SYNC_SLAVE (1 << 16) |
paul@9 | 69 | |
paul@9 | 70 | #define DE_P (0 << 9) |
paul@9 | 71 | #define DE_N (1 << 9) |
paul@9 | 72 | |
paul@9 | 73 | #define PCLK_P (0 << 10) |
paul@9 | 74 | #define PCLK_N (1 << 10) |
paul@9 | 75 | |
paul@9 | 76 | #define HSYNC_P (0 << 11) |
paul@9 | 77 | #define HSYNC_N (1 << 11) |
paul@9 | 78 | |
paul@9 | 79 | #define VSYNC_P (0 << 8) |
paul@9 | 80 | #define VSYNC_N (1 << 8) |
paul@9 | 81 | |
paul@9 | 82 | #define DATA_NORMAL (0 << 17) |
paul@9 | 83 | #define DATA_INVERSE (1 << 17) |
paul@9 | 84 | |
paul@9 | 85 | |
paul@9 | 86 | /* Jz LCDFB supported I/O controls. */ |
paul@9 | 87 | #define FBIOSETBACKLIGHT 0x4688 |
paul@9 | 88 | #define FBIODISPON 0x4689 |
paul@9 | 89 | #define FBIODISPOFF 0x468a |
paul@9 | 90 | #define FBIORESET 0x468b |
paul@9 | 91 | #define FBIOPRINT_REG 0x468c |
paul@9 | 92 | |
paul@9 | 93 | /* |
paul@9 | 94 | * LCD panel specific definition |
paul@9 | 95 | */ |
paul@9 | 96 | #define MODE (0xc9) /* 8bit serial RGB */ |
paul@9 | 97 | |
paul@9 | 98 | #define __spi_write_reg1(reg, val) \ |
paul@9 | 99 | do { \ |
paul@9 | 100 | unsigned char no; \ |
paul@9 | 101 | unsigned short value; \ |
paul@9 | 102 | unsigned char a=reg; \ |
paul@9 | 103 | unsigned char b=val; \ |
paul@9 | 104 | __gpio_set_pin(SPEN); \ |
paul@9 | 105 | __gpio_set_pin(SPCK); \ |
paul@9 | 106 | __gpio_clear_pin(SPDA); \ |
paul@9 | 107 | __gpio_clear_pin(SPEN); \ |
paul@9 | 108 | value=((a<<8)|(b&0xFF)); \ |
paul@9 | 109 | for(no=0;no<16;no++) \ |
paul@9 | 110 | { \ |
paul@9 | 111 | __gpio_clear_pin(SPCK); \ |
paul@9 | 112 | if((value&0x8000)==0x8000) \ |
paul@9 | 113 | __gpio_set_pin(SPDA); \ |
paul@9 | 114 | else \ |
paul@9 | 115 | __gpio_clear_pin(SPDA); \ |
paul@9 | 116 | __gpio_set_pin(SPCK); \ |
paul@9 | 117 | value=(value<<1); \ |
paul@9 | 118 | } \ |
paul@9 | 119 | __gpio_set_pin(SPEN); \ |
paul@9 | 120 | } while (0) |
paul@9 | 121 | |
paul@9 | 122 | #define __lcd_display_pin_init() \ |
paul@9 | 123 | do { \ |
paul@9 | 124 | __cpm_start_tcu(); \ |
paul@21 | 125 | __gpio_as_output(SPEN); \ |
paul@21 | 126 | __gpio_as_output(SPCK); \ |
paul@21 | 127 | __gpio_as_output(SPDA); \ |
paul@9 | 128 | } while (0) |
paul@9 | 129 | |
paul@9 | 130 | #define __lcd_display_on() \ |
paul@9 | 131 | do { \ |
paul@9 | 132 | __spi_write_reg1(0x05, 0x1e); \ |
paul@9 | 133 | __spi_write_reg1(0x05, 0x5e); \ |
paul@9 | 134 | __spi_write_reg1(0x07, 0x8d); \ |
paul@9 | 135 | __spi_write_reg1(0x13, 0x01); \ |
paul@9 | 136 | __spi_write_reg1(0x05, 0x5f); \ |
paul@9 | 137 | } while (0) |
paul@9 | 138 | |
paul@9 | 139 | #define __lcd_display_off() \ |
paul@9 | 140 | do { \ |
paul@9 | 141 | __spi_write_reg1(0x05, 0x5e); \ |
paul@9 | 142 | } while (0) |
paul@9 | 143 | |
paul@9 | 144 | #endif /* __QI_LB60_GPM940B0_H__ */ |