paul@33 | 1 | /* |
paul@63 | 2 | * Common SDRAM configuration. |
paul@33 | 3 | * |
paul@67 | 4 | * Copyright (C) 1996, 1997 by Ralf Baechle |
paul@67 | 5 | * |
paul@33 | 6 | * Copyright (C) 2009 Qi Hardware Inc. |
paul@33 | 7 | * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> |
paul@67 | 8 | * |
paul@95 | 9 | * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> |
paul@33 | 10 | * |
paul@63 | 11 | * This program is free software: you can redistribute it and/or modify |
paul@63 | 12 | * it under the terms of the GNU General Public License as published by |
paul@63 | 13 | * the Free Software Foundation, either version 3 of the License, or |
paul@63 | 14 | * (at your option) any later version. |
paul@33 | 15 | * |
paul@33 | 16 | * This program is distributed in the hope that it will be useful, |
paul@33 | 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@33 | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@33 | 19 | * GNU General Public License for more details. |
paul@33 | 20 | * |
paul@33 | 21 | * You should have received a copy of the GNU General Public License |
paul@63 | 22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@33 | 23 | */ |
paul@33 | 24 | |
paul@33 | 25 | #ifndef __SDRAM_H__ |
paul@33 | 26 | #define __SDRAM_H__ |
paul@33 | 27 | |
paul@33 | 28 | /* |
paul@33 | 29 | * RAM configuration |
paul@33 | 30 | */ |
paul@33 | 31 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
paul@33 | 32 | |
paul@33 | 33 | /* |
paul@33 | 34 | * SDRAM configuration (timings in ns) |
paul@33 | 35 | */ |
paul@56 | 36 | #ifdef CONFIG_CPU_JZ4730_MINIPC |
paul@56 | 37 | #define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ |
paul@56 | 38 | #else |
paul@56 | 39 | #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ |
paul@56 | 40 | #endif |
paul@56 | 41 | |
paul@56 | 42 | #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
paul@56 | 43 | #define SDRAM_ROW 13 /* Row address: 11 to 13 */ |
paul@56 | 44 | #define SDRAM_COL 9 /* Column address: 8 to 12 */ |
paul@56 | 45 | #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ |
paul@56 | 46 | #define SDRAM_TRAS 45 /* RAS# Active Time */ |
paul@56 | 47 | #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ |
paul@56 | 48 | #define SDRAM_TPC 20 /* RAS# Precharge Time */ |
paul@56 | 49 | #define SDRAM_TRWL 7 /* Write Latency Time */ |
paul@56 | 50 | |
paul@56 | 51 | #ifdef CONFIG_CPU_JZ4730_MINIPC |
paul@56 | 52 | #define SDRAM_TREF 7812 /* Refresh period: 8192 cycles/64ms */ |
paul@56 | 53 | #else |
paul@56 | 54 | #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ |
paul@56 | 55 | #endif |
paul@33 | 56 | |
paul@33 | 57 | #define SDRAM_ROW0 11 /* Row address minimum */ |
paul@33 | 58 | #define SDRAM_COL0 8 /* Column address minimum */ |
paul@33 | 59 | #define SDRAM_BANK40 0 /* Bank minimum */ |
paul@33 | 60 | |
paul@33 | 61 | /* |
paul@33 | 62 | * Cache configuration |
paul@33 | 63 | */ |
paul@33 | 64 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
paul@33 | 65 | #define CONFIG_SYS_ICACHE_SIZE 16384 |
paul@33 | 66 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
paul@33 | 67 | |
paul@67 | 68 | #define Index_Invalidate_I 0x00 |
paul@67 | 69 | #define Index_Writeback_Inv_D 0x01 |
paul@67 | 70 | #define Index_Store_Tag_I 0x08 |
paul@67 | 71 | #define Index_Store_Tag_D 0x09 |
paul@67 | 72 | #define Hit_Writeback_Inv_D 0x15 |
paul@67 | 73 | |
paul@67 | 74 | #define CONFIG_CM_UNCACHED 2 |
paul@67 | 75 | #define CONFIG_CM_CACHABLE_NONCOHERENT 3 |
paul@67 | 76 | |
paul@33 | 77 | /* |
paul@33 | 78 | * Memory configuration |
paul@33 | 79 | */ |
paul@33 | 80 | #define KSEG0 0x80000000 |
paul@33 | 81 | #define PAGE_SIZE 4096 |
paul@33 | 82 | |
paul@33 | 83 | #endif /* __SDRAM_H__ */ |