1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/stage2/cpu.c Sun Jun 14 21:17:08 2015 +0200
1.3 @@ -0,0 +1,80 @@
1.4 +/*
1.5 + * CPU-specific routines from U-Boot.
1.6 + * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
1.7 + * See: u-boot/arch/mips/include/asm/cacheops.h
1.8 + *
1.9 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
1.10 + *
1.11 + * This program is free software; you can redistribute it and/or
1.12 + * modify it under the terms of the GNU General Public License as
1.13 + * published by the Free Software Foundation; either version 2 of
1.14 + * the License, or (at your option) any later version.
1.15 + *
1.16 + * This program is distributed in the hope that it will be useful,
1.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.19 + * GNU General Public License for more details.
1.20 + *
1.21 + * You should have received a copy of the GNU General Public License
1.22 + * along with this program; if not, write to the Free Software
1.23 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.24 + * Boston, MA 02110-1301, USA
1.25 + */
1.26 +
1.27 +#include "xburst_types.h"
1.28 +#include "sdram.h"
1.29 +
1.30 +#define Index_Store_Tag_I 0x08
1.31 +#define Index_Writeback_Inv_D 0x15
1.32 +
1.33 +void flush_icache_all(void)
1.34 +{
1.35 + u32 addr, t = 0;
1.36 +
1.37 + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
1.38 + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
1.39 +
1.40 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
1.41 + addr += CONFIG_SYS_CACHELINE_SIZE) {
1.42 + asm volatile (
1.43 + ".set mips3\n\t"
1.44 + " cache %0, 0(%1)\n\t"
1.45 + ".set mips2\n\t"
1.46 + :
1.47 + : "I" (Index_Store_Tag_I), "r"(addr));
1.48 + }
1.49 +
1.50 + /* invalicate btb */
1.51 + asm volatile (
1.52 + ".set mips32\n\t"
1.53 + "mfc0 %0, $16, 7\n\t"
1.54 + "nop\n\t"
1.55 + "ori %0,2\n\t"
1.56 + "mtc0 %0, $16, 7\n\t"
1.57 + ".set mips2\n\t"
1.58 + :
1.59 + : "r" (t));
1.60 +}
1.61 +
1.62 +void flush_dcache_all(void)
1.63 +{
1.64 + u32 addr;
1.65 +
1.66 + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
1.67 + addr += CONFIG_SYS_CACHELINE_SIZE) {
1.68 + asm volatile (
1.69 + ".set mips3\n\t"
1.70 + " cache %0, 0(%1)\n\t"
1.71 + ".set mips2\n\t"
1.72 + :
1.73 + : "I" (Index_Writeback_Inv_D), "r"(addr));
1.74 + }
1.75 +
1.76 + asm volatile ("sync");
1.77 +}
1.78 +
1.79 +void flush_cache_all(void)
1.80 +{
1.81 + flush_dcache_all();
1.82 + flush_icache_all();
1.83 +}