1.1 --- a/stage1/board-nanonote.c Mon Jun 08 18:10:10 2015 +0200
1.2 +++ b/stage1/board-nanonote.c Mon Jun 08 18:47:40 2015 +0200
1.3 @@ -21,7 +21,6 @@
1.4 */
1.5
1.6 #include "jz4740.h"
1.7 -#include "configs.h"
1.8 #include "nanonote.h"
1.9 #include "usb_boot_defines.h"
1.10
1.11 @@ -29,26 +28,26 @@
1.12 /etc/xburst-tools/usbboot.cfg. */
1.13
1.14 struct fw_args *fw_args;
1.15 -volatile u32 CPU_ID;
1.16 -volatile u8 SDRAM_BW16;
1.17 -volatile u8 SDRAM_BANK4;
1.18 -volatile u8 SDRAM_ROW;
1.19 -volatile u8 SDRAM_COL;
1.20 -volatile u8 CONFIG_MOBILE_SDRAM;
1.21 -volatile u8 IS_SHARE;
1.22 +volatile u32 FW_CPU_ID;
1.23 +volatile u8 FW_SDRAM_BW16;
1.24 +volatile u8 FW_SDRAM_BANK4;
1.25 +volatile u8 FW_SDRAM_ROW;
1.26 +volatile u8 FW_SDRAM_COL;
1.27 +volatile u8 FW_CONFIG_MOBILE_SDRAM;
1.28 +volatile u8 FW_IS_SHARE;
1.29
1.30 void load_args(void)
1.31 {
1.32 /* Get the fw args from memory. See head1.S for the memory layout. */
1.33
1.34 fw_args = (struct fw_args *)0x80002008;
1.35 - CPU_ID = fw_args->cpu_id ;
1.36 - SDRAM_BW16 = fw_args->bus_width;
1.37 - SDRAM_BANK4 = fw_args->bank_num;
1.38 - SDRAM_ROW = fw_args->row_addr;
1.39 - SDRAM_COL = fw_args->col_addr;
1.40 - CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
1.41 - IS_SHARE = fw_args->is_busshare;
1.42 + FW_CPU_ID = fw_args->cpu_id ;
1.43 + FW_SDRAM_BW16 = fw_args->bus_width;
1.44 + FW_SDRAM_BANK4 = fw_args->bank_num;
1.45 + FW_SDRAM_ROW = fw_args->row_addr;
1.46 + FW_SDRAM_COL = fw_args->col_addr;
1.47 + FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
1.48 + FW_IS_SHARE = fw_args->is_busshare;
1.49 }
1.50
1.51 /* Initialisation functions. */
1.52 @@ -140,15 +139,15 @@
1.53 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
1.54 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
1.55 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
1.56 - (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.57 + (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.58 EMC_DMCR_EPIN |
1.59 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
1.60
1.61 /* Basic DMCR value */
1.62 - dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
1.63 - ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
1.64 - (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
1.65 - (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.66 + dmcr = ((FW_SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
1.67 + ((FW_SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
1.68 + (FW_SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
1.69 + (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.70 EMC_DMCR_EPIN |
1.71 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
1.72