1.1 --- a/stage2/cpu.c Tue Jun 23 23:04:17 2015 +0200
1.2 +++ b/stage2/cpu.c Tue Jun 23 23:05:00 2015 +0200
1.3 @@ -24,9 +24,6 @@
1.4 #include "xburst_types.h"
1.5 #include "sdram.h"
1.6
1.7 -#define Index_Store_Tag_I 0x08
1.8 -#define Index_Writeback_Inv_D 0x15
1.9 -
1.10 void flush_icache_all(void)
1.11 {
1.12 u32 addr, t = 0;
1.13 @@ -78,3 +75,14 @@
1.14 flush_dcache_all();
1.15 flush_icache_all();
1.16 }
1.17 +
1.18 +void enable_interrupts(void)
1.19 +{
1.20 + asm volatile(
1.21 + "mfc0 $t3, $12\n" /* CP0_STATUS */
1.22 + "nop\n"
1.23 + "li $t4, 0x00000001\n" /* IE = enable interrupts */
1.24 + "or $t3, $t3, $t4\n"
1.25 + "mtc0 $t3, $12\n"
1.26 + "nop\n");
1.27 +}