1.1 --- a/stage2/jzlcd.c Sat Jul 08 23:02:30 2017 +0200
1.2 +++ b/stage2/jzlcd.c Sun Jul 09 00:36:42 2017 +0200
1.3 @@ -25,11 +25,44 @@
1.4 #include "cpu.h"
1.5 #include "board.h"
1.6
1.7 -#define align2(n) (n)=((((n)+1)>>1)<<1)
1.8 -#define align4(n) (n)=((((n)+3)>>2)<<2)
1.9 -#define align8(n) (n)=((((n)+7)>>3)<<3)
1.10 +extern vidinfo_t panel_info;
1.11 +
1.12 +/* Useful alignment operations. */
1.13 +
1.14 +static inline void align2(uint32_t *n)
1.15 +{
1.16 + *n = (((*n)+1)>>1)<<1;
1.17 +}
1.18 +
1.19 +static inline void align4(uint32_t *n)
1.20 +{
1.21 + *n = (((*n)+3)>>2)<<2;
1.22 +}
1.23 +
1.24 +static inline void align8(uint32_t *n)
1.25 +{
1.26 + *n = (((*n)+7)>>3)<<3;
1.27 +}
1.28
1.29 -extern vidinfo_t panel_info;
1.30 +
1.31 +
1.32 +/* Register operations. */
1.33 +
1.34 +static inline uint32_t lcd_ctrl_get(vidinfo_t *vid, uint32_t reg)
1.35 +{
1.36 + return REG32(vid->lcd + reg);
1.37 +}
1.38 +
1.39 +static inline void lcd_ctrl_set(vidinfo_t *vid, uint32_t reg, uint32_t value)
1.40 +{
1.41 + REG32(vid->lcd + reg) = value;
1.42 +}
1.43 +
1.44 +
1.45 +
1.46 +/* Configuration operations. */
1.47 +
1.48 +/* Return the number of panels available. */
1.49
1.50 static uint16_t lcd_get_panels(vidinfo_t *vid)
1.51 {
1.52 @@ -38,6 +71,42 @@
1.53 ((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ? 2 : 1;
1.54 }
1.55
1.56 +/* Calculate and return the pixel clock frequency. */
1.57 +
1.58 +static uint32_t jz_lcd_get_pixel_clock(vidinfo_t *vid)
1.59 +{
1.60 + struct jzfb_info *jzfb = vid->jz_fb;
1.61 + uint32_t pclk, width_cycles, mode = jzfb->cfg & MODE_MASK;
1.62 +
1.63 + /*
1.64 + Serial mode: 3 pixel clock cycles per pixel (one per channel).
1.65 + Parallel mode: 1 pixel clock cycle per pixel.
1.66 + */
1.67 +
1.68 + if (mode == MODE_8BIT_SERIAL_TFT)
1.69 + width_cycles = jzfb->w * 3;
1.70 + else
1.71 + width_cycles = jzfb->w;
1.72 +
1.73 + /* Derive pixel clock from frame clock. */
1.74 +
1.75 + pclk = jzfb->fclk *
1.76 + (width_cycles + jzfb->hsw + jzfb->elw + jzfb->blw) *
1.77 + (jzfb->h + jzfb->vsw + jzfb->efw + jzfb->bfw);
1.78 +
1.79 + if ((mode == MODE_STN_COLOR_SINGLE) || (mode == MODE_STN_COLOR_DUAL))
1.80 + pclk = (pclk * 3);
1.81 +
1.82 + if ((mode == MODE_STN_COLOR_SINGLE) || (mode == MODE_STN_COLOR_DUAL) ||
1.83 + (mode == MODE_STN_MONO_SINGLE) || (mode == MODE_STN_MONO_DUAL))
1.84 + pclk = pclk >> ((jzfb->cfg & STN_DAT_PINMASK) >> 4);
1.85 +
1.86 + if ((mode == MODE_STN_COLOR_DUAL) || (mode == MODE_STN_MONO_DUAL))
1.87 + pclk >>= 1;
1.88 +
1.89 + return pclk;
1.90 +}
1.91 +
1.92
1.93
1.94 /* Functions returning region sizes. */
1.95 @@ -178,51 +247,56 @@
1.96 uint32_t val = 0;
1.97
1.98 switch (jzfb->bpp) {
1.99 - case 1:
1.100 + case 1:
1.101 /* val |= LCD_CTRL_PEDN; */
1.102 - case 2:
1.103 + case 2:
1.104 val |= LCD_CTRL_FRC_2;
1.105 break;
1.106 - case 4:
1.107 +
1.108 + case 4:
1.109 val |= LCD_CTRL_FRC_4;
1.110 break;
1.111 - case 8:
1.112 - default:
1.113 +
1.114 + case 8:
1.115 + default:
1.116 val |= LCD_CTRL_FRC_16;
1.117 break;
1.118 }
1.119
1.120 switch (jzfb->cfg & STN_DAT_PINMASK) {
1.121 - case STN_DAT_PIN1:
1.122 + case STN_DAT_PIN1:
1.123 /* Do not adjust the hori-param value. */
1.124 break;
1.125 - case STN_DAT_PIN2:
1.126 - align2(jzfb->hsw);
1.127 - align2(jzfb->elw);
1.128 - align2(jzfb->blw);
1.129 +
1.130 + case STN_DAT_PIN2:
1.131 + align2(&jzfb->hsw);
1.132 + align2(&jzfb->elw);
1.133 + align2(&jzfb->blw);
1.134 break;
1.135 - case STN_DAT_PIN4:
1.136 - align4(jzfb->hsw);
1.137 - align4(jzfb->elw);
1.138 - align4(jzfb->blw);
1.139 +
1.140 + case STN_DAT_PIN4:
1.141 + align4(&jzfb->hsw);
1.142 + align4(&jzfb->elw);
1.143 + align4(&jzfb->blw);
1.144 break;
1.145 - case STN_DAT_PIN8:
1.146 - align8(jzfb->hsw);
1.147 - align8(jzfb->elw);
1.148 - align8(jzfb->blw);
1.149 +
1.150 + case STN_DAT_PIN8:
1.151 + align8(&jzfb->hsw);
1.152 + align8(&jzfb->elw);
1.153 + align8(&jzfb->blw);
1.154 break;
1.155 }
1.156
1.157 - REG_LCD_VSYNC = (0 << 16) | jzfb->vsw;
1.158 - REG_LCD_HSYNC = ((jzfb->blw+jzfb->w) << 16) | (jzfb->blw+jzfb->w+jzfb->hsw);
1.159 + lcd_ctrl_set(vid, LCD_VSYNC, jzfb->vsw);
1.160 + lcd_ctrl_set(vid, LCD_HSYNC, ((jzfb->blw+jzfb->w) << 16) | (jzfb->blw+jzfb->w+jzfb->hsw));
1.161
1.162 /* Screen setting */
1.163 - REG_LCD_VAT = ((jzfb->blw + jzfb->w + jzfb->hsw + jzfb->elw) << 16) | (stnH + jzfb->vsw + jzfb->bfw + jzfb->efw);
1.164 - REG_LCD_DAH = (jzfb->blw << 16) | (jzfb->blw + jzfb->w);
1.165 - REG_LCD_DAV = (0 << 16) | (stnH);
1.166 + lcd_ctrl_set(vid, LCD_VAT, ((jzfb->blw + jzfb->w + jzfb->hsw + jzfb->elw) << 16) | (stnH + jzfb->vsw + jzfb->bfw + jzfb->efw));
1.167 + lcd_ctrl_set(vid, LCD_DAH, (jzfb->blw << 16) | (jzfb->blw + jzfb->w));
1.168 + lcd_ctrl_set(vid, LCD_DAV, stnH);
1.169
1.170 /* AC BIAs signal */
1.171 - REG_LCD_PS = (0 << 16) | (stnH+jzfb->vsw+jzfb->efw+jzfb->bfw);
1.172 + lcd_ctrl_set(vid, LCD_PS, stnH+jzfb->vsw+jzfb->efw+jzfb->bfw);
1.173
1.174 return val;
1.175 }
1.176 @@ -230,17 +304,18 @@
1.177 static void jz_lcd_tft_init(vidinfo_t *vid)
1.178 {
1.179 struct jzfb_info *jzfb = vid->jz_fb;
1.180 - REG_LCD_VSYNC = (0 << 16) | jzfb->vsw;
1.181 - REG_LCD_HSYNC = (0 << 16) | jzfb->hsw;
1.182 - REG_LCD_DAV =((jzfb->vsw+jzfb->bfw) << 16) | (jzfb->vsw +jzfb->bfw+jzfb->h);
1.183 - REG_LCD_DAH = ((jzfb->hsw + jzfb->blw) << 16) | (jzfb->hsw + jzfb->blw + jzfb->w );
1.184 - REG_LCD_VAT = (((jzfb->blw + jzfb->w + jzfb->elw + jzfb->hsw)) << 16) \
1.185 - | (jzfb->vsw + jzfb->bfw + jzfb->h + jzfb->efw);
1.186 + lcd_ctrl_set(vid, LCD_VSYNC, jzfb->vsw);
1.187 + lcd_ctrl_set(vid, LCD_HSYNC, jzfb->hsw);
1.188 + lcd_ctrl_set(vid, LCD_DAV, ((jzfb->vsw+jzfb->bfw) << 16) | (jzfb->vsw +jzfb->bfw+jzfb->h));
1.189 + lcd_ctrl_set(vid, LCD_DAH, ((jzfb->hsw + jzfb->blw) << 16) | (jzfb->hsw + jzfb->blw + jzfb->w));
1.190 + lcd_ctrl_set(vid, LCD_VAT, (((jzfb->blw + jzfb->w + jzfb->elw + jzfb->hsw)) << 16) |
1.191 + (jzfb->vsw + jzfb->bfw + jzfb->h + jzfb->efw));
1.192 }
1.193
1.194 -static void jz_lcd_samsung_init(uint32_t pclk, vidinfo_t *vid)
1.195 +static void jz_lcd_samsung_init(vidinfo_t *vid)
1.196 {
1.197 struct jzfb_info *jzfb = vid->jz_fb;
1.198 + uint32_t pclk = jz_lcd_get_pixel_clock(vid);
1.199 uint32_t total, tp_s, tp_e, ckv_s, ckv_e;
1.200 uint32_t rev_s, rev_e, inv_s, inv_e;
1.201
1.202 @@ -256,10 +331,10 @@
1.203 rev_e = rev_s + total;
1.204 inv_s = tp_s;
1.205 inv_e = inv_s + total;
1.206 - REG_LCD_CLS = (tp_s << 16) | tp_e;
1.207 - REG_LCD_PS = (ckv_s << 16) | ckv_e;
1.208 - REG_LCD_SPL = (rev_s << 16) | rev_e;
1.209 - REG_LCD_REV = (inv_s << 16) | inv_e;
1.210 + lcd_ctrl_set(vid, LCD_CLS, (tp_s << 16) | tp_e);
1.211 + lcd_ctrl_set(vid, LCD_PS, (ckv_s << 16) | ckv_e);
1.212 + lcd_ctrl_set(vid, LCD_SPL, (rev_s << 16) | rev_e);
1.213 + lcd_ctrl_set(vid, LCD_REV, (inv_s << 16) | inv_e);
1.214 jzfb->cfg |= STFT_REVHI | STFT_SPLHI;
1.215 }
1.216
1.217 @@ -281,208 +356,15 @@
1.218 rev_s = total - 40; /* > 3us (pclk = 80ns) */
1.219 rev_e = rev_s + total;
1.220 jzfb->cfg |= STFT_PSHI;
1.221 - REG_LCD_SPL = (spl_s << 16) | spl_e;
1.222 - REG_LCD_CLS = (cls_s << 16) | cls_e;
1.223 - REG_LCD_PS = (ps_s << 16) | ps_e;
1.224 - REG_LCD_REV = (rev_s << 16) | rev_e;
1.225 -}
1.226 -
1.227 -static uint32_t jz_lcd_get_pixel_clock(vidinfo_t *vid)
1.228 -{
1.229 - struct jzfb_info *jzfb = vid->jz_fb;
1.230 - uint32_t pclk;
1.231 -
1.232 - /* Derive pixel clock from frame clock. */
1.233 -
1.234 - if ( (jzfb->cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
1.235 - pclk = jzfb->fclk * (jzfb->w + jzfb->hsw + jzfb->elw + jzfb->blw) *
1.236 - (jzfb->h + jzfb->vsw + jzfb->efw + jzfb->bfw);
1.237 - } else {
1.238 - /* serial mode: Hsync period = 3*Width_Pixel */
1.239 - pclk = jzfb->fclk * (jzfb->w*3 + jzfb->hsw + jzfb->elw + jzfb->blw) *
1.240 - (jzfb->h + jzfb->vsw + jzfb->efw + jzfb->bfw);
1.241 - }
1.242 -
1.243 - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
1.244 - ((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
1.245 - pclk = (pclk * 3);
1.246 -
1.247 - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
1.248 - ((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
1.249 - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
1.250 - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
1.251 - pclk = pclk >> ((jzfb->cfg & STN_DAT_PINMASK) >> 4);
1.252 -
1.253 - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
1.254 - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
1.255 - pclk >>= 1;
1.256 -
1.257 - return pclk;
1.258 -}
1.259 -
1.260 -static void jz_lcd_set_timing(uint32_t pclk)
1.261 -{
1.262 - uint32_t val;
1.263 -
1.264 -#ifdef CONFIG_CPU_JZ4730
1.265 - val = __cpm_get_pllout() / pclk;
1.266 - REG_CPM_CFCR2 = val - 1;
1.267 - val = pclk * 4 ;
1.268 - if ( val > 150000000 ) {
1.269 - val = 150000000;
1.270 - }
1.271 - val = __cpm_get_pllout() / val;
1.272 - val--;
1.273 - if ( val > 0xF )
1.274 - val = 0xF;
1.275 -#else
1.276 - int pll_div;
1.277 -
1.278 - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
1.279 - pll_div = pll_div ? 1 : 2 ;
1.280 - val = ( __cpm_get_pllout()/pll_div ) / pclk;
1.281 - val--;
1.282 - if ( val > 0x1ff ) {
1.283 - val = 0x1ff;
1.284 - }
1.285 - __cpm_set_pixdiv(val);
1.286 -
1.287 - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
1.288 - if ( val > 150000000 ) {
1.289 - val = 150000000;
1.290 - }
1.291 - val = ( __cpm_get_pllout()/pll_div ) / val;
1.292 - val--;
1.293 - if ( val > 0x1f ) {
1.294 - val = 0x1f;
1.295 - }
1.296 -#endif
1.297 - __cpm_set_ldiv( val );
1.298 - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
1.299 + lcd_ctrl_set(vid, LCD_SPL, (spl_s << 16) | spl_e);
1.300 + lcd_ctrl_set(vid, LCD_CLS, (cls_s << 16) | cls_e);
1.301 + lcd_ctrl_set(vid, LCD_PS, (ps_s << 16) | ps_e);
1.302 + lcd_ctrl_set(vid, LCD_REV, (rev_s << 16) | rev_e);
1.303 }
1.304
1.305 -static int jz_lcd_hw_init(vidinfo_t *vid)
1.306 -{
1.307 - struct jzfb_info *jzfb = vid->jz_fb;
1.308 - struct jz_mem_info *fbi = &vid->jz_mem;
1.309 - uint32_t val = 0;
1.310 - uint32_t pclk = jz_lcd_get_pixel_clock(vid);
1.311
1.312 - /* Setting Control register */
1.313 - switch (jzfb->bpp) {
1.314 - case 1:
1.315 - val |= LCD_CTRL_BPP_1;
1.316 - break;
1.317 - case 2:
1.318 - val |= LCD_CTRL_BPP_2;
1.319 - break;
1.320 - case 4:
1.321 - val |= LCD_CTRL_BPP_4;
1.322 - break;
1.323 - case 8:
1.324 - val |= LCD_CTRL_BPP_8;
1.325 - break;
1.326 - case 15:
1.327 - val |= LCD_CTRL_RGB555;
1.328 - case 16:
1.329 - val |= LCD_CTRL_BPP_16;
1.330 - break;
1.331 -#ifndef CONFIG_CPU_JZ4730
1.332 - case 17 ... 32:
1.333 - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
1.334 - break;
1.335 -#endif
1.336 - default:
1.337 - /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb->bpp); */
1.338 - val |= LCD_CTRL_BPP_16;
1.339 - break;
1.340 - }
1.341 -
1.342 - switch (jzfb->cfg & MODE_MASK) {
1.343 - case MODE_STN_MONO_DUAL:
1.344 - case MODE_STN_COLOR_DUAL:
1.345 - val |= jz_lcd_stn_init(jzfb->h >> 1, vid);
1.346 - break;
1.347 -
1.348 - case MODE_STN_MONO_SINGLE:
1.349 - case MODE_STN_COLOR_SINGLE:
1.350 - val |= jz_lcd_stn_init(jzfb->h, vid);
1.351 - break;
1.352 -
1.353 - case MODE_TFT_GEN:
1.354 - case MODE_TFT_CASIO:
1.355 - case MODE_8BIT_SERIAL_TFT:
1.356 - case MODE_TFT_18BIT:
1.357 - jz_lcd_tft_init(vid);
1.358 - break;
1.359 -
1.360 - case MODE_TFT_SAMSUNG:
1.361 - {
1.362 - jz_lcd_samsung_init(pclk, vid);
1.363 - break;
1.364 - }
1.365
1.366 - case MODE_TFT_SHARP:
1.367 - {
1.368 - jz_lcd_sharp_init(vid);
1.369 - break;
1.370 - }
1.371 -
1.372 - default:
1.373 - break;
1.374 - }
1.375 -
1.376 - /* Configure the LCD panel */
1.377 -
1.378 - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
1.379 - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
1.380 - REG_LCD_CTRL = val;
1.381 - REG_LCD_CFG = jzfb->cfg;
1.382 -
1.383 - /* Timing reset. */
1.384 -
1.385 - __cpm_stop_lcd();
1.386 - jz_lcd_set_timing(pclk);
1.387 - __cpm_start_lcd();
1.388 - udelay(1000);
1.389 -
1.390 - /* Configure DMA. */
1.391 -
1.392 - REG_LCD_DA0 = (uint32_t) fbi->fdadr0; /* frame descriptor */
1.393 -
1.394 - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
1.395 - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
1.396 - REG_LCD_DA1 = (uint32_t) fbi->fdadr1; /* frame descriptor */
1.397 -
1.398 - return 0;
1.399 -}
1.400 -
1.401 -/* Public operations. */
1.402 -
1.403 -void lcd_set_bpp(uint8_t bpp)
1.404 -{
1.405 - vidinfo_t *vid = &panel_info;
1.406 - struct jzfb_info *jzfb = vid->jz_fb;
1.407 - jzfb->bpp = bpp;
1.408 -}
1.409 -
1.410 -void lcd_enable()
1.411 -{
1.412 - /* Clear the disable bit and set the enable bit. */
1.413 -
1.414 - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
1.415 - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
1.416 -}
1.417 -
1.418 -void lcd_disable()
1.419 -{
1.420 - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
1.421 -}
1.422 -
1.423 -void lcd_quick_disable()
1.424 -{
1.425 - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.ENA, quick disable */
1.426 -}
1.427 +/* Palette initialisation. */
1.428
1.429 static inline uint16_t rgb8_to_rgb16(uint8_t rgb)
1.430 {
1.431 @@ -496,7 +378,7 @@
1.432
1.433 static void lcd_init_palette(vidinfo_t *vid)
1.434 {
1.435 - uint16_t *palette = (uint16_t *) lcd_get_palette(get_memory_size(), vid);
1.436 + uint16_t *palette = (uint16_t *) vid->jz_mem.palette;
1.437 uint16_t *end = (uint16_t *) palette + (1 << (vid->jz_fb->bpp));
1.438 uint8_t value = 0;
1.439
1.440 @@ -519,6 +401,189 @@
1.441 }
1.442 }
1.443
1.444 +
1.445 +
1.446 +static void jz_lcd_set_timing(vidinfo_t *vid)
1.447 +{
1.448 + uint32_t pclk = jz_lcd_get_pixel_clock(vid);
1.449 + uint32_t val;
1.450 +
1.451 +#ifdef CONFIG_CPU_JZ4730
1.452 + val = __cpm_get_pllout() / pclk;
1.453 + lcd_ctrl_set(vid, CPM_CFCR2, val - 1);
1.454 + val = pclk * 4 ;
1.455 + if ( val > 150000000 ) {
1.456 + val = 150000000;
1.457 + }
1.458 + val = __cpm_get_pllout() / val;
1.459 + val--;
1.460 + if ( val > 0xF )
1.461 + val = 0xF;
1.462 +#else
1.463 + int pll_div;
1.464 +
1.465 + pll_div = lcd_ctrl_get(vid, CPM_CPCCR) & lcd_ctrl_get(vid, CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
1.466 + pll_div = pll_div ? 1 : 2 ;
1.467 + val = ( __cpm_get_pllout()/pll_div ) / pclk;
1.468 + val--;
1.469 + if ( val > 0x1ff ) {
1.470 + val = 0x1ff;
1.471 + }
1.472 + __cpm_set_pixdiv(val);
1.473 +
1.474 + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
1.475 + if ( val > 150000000 ) {
1.476 + val = 150000000;
1.477 + }
1.478 + val = ( __cpm_get_pllout()/pll_div ) / val;
1.479 + val--;
1.480 + if ( val > 0x1f ) {
1.481 + val = 0x1f;
1.482 + }
1.483 +#endif
1.484 + __cpm_set_ldiv( val );
1.485 + lcd_ctrl_set(vid, CPM_CPCCR, lcd_ctrl_get(vid, CPM_CPCCR) | CPM_CPCCR_CE); /* update divide */
1.486 +}
1.487 +
1.488 +static void jz_lcd_hw_init(vidinfo_t *vid)
1.489 +{
1.490 + struct jzfb_info *jzfb = vid->jz_fb;
1.491 + uint32_t val = 0;
1.492 +
1.493 + /* Compute control register flags. */
1.494 +
1.495 + switch (jzfb->bpp) {
1.496 + case 1:
1.497 + val |= LCD_CTRL_BPP_1;
1.498 + break;
1.499 +
1.500 + case 2:
1.501 + val |= LCD_CTRL_BPP_2;
1.502 + break;
1.503 +
1.504 + case 4:
1.505 + val |= LCD_CTRL_BPP_4;
1.506 + break;
1.507 +
1.508 + case 8:
1.509 + val |= LCD_CTRL_BPP_8;
1.510 + break;
1.511 +
1.512 + case 15:
1.513 + val |= LCD_CTRL_RGB555;
1.514 + case 16:
1.515 + val |= LCD_CTRL_BPP_16;
1.516 + break;
1.517 +
1.518 + case 17 ... 32:
1.519 + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
1.520 + break;
1.521 +
1.522 + default:
1.523 + val |= LCD_CTRL_BPP_16; /* default to 16bpp */
1.524 + break;
1.525 + }
1.526 +
1.527 + /* Set various configuration registers for the panel. */
1.528 +
1.529 + switch (jzfb->cfg & MODE_MASK) {
1.530 + case MODE_STN_MONO_DUAL:
1.531 + case MODE_STN_COLOR_DUAL:
1.532 + val |= jz_lcd_stn_init(jzfb->h >> 1, vid);
1.533 + break;
1.534 +
1.535 + case MODE_STN_MONO_SINGLE:
1.536 + case MODE_STN_COLOR_SINGLE:
1.537 + val |= jz_lcd_stn_init(jzfb->h, vid);
1.538 + break;
1.539 +
1.540 + case MODE_TFT_GEN:
1.541 + case MODE_TFT_CASIO:
1.542 + case MODE_8BIT_SERIAL_TFT:
1.543 + case MODE_TFT_18BIT:
1.544 + jz_lcd_tft_init(vid);
1.545 + break;
1.546 +
1.547 + case MODE_TFT_SAMSUNG:
1.548 + jz_lcd_samsung_init(vid);
1.549 + break;
1.550 +
1.551 + case MODE_TFT_SHARP:
1.552 + jz_lcd_sharp_init(vid);
1.553 + break;
1.554 +
1.555 + default:
1.556 + break;
1.557 + }
1.558 +
1.559 + /* Further control register and panel configuration. */
1.560 +
1.561 + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
1.562 + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
1.563 +
1.564 + lcd_ctrl_set(vid, LCD_CTRL, val);
1.565 + lcd_ctrl_set(vid, LCD_CFG, jzfb->cfg);
1.566 +}
1.567 +
1.568 +static void jz_lcd_timing_init(vidinfo_t *vid)
1.569 +{
1.570 + __cpm_stop_lcd();
1.571 + jz_lcd_set_timing(vid);
1.572 + __cpm_start_lcd();
1.573 + udelay(1000);
1.574 +}
1.575 +
1.576 +/* Initialise DMA for the driver. */
1.577 +
1.578 +static void jz_lcd_dma_init(vidinfo_t *vid)
1.579 +{
1.580 + struct jz_mem_info *fbi = &vid->jz_mem;
1.581 + uint32_t mode = vid->jz_fb->cfg & MODE_MASK;
1.582 +
1.583 + /* Configure DMA by setting frame descriptor addresses. */
1.584 +
1.585 + lcd_ctrl_set(vid, LCD_DA0, (uint32_t) fbi->fdadr0);
1.586 +
1.587 + if ((mode == MODE_STN_COLOR_DUAL) || (mode == MODE_STN_MONO_DUAL))
1.588 + lcd_ctrl_set(vid, LCD_DA1, (uint32_t) fbi->fdadr1);
1.589 +}
1.590 +
1.591 +/* Public operations. */
1.592 +
1.593 +void lcd_set_bpp(uint8_t bpp)
1.594 +{
1.595 + vidinfo_t *vid = &panel_info;
1.596 + struct jzfb_info *jzfb = vid->jz_fb;
1.597 + jzfb->bpp = bpp;
1.598 +}
1.599 +
1.600 +void lcd_enable()
1.601 +{
1.602 + vidinfo_t *vid = &panel_info;
1.603 +
1.604 + /* Clear the disable bit (DIS) and set the enable bit (ENA). */
1.605 +
1.606 + lcd_ctrl_set(vid, LCD_CTRL, (lcd_ctrl_get(vid, LCD_CTRL) & ~LCD_CTRL_DIS) | LCD_CTRL_ENA);
1.607 +}
1.608 +
1.609 +void lcd_disable()
1.610 +{
1.611 + vidinfo_t *vid = &panel_info;
1.612 +
1.613 + /* Set the disable bit (DIS). */
1.614 +
1.615 + lcd_ctrl_set(vid, LCD_CTRL, lcd_ctrl_get(vid, LCD_CTRL) | LCD_CTRL_DIS);
1.616 +}
1.617 +
1.618 +void lcd_quick_disable()
1.619 +{
1.620 + vidinfo_t *vid = &panel_info;
1.621 +
1.622 + /* Clear the enable bit (ENA) for quick disable. */
1.623 +
1.624 + lcd_ctrl_set(vid, LCD_CTRL, lcd_ctrl_get(vid, LCD_CTRL) & ~LCD_CTRL_ENA);
1.625 +}
1.626 +
1.627 uint32_t lcd_ctrl_init()
1.628 {
1.629 vidinfo_t *vid = &panel_info;
1.630 @@ -534,6 +599,8 @@
1.631
1.632 jz_lcd_desc_init(vid);
1.633 jz_lcd_hw_init(vid);
1.634 + jz_lcd_timing_init(vid);
1.635 + jz_lcd_dma_init(vid);
1.636
1.637 return fbi->screen;
1.638 }