1.1 --- a/stage2/jzlcd.c Mon Jan 25 00:46:52 2016 +0100
1.2 +++ b/stage2/jzlcd.c Mon Jan 25 15:22:22 2016 +0100
1.3 @@ -41,37 +41,38 @@
1.4 return line_length * vid->vl_row;
1.5 }
1.6
1.7 -static unsigned long lcd_get_palette_size(vidinfo_t *vid)
1.8 +static unsigned long lcd_get_palette_size()
1.9 {
1.10 return 256 * sizeof(u16);
1.11 }
1.12
1.13 +static unsigned long lcd_get_descriptors_size()
1.14 +{
1.15 + return 3 * sizeof(struct jz_fb_dma_descriptor);
1.16 +}
1.17 +
1.18 static unsigned long lcd_get_aligned_size(vidinfo_t *vid)
1.19 {
1.20 - return ALIGN(lcd_get_size(vid), PAGE_SIZE);
1.21 -}
1.22 -
1.23 -static unsigned long lcd_get_aligned_palette_size(vidinfo_t *vid)
1.24 -{
1.25 - return ALIGN(lcd_get_palette_size(vid), PAGE_SIZE);
1.26 -}
1.27 -
1.28 -static unsigned long lcd_get_total_size(vidinfo_t *vid)
1.29 -{
1.30 /* Round up to nearest full page, or MMU section if defined */
1.31 - return lcd_get_aligned_size(vid) + lcd_get_aligned_palette_size(vid);
1.32 + return ALIGN(lcd_get_size(vid) + lcd_get_palette_size() + lcd_get_descriptors_size(), PAGE_SIZE);
1.33 }
1.34
1.35 static unsigned long lcd_get_palette(unsigned long addr)
1.36 {
1.37 - /* Allocate memory at the end of a page for the palette. */
1.38 - return addr - lcd_get_palette_size(&panel_info);
1.39 + /* Allocate memory at the end of the region for the palette. */
1.40 + return addr - lcd_get_palette_size();
1.41 +}
1.42 +
1.43 +static unsigned long lcd_get_descriptors(unsigned long addr)
1.44 +{
1.45 + /* Allocate memory before the palette for the descriptor array. */
1.46 + return addr - lcd_get_palette_size() - lcd_get_descriptors_size();
1.47 }
1.48
1.49 static unsigned long lcd_get_framebuffer(unsigned long addr)
1.50 {
1.51 /* Allocate pages for the frame buffer and palette. */
1.52 - return addr - lcd_get_total_size(&panel_info);
1.53 + return addr - lcd_get_aligned_size(&panel_info);
1.54 }
1.55
1.56 static void jz_lcd_desc_init(vidinfo_t *vid);
1.57 @@ -116,7 +117,7 @@
1.58
1.59 /* Allocate space for descriptors before the palette entries. */
1.60
1.61 - descriptors = ((struct jz_fb_dma_descriptor *) fbi->palette) - 3;
1.62 + descriptors = (struct jz_fb_dma_descriptor *) lcd_get_descriptors(get_memory_size());
1.63 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *) &descriptors[0];
1.64 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *) &descriptors[1];
1.65 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *) &descriptors[2];
1.66 @@ -218,14 +219,84 @@
1.67 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
1.68 }
1.69
1.70 +static unsigned int jz_lcd_get_pixel_clock()
1.71 +{
1.72 + unsigned int pclk;
1.73 +
1.74 + /* Derive pixel clock from frame clock. */
1.75 +
1.76 + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
1.77 + pclk = jzfb.fclk * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
1.78 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw);
1.79 + } else {
1.80 + /* serial mode: Hsync period = 3*Width_Pixel */
1.81 + pclk = jzfb.fclk * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
1.82 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw);
1.83 + }
1.84 +
1.85 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
1.86 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
1.87 + pclk = (pclk * 3);
1.88 +
1.89 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
1.90 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
1.91 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
1.92 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
1.93 + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
1.94 +
1.95 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
1.96 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
1.97 + pclk >>= 1;
1.98 +
1.99 + return pclk;
1.100 +}
1.101 +
1.102 +static void jz_lcd_set_timing(unsigned int pclk)
1.103 +{
1.104 + unsigned int val;
1.105 +
1.106 +#ifdef CONFIG_CPU_JZ4730
1.107 + val = __cpm_get_pllout() / pclk;
1.108 + REG_CPM_CFCR2 = val - 1;
1.109 + val = pclk * 4 ;
1.110 + if ( val > 150000000 ) {
1.111 + val = 150000000;
1.112 + }
1.113 + val = __cpm_get_pllout() / val;
1.114 + val--;
1.115 + if ( val > 0xF )
1.116 + val = 0xF;
1.117 +#else
1.118 + int pll_div;
1.119 +
1.120 + pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
1.121 + pll_div = pll_div ? 1 : 2 ;
1.122 + val = ( __cpm_get_pllout()/pll_div ) / pclk;
1.123 + val--;
1.124 + if ( val > 0x1ff ) {
1.125 + val = 0x1ff;
1.126 + }
1.127 + __cpm_set_pixdiv(val);
1.128 +
1.129 + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
1.130 + if ( val > 150000000 ) {
1.131 + val = 150000000;
1.132 + }
1.133 + val = ( __cpm_get_pllout()/pll_div ) / val;
1.134 + val--;
1.135 + if ( val > 0x1f ) {
1.136 + val = 0x1f;
1.137 + }
1.138 +#endif
1.139 + __cpm_set_ldiv( val );
1.140 + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
1.141 +}
1.142 +
1.143 static int jz_lcd_hw_init(vidinfo_t *vid)
1.144 {
1.145 struct jz_fb_info *fbi = &vid->jz_fb;
1.146 unsigned int val = 0;
1.147 - unsigned int pclk;
1.148 -#ifndef CONFIG_CPU_JZ4730
1.149 - int pll_div;
1.150 -#endif
1.151 + unsigned int pclk = jz_lcd_get_pixel_clock();
1.152
1.153 /* Setting Control register */
1.154 switch (jzfb.bpp) {
1.155 @@ -282,9 +353,6 @@
1.156
1.157 jz_lcd_tft_init();
1.158
1.159 - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
1.160 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
1.161 -
1.162 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
1.163 tp_s = jzfb.blw + jzfb.w + 1;
1.164 tp_e = tp_s + 1;
1.165 @@ -338,67 +406,10 @@
1.166 REG_LCD_CTRL = val;
1.167 REG_LCD_CFG = jzfb.cfg;
1.168
1.169 - /* Timing setting */
1.170 - __cpm_stop_lcd();
1.171 -
1.172 - val = jzfb.fclk; /* frame clk */
1.173 - if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
1.174 - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
1.175 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
1.176 - } else {
1.177 - /* serial mode: Hsync period = 3*Width_Pixel */
1.178 - pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
1.179 - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
1.180 - }
1.181 -
1.182 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
1.183 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
1.184 - pclk = (pclk * 3);
1.185 -
1.186 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
1.187 - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
1.188 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
1.189 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
1.190 - pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
1.191 -
1.192 - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
1.193 - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
1.194 - pclk >>= 1;
1.195 + /* Timing reset. */
1.196
1.197 -#ifdef CONFIG_CPU_JZ4730
1.198 - val = __cpm_get_pllout() / pclk;
1.199 - REG_CPM_CFCR2 = val - 1;
1.200 - val = pclk * 4 ;
1.201 - if ( val > 150000000 ) {
1.202 - val = 150000000;
1.203 - }
1.204 - val = __cpm_get_pllout() / val;
1.205 - val--;
1.206 - if ( val > 0xF )
1.207 - val = 0xF;
1.208 -#else
1.209 - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
1.210 - pll_div = pll_div ? 1 : 2 ;
1.211 - val = ( __cpm_get_pllout()/pll_div ) / pclk;
1.212 - val--;
1.213 - if ( val > 0x1ff ) {
1.214 - val = 0x1ff;
1.215 - }
1.216 - __cpm_set_pixdiv(val);
1.217 -
1.218 - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
1.219 - if ( val > 150000000 ) {
1.220 - val = 150000000;
1.221 - }
1.222 - val = ( __cpm_get_pllout()/pll_div ) / val;
1.223 - val--;
1.224 - if ( val > 0x1f ) {
1.225 - val = 0x1f;
1.226 - }
1.227 -#endif
1.228 - __cpm_set_ldiv( val );
1.229 - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
1.230 -
1.231 + __cpm_stop_lcd();
1.232 + jz_lcd_set_timing(pclk);
1.233 __cpm_start_lcd();
1.234 udelay(1000);
1.235