1.1 --- a/stage2/board-nanonote.c Tue Jun 09 00:03:27 2015 +0200
1.2 +++ b/stage2/board-nanonote.c Tue Jun 09 21:10:40 2015 +0200
1.3 @@ -1,10 +1,10 @@
1.4 /*
1.5 * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools.
1.6 *
1.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
1.9 + * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
1.10 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
1.11 - * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
1.12 - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
1.13 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.14 *
1.15 * This program is free software; you can redistribute it and/or modify it under
1.16 * the terms of the GNU General Public License as published by the Free Software
1.17 @@ -20,7 +20,7 @@
1.18 * this program. If not, see <http://www.gnu.org/licenses/>.
1.19 */
1.20
1.21 -#include "jz4740.h"
1.22 +#include "board.h"
1.23 #include "nanonote.h"
1.24
1.25 /* Later initialisation functions. */
1.26 @@ -106,37 +106,10 @@
1.27 REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
1.28 }
1.29
1.30 -unsigned long get_memory_size(void)
1.31 -{
1.32 - unsigned int dmcr;
1.33 - unsigned int rows, cols, dw, banks;
1.34 - unsigned long size;
1.35 -
1.36 - dmcr = REG_EMC_DMCR;
1.37 - rows = SDRAM_ROW0 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
1.38 - cols = SDRAM_COL0 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
1.39 - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
1.40 - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
1.41 -
1.42 - size = (1 << (rows + cols)) * dw * banks;
1.43 -
1.44 - return size;
1.45 -}
1.46 -
1.47 /* Timer routines. */
1.48
1.49 -#define TIMER_CHAN 0
1.50 -#define TIMER_FDATA 0xffff /* Timer full data value */
1.51 -#define TIMER_HZ CONFIG_SYS_HZ
1.52 -
1.53 -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
1.54 -
1.55 -static unsigned long timestamp;
1.56 -static unsigned long lastdec;
1.57 -
1.58 -void reset_timer_masked(void);
1.59 -unsigned long get_timer_masked(void);
1.60 -void udelay_masked(unsigned long usec);
1.61 +unsigned long timestamp;
1.62 +unsigned long lastdec;
1.63
1.64 /*
1.65 * timer without interrupts
1.66 @@ -158,176 +131,3 @@
1.67
1.68 return 0;
1.69 }
1.70 -
1.71 -void reset_timer(void)
1.72 -{
1.73 - reset_timer_masked ();
1.74 -}
1.75 -
1.76 -unsigned long get_timer(unsigned long base)
1.77 -{
1.78 - return get_timer_masked () - base;
1.79 -}
1.80 -
1.81 -void set_timer(unsigned long t)
1.82 -{
1.83 - timestamp = t;
1.84 -}
1.85 -
1.86 -void udelay (unsigned long usec)
1.87 -{
1.88 - unsigned long tmo,tmp;
1.89 -
1.90 - /* normalize */
1.91 - if (usec >= 1000) {
1.92 - tmo = usec / 1000;
1.93 - tmo *= TIMER_HZ;
1.94 - tmo /= 1000;
1.95 - }
1.96 - else {
1.97 - if (usec >= 1) {
1.98 - tmo = usec * TIMER_HZ;
1.99 - tmo /= (1000*1000);
1.100 - }
1.101 - else
1.102 - tmo = 1;
1.103 - }
1.104 -
1.105 - /* check for rollover during this delay */
1.106 - tmp = get_timer (0);
1.107 - if ((tmp + tmo) < tmp )
1.108 - reset_timer_masked(); /* timer would roll over */
1.109 - else
1.110 - tmo += tmp;
1.111 -
1.112 - while (get_timer_masked () < tmo);
1.113 -}
1.114 -
1.115 -void reset_timer_masked (void)
1.116 -{
1.117 - /* reset time */
1.118 - lastdec = READ_TIMER;
1.119 - timestamp = 0;
1.120 -}
1.121 -
1.122 -unsigned long get_timer_masked (void)
1.123 -{
1.124 - unsigned long now = READ_TIMER;
1.125 -
1.126 - if (lastdec <= now) {
1.127 - /* normal mode */
1.128 - timestamp += (now - lastdec);
1.129 - } else {
1.130 - /* we have an overflow ... */
1.131 - timestamp += TIMER_FDATA + now - lastdec;
1.132 - }
1.133 - lastdec = now;
1.134 -
1.135 - return timestamp;
1.136 -}
1.137 -
1.138 -void udelay_masked (unsigned long usec)
1.139 -{
1.140 - unsigned long tmo;
1.141 - unsigned long endtime;
1.142 - signed long diff;
1.143 -
1.144 - /* normalize */
1.145 - if (usec >= 1000) {
1.146 - tmo = usec / 1000;
1.147 - tmo *= TIMER_HZ;
1.148 - tmo /= 1000;
1.149 - } else {
1.150 - if (usec > 1) {
1.151 - tmo = usec * TIMER_HZ;
1.152 - tmo /= (1000*1000);
1.153 - } else {
1.154 - tmo = 1;
1.155 - }
1.156 - }
1.157 -
1.158 - endtime = get_timer_masked () + tmo;
1.159 -
1.160 - do {
1.161 - unsigned long now = get_timer_masked ();
1.162 - diff = endtime - now;
1.163 - } while (diff >= 0);
1.164 -}
1.165 -
1.166 -/*
1.167 - * This function is derived from PowerPC code (read timebase as long long).
1.168 - * On MIPS it just returns the timer value.
1.169 - */
1.170 -unsigned long long get_ticks(void)
1.171 -{
1.172 - return get_timer(0);
1.173 -}
1.174 -
1.175 -/*
1.176 - * This function is derived from PowerPC code (timebase clock frequency).
1.177 - * On MIPS it returns the number of timer ticks per second.
1.178 - */
1.179 -unsigned long get_tbclk (void)
1.180 -{
1.181 - return TIMER_HZ;
1.182 -}
1.183 -
1.184 -/* CPU-specific routines from U-Boot.
1.185 - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
1.186 - See: u-boot/arch/mips/include/asm/cacheops.h
1.187 -*/
1.188 -
1.189 -#define Index_Store_Tag_I 0x08
1.190 -#define Index_Writeback_Inv_D 0x15
1.191 -
1.192 -void flush_icache_all(void)
1.193 -{
1.194 - u32 addr, t = 0;
1.195 -
1.196 - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
1.197 - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
1.198 -
1.199 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
1.200 - addr += CONFIG_SYS_CACHELINE_SIZE) {
1.201 - asm volatile (
1.202 - ".set mips3\n\t"
1.203 - " cache %0, 0(%1)\n\t"
1.204 - ".set mips2\n\t"
1.205 - :
1.206 - : "I" (Index_Store_Tag_I), "r"(addr));
1.207 - }
1.208 -
1.209 - /* invalicate btb */
1.210 - asm volatile (
1.211 - ".set mips32\n\t"
1.212 - "mfc0 %0, $16, 7\n\t"
1.213 - "nop\n\t"
1.214 - "ori %0,2\n\t"
1.215 - "mtc0 %0, $16, 7\n\t"
1.216 - ".set mips2\n\t"
1.217 - :
1.218 - : "r" (t));
1.219 -}
1.220 -
1.221 -void flush_dcache_all(void)
1.222 -{
1.223 - u32 addr;
1.224 -
1.225 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
1.226 - addr += CONFIG_SYS_CACHELINE_SIZE) {
1.227 - asm volatile (
1.228 - ".set mips3\n\t"
1.229 - " cache %0, 0(%1)\n\t"
1.230 - ".set mips2\n\t"
1.231 - :
1.232 - : "I" (Index_Writeback_Inv_D), "r"(addr));
1.233 - }
1.234 -
1.235 - asm volatile ("sync");
1.236 -}
1.237 -
1.238 -void flush_cache_all(void)
1.239 -{
1.240 - flush_dcache_all();
1.241 - flush_icache_all();
1.242 -}