1.1 --- a/board-nanonote.c Sun Jun 07 18:21:24 2015 +0200
1.2 +++ b/board-nanonote.c Sun Jun 07 20:17:24 2015 +0200
1.3 @@ -30,33 +30,19 @@
1.4
1.5 struct fw_args *fw_args;
1.6 volatile u32 CPU_ID;
1.7 -volatile u32 UART_BASE;
1.8 -volatile u32 CONFIG_BAUDRATE;
1.9 volatile u8 SDRAM_BW16;
1.10 volatile u8 SDRAM_BANK4;
1.11 volatile u8 SDRAM_ROW;
1.12 volatile u8 SDRAM_COL;
1.13 volatile u8 CONFIG_MOBILE_SDRAM;
1.14 -volatile u32 CFG_CPU_SPEED;
1.15 -volatile u32 CFG_EXTAL;
1.16 -volatile u8 PHM_DIV;
1.17 volatile u8 IS_SHARE;
1.18
1.19 void load_args(void)
1.20 {
1.21 - /* Get the fw args from memory. See head.S for the memory layout. */
1.22 + /* Get the fw args from memory. See head1.S for the memory layout. */
1.23
1.24 fw_args = (struct fw_args *)0x80002008;
1.25 CPU_ID = fw_args->cpu_id ;
1.26 - CFG_EXTAL = (u32)fw_args->ext_clk * 1000000;
1.27 - CFG_CPU_SPEED = (u32)fw_args->cpu_speed * CFG_EXTAL ;
1.28 - if (CFG_EXTAL == 19000000) {
1.29 - CFG_EXTAL = 19200000;
1.30 - CFG_CPU_SPEED = 192000000;
1.31 - }
1.32 - PHM_DIV = fw_args->phm_div;
1.33 - UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000;
1.34 - CONFIG_BAUDRATE = fw_args->boudrate;
1.35 SDRAM_BW16 = fw_args->bus_width;
1.36 SDRAM_BANK4 = fw_args->bank_num;
1.37 SDRAM_ROW = fw_args->row_addr;
1.38 @@ -77,46 +63,54 @@
1.39 /*
1.40 * Initialize SDRAM pins
1.41 */
1.42 - __gpio_as_sdram_32bit();
1.43 + __gpio_as_sdram_16bit_4720();
1.44 }
1.45
1.46 void pll_init(void)
1.47 {
1.48 register unsigned int cfcr, plcr1;
1.49 - int n2FR[33] = {
1.50 - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
1.51 - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
1.52 - 9
1.53 - };
1.54 int nf, pllout2;
1.55
1.56 + /* See CPCCR (Clock Control Register).
1.57 + * 0 == same frequency; 2 == f/3
1.58 + */
1.59 +
1.60 cfcr = CPM_CPCCR_CLKOEN |
1.61 - (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) |
1.62 - (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
1.63 - (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
1.64 - (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
1.65 - (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
1.66 + CPM_CPCCR_PCS |
1.67 + (0 << CPM_CPCCR_CDIV_BIT) |
1.68 + (2 << CPM_CPCCR_HDIV_BIT) |
1.69 + (2 << CPM_CPCCR_PDIV_BIT) |
1.70 + (2 << CPM_CPCCR_MDIV_BIT) |
1.71 + (2 << CPM_CPCCR_LDIV_BIT);
1.72
1.73 - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
1.74 + /* Determine the divider clock output based on the PCS bit. */
1.75 +
1.76 + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
1.77
1.78 - /* Init USB Host clock, pllout2 must be n*48MHz */
1.79 + /* Init USB Host clock.
1.80 + * Divisor == UHCCDR + 1
1.81 + * Desired frequency == 48MHz
1.82 + */
1.83 +
1.84 REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
1.85
1.86 - nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
1.87 - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
1.88 - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
1.89 - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
1.90 - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
1.91 - CPM_CPPCR_PLLEN; /* enable PLL */
1.92 + nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
1.93 + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
1.94 + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
1.95 + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
1.96 + CPM_CPPCR_PLLEN; /* enable PLL */
1.97
1.98 - /* init PLL */
1.99 + /* Update PLL and wait. */
1.100 +
1.101 REG_CPM_CPCCR = cfcr;
1.102 REG_CPM_CPPCR = plcr1;
1.103 + while (!__cpm_pll_is_on());
1.104 }
1.105
1.106 void sdram_init(void)
1.107 {
1.108 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
1.109 + unsigned int pllout = __cpm_get_pllout();
1.110
1.111 unsigned int cas_latency_sdmr[2] = {
1.112 EMC_SDMR_CAS_2,
1.113 @@ -128,10 +122,12 @@
1.114 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
1.115 };
1.116
1.117 + /* Divisors for CPCCR values. */
1.118 +
1.119 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.120
1.121 - cpu_clk = CFG_CPU_SPEED;
1.122 - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
1.123 + cpu_clk = pllout / div[__cpm_get_cdiv()];
1.124 + mem_clk = pllout / div[__cpm_get_mdiv()];
1.125
1.126 REG_EMC_BCR = 0; /* Disable bus release */
1.127 REG_EMC_RTCSR = 0; /* Disable clock for counting */