1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/board-nanonote.c Fri May 22 18:37:44 2015 +0200
1.3 @@ -0,0 +1,232 @@
1.4 +/*
1.5 + * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools.
1.6 + *
1.7 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
1.9 + * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
1.10 + *
1.11 + * This program is free software; you can redistribute it and/or modify it under
1.12 + * the terms of the GNU General Public License as published by the Free Software
1.13 + * Foundation; either version 3 of the License, or (at your option) any later
1.14 + * version.
1.15 + *
1.16 + * This program is distributed in the hope that it will be useful, but WITHOUT
1.17 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
1.18 + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
1.19 + * details.
1.20 + *
1.21 + * You should have received a copy of the GNU General Public License along with
1.22 + * this program. If not, see <http://www.gnu.org/licenses/>.
1.23 + */
1.24 +
1.25 +#include "jz4740.h"
1.26 +#include "configs.h"
1.27 +
1.28 +void gpio_init(void)
1.29 +{
1.30 + /*
1.31 + * Initialize NAND Flash Pins
1.32 + */
1.33 + __gpio_as_nand();
1.34 +
1.35 + /*
1.36 + * Initialize SDRAM pins
1.37 + */
1.38 + __gpio_as_sdram_32bit();
1.39 +
1.40 + /*
1.41 + * Initialize LCD pins
1.42 + */
1.43 + __gpio_as_lcd_8bit();
1.44 +
1.45 + /*
1.46 + * Initialize MSC pins
1.47 + */
1.48 + __gpio_as_msc();
1.49 +
1.50 + /*
1.51 + * Initialize Other pins
1.52 + */
1.53 + unsigned int i;
1.54 + for (i = 0; i < 7; i++){
1.55 + __gpio_as_input(GPIO_KEYIN_BASE + i);
1.56 + __gpio_enable_pull(GPIO_KEYIN_BASE + i);
1.57 + }
1.58 +
1.59 + for (i = 0; i < 8; i++) {
1.60 + __gpio_as_output(GPIO_KEYOUT_BASE + i);
1.61 + __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
1.62 + }
1.63 +
1.64 + /* enable the TP4, TP5 as UART0 */
1.65 + __gpio_jtag_to_uart0();
1.66 +
1.67 + __gpio_as_input(GPIO_KEYIN_8);
1.68 + __gpio_enable_pull(GPIO_KEYIN_8);
1.69 +
1.70 + __gpio_as_output(GPIO_AUDIO_POP);
1.71 + __gpio_set_pin(GPIO_AUDIO_POP);
1.72 +
1.73 + __gpio_as_output(GPIO_LCD_CS);
1.74 + __gpio_clear_pin(GPIO_LCD_CS);
1.75 +
1.76 + __gpio_as_output(GPIO_AMP_EN);
1.77 + __gpio_clear_pin(GPIO_AMP_EN);
1.78 +
1.79 + __gpio_as_output(GPIO_SDPW_EN);
1.80 + __gpio_disable_pull(GPIO_SDPW_EN);
1.81 + __gpio_clear_pin(GPIO_SDPW_EN);
1.82 +
1.83 + __gpio_as_input(GPIO_SD_DETECT);
1.84 + __gpio_disable_pull(GPIO_SD_DETECT);
1.85 +
1.86 + __gpio_as_input(GPIO_USB_DETECT);
1.87 + __gpio_enable_pull(GPIO_USB_DETECT);
1.88 +}
1.89 +
1.90 +void cpm_init(void)
1.91 +{
1.92 + __cpm_stop_ipu();
1.93 + __cpm_stop_cim();
1.94 + __cpm_stop_i2c();
1.95 + __cpm_stop_ssi();
1.96 + __cpm_stop_uart1();
1.97 + __cpm_stop_sadc();
1.98 + __cpm_stop_uhc();
1.99 + __cpm_stop_udc();
1.100 + __cpm_stop_aic1();
1.101 +/* __cpm_stop_aic2();*/
1.102 +}
1.103 +
1.104 +void pll_init(void)
1.105 +{
1.106 + register unsigned int cfcr, plcr1;
1.107 + int n2FR[33] = {
1.108 + 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
1.109 + 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
1.110 + 9
1.111 + };
1.112 + int nf, pllout2;
1.113 +
1.114 + cfcr = CPM_CPCCR_CLKOEN |
1.115 + (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) |
1.116 + (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
1.117 + (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
1.118 + (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
1.119 + (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
1.120 +
1.121 + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
1.122 +
1.123 + /* Init USB Host clock, pllout2 must be n*48MHz */
1.124 + REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
1.125 +
1.126 + nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
1.127 + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
1.128 + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
1.129 + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
1.130 + (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
1.131 + CPM_CPPCR_PLLEN; /* enable PLL */
1.132 +
1.133 + /* init PLL */
1.134 + REG_CPM_CPCCR = cfcr;
1.135 + REG_CPM_CPPCR = plcr1;
1.136 +}
1.137 +
1.138 +void sdram_init(void)
1.139 +{
1.140 + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
1.141 +
1.142 + unsigned int cas_latency_sdmr[2] = {
1.143 + EMC_SDMR_CAS_2,
1.144 + EMC_SDMR_CAS_3,
1.145 + };
1.146 +
1.147 + unsigned int cas_latency_dmcr[2] = {
1.148 + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
1.149 + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
1.150 + };
1.151 +
1.152 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.153 +
1.154 + cpu_clk = CFG_CPU_SPEED;
1.155 + mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
1.156 +
1.157 + REG_EMC_BCR = 0; /* Disable bus release */
1.158 + REG_EMC_RTCSR = 0; /* Disable clock for counting */
1.159 +
1.160 + /* Fault DMCR value for mode register setting*/
1.161 +#define SDRAM_ROW0 11
1.162 +#define SDRAM_COL0 8
1.163 +#define SDRAM_BANK40 0
1.164 +
1.165 + dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
1.166 + ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
1.167 + (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
1.168 + (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.169 + EMC_DMCR_EPIN |
1.170 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
1.171 +
1.172 + /* Basic DMCR value */
1.173 + dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
1.174 + ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
1.175 + (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
1.176 + (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.177 + EMC_DMCR_EPIN |
1.178 + cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
1.179 +
1.180 + /* SDRAM timimg */
1.181 + ns = 1000000000 / mem_clk;
1.182 + tmp = SDRAM_TRAS/ns;
1.183 + if (tmp < 4) tmp = 4;
1.184 + if (tmp > 11) tmp = 11;
1.185 + dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
1.186 + tmp = SDRAM_RCD/ns;
1.187 + if (tmp > 3) tmp = 3;
1.188 + dmcr |= (tmp << EMC_DMCR_RCD_BIT);
1.189 + tmp = SDRAM_TPC/ns;
1.190 + if (tmp > 7) tmp = 7;
1.191 + dmcr |= (tmp << EMC_DMCR_TPC_BIT);
1.192 + tmp = SDRAM_TRWL/ns;
1.193 + if (tmp > 3) tmp = 3;
1.194 + dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
1.195 + tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
1.196 + if (tmp > 14) tmp = 14;
1.197 + dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
1.198 +
1.199 + /* SDRAM mode value */
1.200 + sdmode = EMC_SDMR_BT_SEQ |
1.201 + EMC_SDMR_OM_NORMAL |
1.202 + EMC_SDMR_BL_4 |
1.203 + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
1.204 +
1.205 + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
1.206 + REG_EMC_DMCR = dmcr;
1.207 + REG8(EMC_SDMR0|sdmode) = 0;
1.208 +
1.209 + /* Wait for precharge, > 200us */
1.210 + tmp = (cpu_clk / 1000000) * 1000;
1.211 + while (tmp--);
1.212 +
1.213 + /* Stage 2. Enable auto-refresh */
1.214 + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
1.215 +
1.216 + tmp = SDRAM_TREF/ns;
1.217 + tmp = tmp/64 + 1;
1.218 + if (tmp > 0xff) tmp = 0xff;
1.219 + REG_EMC_RTCOR = tmp;
1.220 + REG_EMC_RTCNT = 0;
1.221 + REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
1.222 +
1.223 + /* Wait for number of auto-refresh cycles */
1.224 + tmp = (cpu_clk / 1000000) * 1000;
1.225 + while (tmp--);
1.226 +
1.227 + /* Stage 3. Mode Register Set */
1.228 + REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
1.229 + REG8(EMC_SDMR0|sdmode) = 0;
1.230 +
1.231 + /* Set back to basic DMCR value */
1.232 + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
1.233 +
1.234 + /* everything is ok now */
1.235 +}
