1.1 --- a/stage2/head2.S Tue Jun 23 23:08:19 2015 +0200
1.2 +++ b/stage2/head2.S Wed Jun 24 13:29:41 2015 +0200
1.3 @@ -34,13 +34,16 @@
1.4
1.5 la $sp, 0x80080000
1.6
1.7 + /* Initialise the globals pointer. */
1.8 +
1.9 + lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
1.10 + ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
1.11 +
1.12 /* Copy TLB handling instructions. */
1.13
1.14 - lui $t0, %hi(_tlb_entry) /* start */
1.15 - ori $t0, $t0, %lo(_tlb_entry)
1.16 + la $t0, _tlb_entry /* start */
1.17 li $t1, 0x80000000
1.18 - lui $t2, %hi(_exc_entry) /* end */
1.19 - ori $t2, $t2, %lo(_exc_entry)
1.20 + la $t2, _cache_entry /* end */
1.21 _tlb_copy:
1.22 lw $t3, 0($t0)
1.23 addiu $t0, $t0, 4
1.24 @@ -48,12 +51,23 @@
1.25 bne $t0, $t2, _tlb_copy
1.26 addiu $t1, $t1, 4 /* executed in delay slot before branch */
1.27
1.28 + /* Copy cache handling instructions. */
1.29 +
1.30 + move $t0, $t2 /* start */
1.31 + li $t1, 0x80000100
1.32 + la $t2, _exc_entry /* end */
1.33 +_cache_copy:
1.34 + lw $t3, 0($t0)
1.35 + addiu $t0, $t0, 4
1.36 + sw $t3, 0($t1)
1.37 + bne $t0, $t2, _cache_copy
1.38 + addiu $t1, $t1, 4 /* executed in delay slot before branch */
1.39 +
1.40 /* Copy exception handling instructions. */
1.41
1.42 move $t0, $t2 /* start */
1.43 li $t1, 0x80000180
1.44 - lui $t2, %hi(_irq_entry) /* end */
1.45 - ori $t2, $t2, %lo(_irq_entry)
1.46 + la $t2, _irq_entry /* end */
1.47 _exc_copy:
1.48 lw $t3, 0($t0)
1.49 addiu $t0, $t0, 4
1.50 @@ -65,8 +79,7 @@
1.51
1.52 move $t0, $t2 /* start */
1.53 li $t1, 0x80000200
1.54 - lui $t2, %hi(_end_entries) /* end */
1.55 - ori $t2, $t2, %lo(_end_entries)
1.56 + la $t2, _end_entries /* end */
1.57 _irq_copy:
1.58 lw $t3, 0($t0)
1.59 addiu $t0, $t0, 4