1.1 --- a/stage1/board-nanonote.c Mon Jun 08 19:20:02 2015 +0200
1.2 +++ b/stage1/board-nanonote.c Mon Jun 08 19:33:10 2015 +0200
1.3 @@ -132,21 +132,17 @@
1.4 REG_EMC_RTCSR = 0; /* Disable clock for counting */
1.5
1.6 /* Fault DMCR value for mode register setting*/
1.7 -#define SDRAM_ROW0 11
1.8 -#define SDRAM_COL0 8
1.9 -#define SDRAM_BANK40 0
1.10 -
1.11 - dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
1.12 - ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
1.13 - (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
1.14 + dmcr0 = (0<<EMC_DMCR_RA_BIT) |
1.15 + (0<<EMC_DMCR_CA_BIT) |
1.16 + (0<<EMC_DMCR_BA_BIT) |
1.17 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.18 EMC_DMCR_EPIN |
1.19 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
1.20
1.21 /* Basic DMCR value */
1.22 - dmcr = ((FW_SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
1.23 - ((FW_SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
1.24 - (FW_SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
1.25 + dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) |
1.26 + ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) |
1.27 + ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) |
1.28 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
1.29 EMC_DMCR_EPIN |
1.30 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];