1.1 --- a/stage2/jzlcd.c Tue Jun 09 23:11:32 2015 +0200
1.2 +++ b/stage2/jzlcd.c Tue Jun 09 23:55:00 2015 +0200
1.3 @@ -128,7 +128,9 @@
1.4 unsigned int val = 0;
1.5 unsigned int pclk;
1.6 unsigned int stnH;
1.7 +#ifndef CONFIG_CPU_JZ4730
1.8 int pll_div;
1.9 +#endif
1.10
1.11 /* Setting Control register */
1.12 switch (jzfb.bpp) {
1.13 @@ -149,10 +151,11 @@
1.14 case 16:
1.15 val |= LCD_CTRL_BPP_16;
1.16 break;
1.17 +#ifndef CONFIG_CPU_JZ4730
1.18 case 17 ... 32:
1.19 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
1.20 break;
1.21 -
1.22 +#endif
1.23 default:
1.24 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */
1.25 val |= LCD_CTRL_BPP_16;