1 /* 2 * Common SDRAM configuration. 3 * 4 * Copyright (C) 1996, 1997 by Ralf Baechle 5 * 6 * Copyright (C) 2009 Qi Hardware Inc. 7 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> 8 * 9 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 10 * 11 * This program is free software: you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 3 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef __SDRAM_H__ 26 #define __SDRAM_H__ 27 28 /* 29 * RAM configuration 30 */ 31 #define CONFIG_SYS_SDRAM_BASE 0x80000000 32 33 /* 34 * SDRAM configuration (timings in ns) 35 */ 36 #ifdef CONFIG_CPU_JZ4730_MINIPC 37 #define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ 38 #else 39 #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ 40 #endif 41 42 #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ 43 #define SDRAM_ROW 13 /* Row address: 11 to 13 */ 44 #define SDRAM_COL 9 /* Column address: 8 to 12 */ 45 #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ 46 #define SDRAM_TRAS 45 /* RAS# Active Time */ 47 #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ 48 #define SDRAM_TPC 20 /* RAS# Precharge Time */ 49 #define SDRAM_TRWL 7 /* Write Latency Time */ 50 51 #ifdef CONFIG_CPU_JZ4730_MINIPC 52 #define SDRAM_TREF 7812 /* Refresh period: 8192 cycles/64ms */ 53 #else 54 #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ 55 #endif 56 57 #define SDRAM_ROW0 11 /* Row address minimum */ 58 #define SDRAM_COL0 8 /* Column address minimum */ 59 #define SDRAM_BANK40 0 /* Bank minimum */ 60 61 /* 62 * Cache configuration 63 */ 64 #define CONFIG_SYS_DCACHE_SIZE 16384 65 #define CONFIG_SYS_ICACHE_SIZE 16384 66 #define CONFIG_SYS_CACHELINE_SIZE 32 67 68 #define Index_Invalidate_I 0x00 69 #define Index_Writeback_Inv_D 0x01 70 #define Index_Store_Tag_I 0x08 71 #define Index_Store_Tag_D 0x09 72 #define Hit_Writeback_Inv_D 0x15 73 74 #define CONFIG_CM_UNCACHED 2 75 #define CONFIG_CM_CACHABLE_NONCOHERENT 3 76 77 /* 78 * Memory configuration 79 */ 80 #define KSEG0 0x80000000 81 #define PAGE_SIZE 4096 82 83 #endif /* __SDRAM_H__ */