1 /* 2 * Interrupt and TLB miss handling support. 3 * 4 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 .text 21 .extern interrupt_handler 22 .extern current_registers 23 .extern current_stack_pointer 24 .globl _tlb_entry 25 .globl _exc_entry 26 .globl _irq_entry 27 .globl _end_entries 28 .set noreorder 29 30 /* NOTE: Duplicated from cpu.h. */ 31 32 #define page_table_start 0x80040000 33 #define page_table_task_size 0x00008000 34 35 _tlb_entry: 36 /* Get the bad address. */ 37 38 mfc0 $k0, $10 /* CP0_ENTRYHI */ 39 nop 40 andi $k1, $k0, 0xff /* ASID */ 41 42 /* For ASID == 0... */ 43 44 beqz $k1, _tlb_entry_direct 45 nop 46 47 /* For addresses over 0x00080000... */ 48 49 li $k1, 0xfff80000 50 and $k1, $k0, $k1 51 bnez $k1, _tlb_entry_direct 52 nop 53 54 /* Otherwise, load the page table entries. */ 55 56 andi $k1, $k0, 0xff /* ASID */ 57 li $k0, page_table_task_size 58 mul $k0, $k0, $k1 /* [ASID] (ASID * page_table_task_size) */ 59 li $k1, page_table_start /* page_table */ 60 addu $k1, $k0, $k1 /* page_table[ASID] */ 61 62 mfc0 $k0, $4 /* CP0_CONTEXT */ 63 nop 64 srl $k0, $k0, 1 /* use 8 byte - not 16 byte - entries */ 65 addu $k0, $k0, $k1 /* page_table[ASID][entry] */ 66 67 lw $k1, 0($k0) /* page_table[ASID][entry][0] */ 68 mtc0 $k1, $2 /* CP0_ENTRYLO0 */ 69 70 lw $k1, 4($k0) /* page_table[ASID][entry][1] */ 71 mtc0 $k1, $3 /* CP0_ENTRYLO1 */ 72 /* page size is 4KB */ 73 mtc0 $zero, $5 /* CP0_PAGEMASK */ 74 nop 75 76 tlbwr 77 nop 78 eret 79 nop 80 81 _tlb_entry_direct: 82 /* Otherwise, just translate the address directly. */ 83 84 li $k1, 0xffffe000 85 and $k0, $k0, $k1 /* VPN2 (8KB resolution) */ 86 srl $k0, $k0, 6 /* PFN (maintain 8KB resolution, bit 6 remaining zero) */ 87 ori $k0, $k0, 0x1e /* flags */ 88 89 mtc0 $k0, $2 /* CP0_ENTRYLO0 */ 90 ori $k0, $k0, 0x40 /* page size is 4KB (bit 6 set) */ 91 mtc0 $k0, $3 /* CP0_ENTRYLO1 */ 92 nop /* page size is 4KB */ 93 mtc0 $zero, $5 /* CP0_PAGEMASK */ 94 nop 95 96 tlbwr 97 nop 98 eret 99 nop 100 101 _exc_entry: 102 /* Handle TLB refill exceptions. */ 103 104 mfc0 $k0, $13 /* CP0_CAUSE */ 105 li $k1, 0x0000007c 106 and $k0, $k0, $k1 /* ExcCode << 2 */ 107 srl $k0, $k0, 2 /* ExcCode */ 108 addi $k1, $k0, -2 /* ExcCode == 2 */ 109 beqz $k1, _tlb_entry 110 addi $k1, $k0, -3 /* ExcCode == 3 */ 111 beqz $k1, _tlb_entry 112 nop 113 _fail: 114 b _fail 115 nop 116 117 _irq_entry: 118 /* Set the ASID. */ 119 120 mtc0 $zero, $10 /* CP0_ENTRYHI */ 121 nop 122 123 /* Obtain the kernel global offset table. */ 124 125 move $k0, $gp 126 lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) 127 ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) 128 129 /* Obtain a store of registers for the current task. */ 130 131 la $k1, current_registers 132 lw $k1, 0($k1) 133 134 /* Save registers that the assembler wants to trash. */ 135 136 sw $t9, 100($k1) 137 sw $k0, 104($k1) /* old gp */ 138 sw $ra, 112($k1) 139 140 /* Record the stack pointer. */ 141 142 la $k1, current_stack_pointer 143 lw $k1, 0($k1) /* &stack_pointers[current_task] */ 144 sw $sp, 0($k1) 145 146 /* Switch to the kernel stack. */ 147 148 li $sp, 0x80070000 149 150 /* Invoke the rest of the interrupt handling process. */ 151 152 la $k0, interrupt_handler 153 jr $k0 154 nop 155 156 _end_entries: 157 158 .set reorder