1 /* 2 * Include file for Ingenic Semiconductor's JZ4740 CPU. 3 * 4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. 5 * Copyright (C) 2009 Qi Hardware Inc. 6 * Author: Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 #ifndef __JZ4740_H__ 25 #define __JZ4740_H__ 26 27 #include "xburst_types.h" 28 29 /* NOTE: Independent of usbboot parameters. */ 30 31 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ 32 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ 33 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ 34 35 #define JZ_EXTAL CONFIG_SYS_EXTAL 36 #define JZ_EXTAL2 32768 /* RTC clock */ 37 38 /* Boot ROM Specification */ 39 /* NOR Boot config */ 40 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ 41 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ 42 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ 43 44 /* NAND Boot config */ 45 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ 46 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ 47 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ 48 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ 49 50 51 /* Register Definitions */ 52 #define CPM_BASE 0xB0000000 53 #define INTC_BASE 0xB0001000 54 #define TCU_BASE 0xB0002000 55 #define WDT_BASE 0xB0002000 56 #define RTC_BASE 0xB0003000 57 #define GPIO_BASE 0xB0010000 58 #define AIC_BASE 0xB0020000 59 #define ICDC_BASE 0xB0020000 60 #define MSC_BASE 0xB0021000 61 #define UART0_BASE 0xB0030000 62 #define I2C_BASE 0xB0042000 63 #define SSI_BASE 0xB0043000 64 #define SADC_BASE 0xB0070000 65 #define EMC_BASE 0xB3010000 66 #define DMAC_BASE 0xB3020000 67 #define UHC_BASE 0xB3030000 68 #define UDC_BASE 0xB3040000 69 #define LCD_BASE 0xB3050000 70 #define SLCD_BASE 0xB3050000 71 #define CIM_BASE 0xB3060000 72 #define ETH_BASE 0xB3100000 73 74 75 /* 76 * INTC (Interrupt Controller) 77 */ 78 #define INTC_ISR (INTC_BASE + 0x00) 79 #define INTC_IMR (INTC_BASE + 0x04) 80 #define INTC_IMSR (INTC_BASE + 0x08) 81 #define INTC_IMCR (INTC_BASE + 0x0c) 82 #define INTC_IPR (INTC_BASE + 0x10) 83 84 #define REG_INTC_ISR REG32(INTC_ISR) 85 #define REG_INTC_IMR REG32(INTC_IMR) 86 #define REG_INTC_IMSR REG32(INTC_IMSR) 87 #define REG_INTC_IMCR REG32(INTC_IMCR) 88 #define REG_INTC_IPR REG32(INTC_IPR) 89 90 /* 1st-level interrupts */ 91 #define IRQ_I2C 1 92 #define IRQ_UHC 3 93 #define IRQ_UART0 9 94 #define IRQ_SADC 12 95 #define IRQ_MSC 14 96 #define IRQ_RTC 15 97 #define IRQ_SSI 16 98 #define IRQ_CIM 17 99 #define IRQ_AIC 18 100 #define IRQ_ETH 19 101 #define IRQ_DMAC 20 102 #define IRQ_TCU2 21 103 #define IRQ_TCU1 22 104 #define IRQ_TCU0 23 105 #define IRQ_UDC 24 106 #define IRQ_GPIO3 25 107 #define IRQ_GPIO2 26 108 #define IRQ_GPIO1 27 109 #define IRQ_GPIO0 28 110 #define IRQ_IPU 29 111 #define IRQ_LCD 30 112 113 /* 2nd-level interrupts */ 114 #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ 115 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ 116 117 118 /* 119 * RTC 120 */ 121 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ 122 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ 123 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ 124 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ 125 126 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ 127 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ 128 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ 129 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ 130 #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ 131 #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ 132 133 #define REG_RTC_RCR REG32(RTC_RCR) 134 #define REG_RTC_RSR REG32(RTC_RSR) 135 #define REG_RTC_RSAR REG32(RTC_RSAR) 136 #define REG_RTC_RGR REG32(RTC_RGR) 137 #define REG_RTC_HCR REG32(RTC_HCR) 138 #define REG_RTC_HWFCR REG32(RTC_HWFCR) 139 #define REG_RTC_HRCR REG32(RTC_HRCR) 140 #define REG_RTC_HWCR REG32(RTC_HWCR) 141 #define REG_RTC_HWRSR REG32(RTC_HWRSR) 142 #define REG_RTC_HSPR REG32(RTC_HSPR) 143 144 /* RTC Control Register */ 145 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ 146 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ 147 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ 148 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */ 149 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ 150 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ 151 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ 152 153 /* RTC Regulator Register */ 154 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ 155 #define RTC_RGR_ADJC_BIT 16 156 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) 157 #define RTC_RGR_NC1HZ_BIT 0 158 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) 159 160 /* Hibernate Control Register */ 161 #define RTC_HCR_PD (1 << 0) /* Power Down */ 162 163 /* Hibernate Wakeup Filter Counter Register */ 164 #define RTC_HWFCR_BIT 5 165 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) 166 167 /* Hibernate Reset Counter Register */ 168 #define RTC_HRCR_BIT 5 169 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) 170 171 /* Hibernate Wakeup Control Register */ 172 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ 173 174 /* Hibernate Wakeup Status Register */ 175 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ 176 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ 177 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ 178 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ 179 180 /************************************************************************* 181 * CPM (Clock reset and Power control Management) 182 *************************************************************************/ 183 184 /* Register definitions with absolute positioning have been removed. */ 185 186 /* Clock Control Register */ 187 #define CPM_CPCCR_I2CS (1 << 31) 188 #define CPM_CPCCR_CLKOEN (1 << 30) 189 #define CPM_CPCCR_UCS (1 << 29) 190 #define CPM_CPCCR_UDIV_BIT 23 191 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) 192 #define CPM_CPCCR_CE (1 << 22) 193 #define CPM_CPCCR_PCS (1 << 21) 194 #define CPM_CPCCR_LDIV_BIT 16 195 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) 196 #define CPM_CPCCR_MDIV_BIT 12 197 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) 198 #define CPM_CPCCR_PDIV_BIT 8 199 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) 200 #define CPM_CPCCR_HDIV_BIT 4 201 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) 202 #define CPM_CPCCR_CDIV_BIT 0 203 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) 204 205 /* I2S Clock Divider Register */ 206 #define CPM_I2SCDR_I2SDIV_BIT 0 207 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) 208 209 /* LCD Pixel Clock Divider Register */ 210 #define CPM_LPCDR_PIXDIV_BIT 0 211 #define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT) 212 213 /* MSC Clock Divider Register */ 214 #define CPM_MSCCDR_MSCDIV_BIT 0 215 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) 216 217 /* PLL Control Register */ 218 #define CPM_CPPCR_PLLM_BIT 23 219 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) 220 #define CPM_CPPCR_PLLN_BIT 18 221 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) 222 #define CPM_CPPCR_PLLOD_BIT 16 223 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) 224 #define CPM_CPPCR_PLLS (1 << 10) 225 #define CPM_CPPCR_PLLBP (1 << 9) 226 #define CPM_CPPCR_PLLEN (1 << 8) 227 #define CPM_CPPCR_PLLST_BIT 0 228 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) 229 230 /* Low Power Control Register */ 231 #define CPM_LCR_DOZE_DUTY_BIT 3 232 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) 233 #define CPM_LCR_DOZE_ON (1 << 2) 234 #define CPM_LCR_LPM_BIT 0 235 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) 236 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) 237 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) 238 239 /* Clock Gate Register */ 240 #define CPM_CLKGR_UART1 (1 << 15) 241 #define CPM_CLKGR_UHC (1 << 14) 242 #define CPM_CLKGR_IPU (1 << 13) 243 #define CPM_CLKGR_DMAC (1 << 12) 244 #define CPM_CLKGR_UDC (1 << 11) 245 #define CPM_CLKGR_LCD (1 << 10) 246 #define CPM_CLKGR_CIM (1 << 9) 247 #define CPM_CLKGR_SADC (1 << 8) 248 #define CPM_CLKGR_MSC (1 << 7) 249 #define CPM_CLKGR_AIC1 (1 << 6) 250 #define CPM_CLKGR_AIC2 (1 << 5) 251 #define CPM_CLKGR_SSI (1 << 4) 252 #define CPM_CLKGR_I2C (1 << 3) 253 #define CPM_CLKGR_RTC (1 << 2) 254 #define CPM_CLKGR_TCU (1 << 1) 255 #define CPM_CLKGR_UART0 (1 << 0) 256 257 /* Sleep Control Register */ 258 #define CPM_SCR_O1ST_BIT 8 259 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) 260 #define CPM_SCR_UDCPHY_ENABLE (1 << 6) 261 #define CPM_SCR_USBPHY_DISABLE (1 << 7) 262 #define CPM_SCR_OSC_ENABLE (1 << 4) 263 264 /* Hibernate Control Register */ 265 #define CPM_HCR_PD (1 << 0) 266 267 /* Wakeup Filter Counter Register in Hibernate Mode */ 268 #define CPM_HWFCR_TIME_BIT 0 269 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) 270 271 /* Reset Counter Register in Hibernate Mode */ 272 #define CPM_HRCR_TIME_BIT 0 273 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) 274 275 /* Wakeup Control Register in Hibernate Mode */ 276 #define CPM_HWCR_WLE_LOW (0 << 2) 277 #define CPM_HWCR_WLE_HIGH (1 << 2) 278 #define CPM_HWCR_PIN_WAKEUP (1 << 1) 279 #define CPM_HWCR_RTC_WAKEUP (1 << 0) 280 281 /* Wakeup Status Register in Hibernate Mode */ 282 #define CPM_HWSR_WSR_PIN (1 << 1) 283 #define CPM_HWSR_WSR_RTC (1 << 0) 284 285 /* Reset Status Register */ 286 #define CPM_RSR_HR (1 << 2) 287 #define CPM_RSR_WR (1 << 1) 288 #define CPM_RSR_PR (1 << 0) 289 290 291 /************************************************************************* 292 * TCU (Timer Counter Unit) 293 *************************************************************************/ 294 #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ 295 #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ 296 #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ 297 #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ 298 #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ 299 #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ 300 #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ 301 #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ 302 #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ 303 #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ 304 #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ 305 #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ 306 #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ 307 #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ 308 #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ 309 #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ 310 #define TCU_TDFR1 (TCU_BASE + 0x50) 311 #define TCU_TDHR1 (TCU_BASE + 0x54) 312 #define TCU_TCNT1 (TCU_BASE + 0x58) 313 #define TCU_TCSR1 (TCU_BASE + 0x5C) 314 #define TCU_TDFR2 (TCU_BASE + 0x60) 315 #define TCU_TDHR2 (TCU_BASE + 0x64) 316 #define TCU_TCNT2 (TCU_BASE + 0x68) 317 #define TCU_TCSR2 (TCU_BASE + 0x6C) 318 #define TCU_TDFR3 (TCU_BASE + 0x70) 319 #define TCU_TDHR3 (TCU_BASE + 0x74) 320 #define TCU_TCNT3 (TCU_BASE + 0x78) 321 #define TCU_TCSR3 (TCU_BASE + 0x7C) 322 #define TCU_TDFR4 (TCU_BASE + 0x80) 323 #define TCU_TDHR4 (TCU_BASE + 0x84) 324 #define TCU_TCNT4 (TCU_BASE + 0x88) 325 #define TCU_TCSR4 (TCU_BASE + 0x8C) 326 #define TCU_TDFR5 (TCU_BASE + 0x90) 327 #define TCU_TDHR5 (TCU_BASE + 0x94) 328 #define TCU_TCNT5 (TCU_BASE + 0x98) 329 #define TCU_TCSR5 (TCU_BASE + 0x9C) 330 331 #define REG_TCU_TSR REG32(TCU_TSR) 332 #define REG_TCU_TSSR REG32(TCU_TSSR) 333 #define REG_TCU_TSCR REG32(TCU_TSCR) 334 #define REG_TCU_TER REG8(TCU_TER) 335 #define REG_TCU_TESR REG8(TCU_TESR) 336 #define REG_TCU_TECR REG8(TCU_TECR) 337 #define REG_TCU_TFR REG32(TCU_TFR) 338 #define REG_TCU_TFSR REG32(TCU_TFSR) 339 #define REG_TCU_TFCR REG32(TCU_TFCR) 340 #define REG_TCU_TMR REG32(TCU_TMR) 341 #define REG_TCU_TMSR REG32(TCU_TMSR) 342 #define REG_TCU_TMCR REG32(TCU_TMCR) 343 #define REG_TCU_TDFR0 REG16(TCU_TDFR0) 344 #define REG_TCU_TDHR0 REG16(TCU_TDHR0) 345 #define REG_TCU_TCNT0 REG16(TCU_TCNT0) 346 #define REG_TCU_TCSR0 REG16(TCU_TCSR0) 347 #define REG_TCU_TDFR1 REG16(TCU_TDFR1) 348 #define REG_TCU_TDHR1 REG16(TCU_TDHR1) 349 #define REG_TCU_TCNT1 REG16(TCU_TCNT1) 350 #define REG_TCU_TCSR1 REG16(TCU_TCSR1) 351 #define REG_TCU_TDFR2 REG16(TCU_TDFR2) 352 #define REG_TCU_TDHR2 REG16(TCU_TDHR2) 353 #define REG_TCU_TCNT2 REG16(TCU_TCNT2) 354 #define REG_TCU_TCSR2 REG16(TCU_TCSR2) 355 #define REG_TCU_TDFR3 REG16(TCU_TDFR3) 356 #define REG_TCU_TDHR3 REG16(TCU_TDHR3) 357 #define REG_TCU_TCNT3 REG16(TCU_TCNT3) 358 #define REG_TCU_TCSR3 REG16(TCU_TCSR3) 359 #define REG_TCU_TDFR4 REG16(TCU_TDFR4) 360 #define REG_TCU_TDHR4 REG16(TCU_TDHR4) 361 #define REG_TCU_TCNT4 REG16(TCU_TCNT4) 362 #define REG_TCU_TCSR4 REG16(TCU_TCSR4) 363 364 /* n = 0,1,2,3,4,5 */ 365 #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ 366 #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ 367 #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ 368 #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ 369 370 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) 371 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) 372 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) 373 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) 374 375 /* Register definitions */ 376 #define TCU_TCSR_PWM_SD (1 << 9) 377 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) 378 #define TCU_TCSR_PWM_EN (1 << 7) 379 #define TCU_TCSR_PRESCALE_BIT 3 380 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) 381 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) 382 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) 383 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) 384 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) 385 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) 386 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) 387 #define TCU_TCSR_EXT_EN (1 << 2) 388 #define TCU_TCSR_RTC_EN (1 << 1) 389 #define TCU_TCSR_PCK_EN (1 << 0) 390 391 #define TCU_TER_TCEN5 (1 << 5) 392 #define TCU_TER_TCEN4 (1 << 4) 393 #define TCU_TER_TCEN3 (1 << 3) 394 #define TCU_TER_TCEN2 (1 << 2) 395 #define TCU_TER_TCEN1 (1 << 1) 396 #define TCU_TER_TCEN0 (1 << 0) 397 398 #define TCU_TESR_TCST5 (1 << 5) 399 #define TCU_TESR_TCST4 (1 << 4) 400 #define TCU_TESR_TCST3 (1 << 3) 401 #define TCU_TESR_TCST2 (1 << 2) 402 #define TCU_TESR_TCST1 (1 << 1) 403 #define TCU_TESR_TCST0 (1 << 0) 404 405 #define TCU_TECR_TCCL5 (1 << 5) 406 #define TCU_TECR_TCCL4 (1 << 4) 407 #define TCU_TECR_TCCL3 (1 << 3) 408 #define TCU_TECR_TCCL2 (1 << 2) 409 #define TCU_TECR_TCCL1 (1 << 1) 410 #define TCU_TECR_TCCL0 (1 << 0) 411 412 #define TCU_TFR_HFLAG5 (1 << 21) 413 #define TCU_TFR_HFLAG4 (1 << 20) 414 #define TCU_TFR_HFLAG3 (1 << 19) 415 #define TCU_TFR_HFLAG2 (1 << 18) 416 #define TCU_TFR_HFLAG1 (1 << 17) 417 #define TCU_TFR_HFLAG0 (1 << 16) 418 #define TCU_TFR_FFLAG5 (1 << 5) 419 #define TCU_TFR_FFLAG4 (1 << 4) 420 #define TCU_TFR_FFLAG3 (1 << 3) 421 #define TCU_TFR_FFLAG2 (1 << 2) 422 #define TCU_TFR_FFLAG1 (1 << 1) 423 #define TCU_TFR_FFLAG0 (1 << 0) 424 425 #define TCU_TFSR_HFLAG5 (1 << 21) 426 #define TCU_TFSR_HFLAG4 (1 << 20) 427 #define TCU_TFSR_HFLAG3 (1 << 19) 428 #define TCU_TFSR_HFLAG2 (1 << 18) 429 #define TCU_TFSR_HFLAG1 (1 << 17) 430 #define TCU_TFSR_HFLAG0 (1 << 16) 431 #define TCU_TFSR_FFLAG5 (1 << 5) 432 #define TCU_TFSR_FFLAG4 (1 << 4) 433 #define TCU_TFSR_FFLAG3 (1 << 3) 434 #define TCU_TFSR_FFLAG2 (1 << 2) 435 #define TCU_TFSR_FFLAG1 (1 << 1) 436 #define TCU_TFSR_FFLAG0 (1 << 0) 437 438 #define TCU_TFCR_HFLAG5 (1 << 21) 439 #define TCU_TFCR_HFLAG4 (1 << 20) 440 #define TCU_TFCR_HFLAG3 (1 << 19) 441 #define TCU_TFCR_HFLAG2 (1 << 18) 442 #define TCU_TFCR_HFLAG1 (1 << 17) 443 #define TCU_TFCR_HFLAG0 (1 << 16) 444 #define TCU_TFCR_FFLAG5 (1 << 5) 445 #define TCU_TFCR_FFLAG4 (1 << 4) 446 #define TCU_TFCR_FFLAG3 (1 << 3) 447 #define TCU_TFCR_FFLAG2 (1 << 2) 448 #define TCU_TFCR_FFLAG1 (1 << 1) 449 #define TCU_TFCR_FFLAG0 (1 << 0) 450 451 #define TCU_TMR_HMASK5 (1 << 21) 452 #define TCU_TMR_HMASK4 (1 << 20) 453 #define TCU_TMR_HMASK3 (1 << 19) 454 #define TCU_TMR_HMASK2 (1 << 18) 455 #define TCU_TMR_HMASK1 (1 << 17) 456 #define TCU_TMR_HMASK0 (1 << 16) 457 #define TCU_TMR_FMASK5 (1 << 5) 458 #define TCU_TMR_FMASK4 (1 << 4) 459 #define TCU_TMR_FMASK3 (1 << 3) 460 #define TCU_TMR_FMASK2 (1 << 2) 461 #define TCU_TMR_FMASK1 (1 << 1) 462 #define TCU_TMR_FMASK0 (1 << 0) 463 464 #define TCU_TMSR_HMST5 (1 << 21) 465 #define TCU_TMSR_HMST4 (1 << 20) 466 #define TCU_TMSR_HMST3 (1 << 19) 467 #define TCU_TMSR_HMST2 (1 << 18) 468 #define TCU_TMSR_HMST1 (1 << 17) 469 #define TCU_TMSR_HMST0 (1 << 16) 470 #define TCU_TMSR_FMST5 (1 << 5) 471 #define TCU_TMSR_FMST4 (1 << 4) 472 #define TCU_TMSR_FMST3 (1 << 3) 473 #define TCU_TMSR_FMST2 (1 << 2) 474 #define TCU_TMSR_FMST1 (1 << 1) 475 #define TCU_TMSR_FMST0 (1 << 0) 476 477 #define TCU_TMCR_HMCL5 (1 << 21) 478 #define TCU_TMCR_HMCL4 (1 << 20) 479 #define TCU_TMCR_HMCL3 (1 << 19) 480 #define TCU_TMCR_HMCL2 (1 << 18) 481 #define TCU_TMCR_HMCL1 (1 << 17) 482 #define TCU_TMCR_HMCL0 (1 << 16) 483 #define TCU_TMCR_FMCL5 (1 << 5) 484 #define TCU_TMCR_FMCL4 (1 << 4) 485 #define TCU_TMCR_FMCL3 (1 << 3) 486 #define TCU_TMCR_FMCL2 (1 << 2) 487 #define TCU_TMCR_FMCL1 (1 << 1) 488 #define TCU_TMCR_FMCL0 (1 << 0) 489 490 #define TCU_TSR_WDTS (1 << 16) 491 #define TCU_TSR_STOP5 (1 << 5) 492 #define TCU_TSR_STOP4 (1 << 4) 493 #define TCU_TSR_STOP3 (1 << 3) 494 #define TCU_TSR_STOP2 (1 << 2) 495 #define TCU_TSR_STOP1 (1 << 1) 496 #define TCU_TSR_STOP0 (1 << 0) 497 498 #define TCU_TSSR_WDTSS (1 << 16) 499 #define TCU_TSSR_STPS5 (1 << 5) 500 #define TCU_TSSR_STPS4 (1 << 4) 501 #define TCU_TSSR_STPS3 (1 << 3) 502 #define TCU_TSSR_STPS2 (1 << 2) 503 #define TCU_TSSR_STPS1 (1 << 1) 504 #define TCU_TSSR_STPS0 (1 << 0) 505 506 #define TCU_TSSR_WDTSC (1 << 16) 507 #define TCU_TSSR_STPC5 (1 << 5) 508 #define TCU_TSSR_STPC4 (1 << 4) 509 #define TCU_TSSR_STPC3 (1 << 3) 510 #define TCU_TSSR_STPC2 (1 << 2) 511 #define TCU_TSSR_STPC1 (1 << 1) 512 #define TCU_TSSR_STPC0 (1 << 0) 513 514 515 /* 516 * WDT (WatchDog Timer) 517 */ 518 #define WDT_TDR (WDT_BASE + 0x00) 519 #define WDT_TCER (WDT_BASE + 0x04) 520 #define WDT_TCNT (WDT_BASE + 0x08) 521 #define WDT_TCSR (WDT_BASE + 0x0C) 522 523 #define REG_WDT_TDR REG16(WDT_TDR) 524 #define REG_WDT_TCER REG8(WDT_TCER) 525 #define REG_WDT_TCNT REG16(WDT_TCNT) 526 #define REG_WDT_TCSR REG16(WDT_TCSR) 527 528 /* Register definition */ 529 #define WDT_TCSR_PRESCALE_BIT 3 530 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) 531 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) 532 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) 533 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) 534 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) 535 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) 536 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) 537 #define WDT_TCSR_EXT_EN (1 << 2) 538 #define WDT_TCSR_RTC_EN (1 << 1) 539 #define WDT_TCSR_PCK_EN (1 << 0) 540 541 #define WDT_TCER_TCEN (1 << 0) 542 543 544 /* 545 * DMAC (DMA Controller) 546 */ 547 548 #define MAX_DMA_NUM 6 /* max 6 channels */ 549 550 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ 551 #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ 552 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ 553 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ 554 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ 555 #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ 556 #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ 557 #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ 558 #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ 559 #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ 560 #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ 561 562 /* channel 0 */ 563 #define DMAC_DSAR0 DMAC_DSAR(0) 564 #define DMAC_DTAR0 DMAC_DTAR(0) 565 #define DMAC_DTCR0 DMAC_DTCR(0) 566 #define DMAC_DRSR0 DMAC_DRSR(0) 567 #define DMAC_DCCSR0 DMAC_DCCSR(0) 568 #define DMAC_DCMD0 DMAC_DCMD(0) 569 #define DMAC_DDA0 DMAC_DDA(0) 570 571 /* channel 1 */ 572 #define DMAC_DSAR1 DMAC_DSAR(1) 573 #define DMAC_DTAR1 DMAC_DTAR(1) 574 #define DMAC_DTCR1 DMAC_DTCR(1) 575 #define DMAC_DRSR1 DMAC_DRSR(1) 576 #define DMAC_DCCSR1 DMAC_DCCSR(1) 577 #define DMAC_DCMD1 DMAC_DCMD(1) 578 #define DMAC_DDA1 DMAC_DDA(1) 579 580 /* channel 2 */ 581 #define DMAC_DSAR2 DMAC_DSAR(2) 582 #define DMAC_DTAR2 DMAC_DTAR(2) 583 #define DMAC_DTCR2 DMAC_DTCR(2) 584 #define DMAC_DRSR2 DMAC_DRSR(2) 585 #define DMAC_DCCSR2 DMAC_DCCSR(2) 586 #define DMAC_DCMD2 DMAC_DCMD(2) 587 #define DMAC_DDA2 DMAC_DDA(2) 588 589 /* channel 3 */ 590 #define DMAC_DSAR3 DMAC_DSAR(3) 591 #define DMAC_DTAR3 DMAC_DTAR(3) 592 #define DMAC_DTCR3 DMAC_DTCR(3) 593 #define DMAC_DRSR3 DMAC_DRSR(3) 594 #define DMAC_DCCSR3 DMAC_DCCSR(3) 595 #define DMAC_DCMD3 DMAC_DCMD(3) 596 #define DMAC_DDA3 DMAC_DDA(3) 597 598 /* channel 4 */ 599 #define DMAC_DSAR4 DMAC_DSAR(4) 600 #define DMAC_DTAR4 DMAC_DTAR(4) 601 #define DMAC_DTCR4 DMAC_DTCR(4) 602 #define DMAC_DRSR4 DMAC_DRSR(4) 603 #define DMAC_DCCSR4 DMAC_DCCSR(4) 604 #define DMAC_DCMD4 DMAC_DCMD(4) 605 #define DMAC_DDA4 DMAC_DDA(4) 606 607 /* channel 5 */ 608 #define DMAC_DSAR5 DMAC_DSAR(5) 609 #define DMAC_DTAR5 DMAC_DTAR(5) 610 #define DMAC_DTCR5 DMAC_DTCR(5) 611 #define DMAC_DRSR5 DMAC_DRSR(5) 612 #define DMAC_DCCSR5 DMAC_DCCSR(5) 613 #define DMAC_DCMD5 DMAC_DCMD(5) 614 #define DMAC_DDA5 DMAC_DDA(5) 615 616 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) 617 #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) 618 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) 619 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) 620 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) 621 #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) 622 #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) 623 #define REG_DMAC_DMACR REG32(DMAC_DMACR) 624 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) 625 #define REG_DMAC_DMADBR REG32(DMAC_DMADBR) 626 #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) 627 628 /* DMA request source register */ 629 #define DMAC_DRSR_RS_BIT 0 630 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) 631 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) 632 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) 633 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) 634 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) 635 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) 636 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) 637 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) 638 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) 639 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) 640 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) 641 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) 642 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) 643 644 /* DMA channel control/status register */ 645 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ 646 #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ 647 #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) 648 #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ 649 #define DMAC_DCCSR_AR (1 << 4) /* address error */ 650 #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ 651 #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ 652 #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ 653 #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ 654 655 /* DMA channel command register */ 656 #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ 657 #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ 658 #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ 659 #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) 660 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) 661 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) 662 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) 663 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) 664 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) 665 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) 666 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) 667 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) 668 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) 669 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) 670 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) 671 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) 672 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) 673 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) 674 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) 675 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) 676 #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ 677 #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) 678 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) 679 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) 680 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) 681 #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ 682 #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) 683 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) 684 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) 685 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) 686 #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ 687 #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) 688 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) 689 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) 690 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) 691 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) 692 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) 693 #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ 694 #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ 695 #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ 696 #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ 697 #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ 698 #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ 699 700 /* DMA descriptor address register */ 701 #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ 702 #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) 703 #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ 704 #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) 705 706 /* DMA control register */ 707 #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ 708 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) 709 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) 710 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) 711 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) 712 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ 713 #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ 714 #define DMAC_DMACR_AR (1 << 2) /* address error flag */ 715 #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ 716 717 /* DMA doorbell register */ 718 #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ 719 #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ 720 #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ 721 #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ 722 #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ 723 #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ 724 725 /* DMA doorbell set register */ 726 #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ 727 #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ 728 #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ 729 #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ 730 #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ 731 #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ 732 733 /* DMA interrupt pending register */ 734 #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ 735 #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ 736 #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ 737 #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ 738 #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ 739 #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ 740 741 742 /************************************************************************* 743 * GPIO (General-Purpose I/O Ports) 744 *************************************************************************/ 745 #define MAX_GPIO_NUM 128 746 747 /* = 0,1,2,3 */ 748 #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ 749 #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ 750 #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ 751 #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ 752 #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ 753 #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ 754 #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ 755 #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ 756 #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ 757 #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ 758 #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ 759 #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ 760 #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ 761 #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ 762 #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ 763 #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ 764 #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ 765 #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ 766 #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ 767 #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ 768 #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ 769 #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ 770 #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ 771 #define GPIO_PXFLGC(n) (GPIO_BASE + (0x84 + (n)*0x100)) /* Port Flag clear Register */ 772 773 #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ 774 #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ 775 #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) 776 #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) 777 #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ 778 #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) 779 #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) 780 #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ 781 #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) 782 #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) 783 #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ 784 #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) 785 #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) 786 #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ 787 #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) 788 #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) 789 #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ 790 #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) 791 #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) 792 #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ 793 #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) 794 #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) 795 #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ 796 #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ 797 798 799 /************************************************************************* 800 * UART 801 *************************************************************************/ 802 803 #define IRDA_BASE UART0_BASE 804 /* #define UART_BASE UART0_BASE */ 805 #define UART_OFF 0x1000 806 807 /* Register Offset */ 808 #define OFF_RDR (0x00) /* R 8b H'xx */ 809 #define OFF_TDR (0x00) /* W 8b H'xx */ 810 #define OFF_DLLR (0x00) /* RW 8b H'00 */ 811 #define OFF_DLHR (0x04) /* RW 8b H'00 */ 812 #define OFF_IER (0x04) /* RW 8b H'00 */ 813 #define OFF_ISR (0x08) /* R 8b H'01 */ 814 #define OFF_FCR (0x08) /* W 8b H'00 */ 815 #define OFF_LCR (0x0C) /* RW 8b H'00 */ 816 #define OFF_MCR (0x10) /* RW 8b H'00 */ 817 #define OFF_LSR (0x14) /* R 8b H'00 */ 818 #define OFF_MSR (0x18) /* R 8b H'00 */ 819 #define OFF_SPR (0x1C) /* RW 8b H'00 */ 820 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ 821 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ 822 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ 823 824 /* Register Address */ 825 #define UART0_RDR (UART0_BASE + OFF_RDR) 826 #define UART0_TDR (UART0_BASE + OFF_TDR) 827 #define UART0_DLLR (UART0_BASE + OFF_DLLR) 828 #define UART0_DLHR (UART0_BASE + OFF_DLHR) 829 #define UART0_IER (UART0_BASE + OFF_IER) 830 #define UART0_ISR (UART0_BASE + OFF_ISR) 831 #define UART0_FCR (UART0_BASE + OFF_FCR) 832 #define UART0_LCR (UART0_BASE + OFF_LCR) 833 #define UART0_MCR (UART0_BASE + OFF_MCR) 834 #define UART0_LSR (UART0_BASE + OFF_LSR) 835 #define UART0_MSR (UART0_BASE + OFF_MSR) 836 #define UART0_SPR (UART0_BASE + OFF_SPR) 837 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) 838 #define UART0_UMR (UART0_BASE + OFF_UMR) 839 #define UART0_UACR (UART0_BASE + OFF_UACR) 840 841 /* 842 * Define macros for UART_IER 843 * UART Interrupt Enable Register 844 */ 845 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ 846 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ 847 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ 848 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ 849 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ 850 851 /* 852 * Define macros for UART_ISR 853 * UART Interrupt Status Register 854 */ 855 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ 856 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ 857 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ 858 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ 859 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ 860 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ 861 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ 862 #define UART_ISR_FFMS_NO_FIFO (0 << 6) 863 #define UART_ISR_FFMS_FIFO_MODE (3 << 6) 864 865 /* 866 * Define macros for UART_FCR 867 * UART FIFO Control Register 868 */ 869 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ 870 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ 871 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ 872 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ 873 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ 874 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ 875 #define UART_FCR_RTRG_1 (0 << 6) 876 #define UART_FCR_RTRG_4 (1 << 6) 877 #define UART_FCR_RTRG_8 (2 << 6) 878 #define UART_FCR_RTRG_15 (3 << 6) 879 880 /* 881 * Define macros for UART_LCR 882 * UART Line Control Register 883 */ 884 #define UART_LCR_WLEN (3 << 0) /* word length */ 885 #define UART_LCR_WLEN_5 (0 << 0) 886 #define UART_LCR_WLEN_6 (1 << 0) 887 #define UART_LCR_WLEN_7 (2 << 0) 888 #define UART_LCR_WLEN_8 (3 << 0) 889 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 890 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 891 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 892 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 893 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 894 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 895 896 #define UART_LCR_PE (1 << 3) /* 0: parity disable */ 897 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ 898 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ 899 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ 900 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ 901 902 /* 903 * Define macros for UART_LSR 904 * UART Line Status Register 905 */ 906 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ 907 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ 908 #define UART_LSR_PER (1 << 2) /* 0: no parity error */ 909 #define UART_LSR_FER (1 << 3) /* 0; no framing error */ 910 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ 911 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ 912 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ 913 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ 914 915 /* 916 * Define macros for UART_MCR 917 * UART Modem Control Register 918 */ 919 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ 920 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ 921 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ 922 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ 923 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ 924 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ 925 926 /* 927 * Define macros for UART_MSR 928 * UART Modem Status Register 929 */ 930 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ 931 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ 932 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ 933 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ 934 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ 935 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ 936 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ 937 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ 938 939 /* 940 * Define macros for SIRCR 941 * Slow IrDA Control Register 942 */ 943 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ 944 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ 945 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length 946 1: 0 pulse width is 1.6us for 115.2Kbps */ 947 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ 948 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ 949 950 951 /************************************************************************* 952 * AIC (AC97/I2S Controller) 953 *************************************************************************/ 954 #define AIC_FR (AIC_BASE + 0x000) 955 #define AIC_CR (AIC_BASE + 0x004) 956 #define AIC_ACCR1 (AIC_BASE + 0x008) 957 #define AIC_ACCR2 (AIC_BASE + 0x00C) 958 #define AIC_I2SCR (AIC_BASE + 0x010) 959 #define AIC_SR (AIC_BASE + 0x014) 960 #define AIC_ACSR (AIC_BASE + 0x018) 961 #define AIC_I2SSR (AIC_BASE + 0x01C) 962 #define AIC_ACCAR (AIC_BASE + 0x020) 963 #define AIC_ACCDR (AIC_BASE + 0x024) 964 #define AIC_ACSAR (AIC_BASE + 0x028) 965 #define AIC_ACSDR (AIC_BASE + 0x02C) 966 #define AIC_I2SDIV (AIC_BASE + 0x030) 967 #define AIC_DR (AIC_BASE + 0x034) 968 969 #define REG_AIC_FR REG32(AIC_FR) 970 #define REG_AIC_CR REG32(AIC_CR) 971 #define REG_AIC_ACCR1 REG32(AIC_ACCR1) 972 #define REG_AIC_ACCR2 REG32(AIC_ACCR2) 973 #define REG_AIC_I2SCR REG32(AIC_I2SCR) 974 #define REG_AIC_SR REG32(AIC_SR) 975 #define REG_AIC_ACSR REG32(AIC_ACSR) 976 #define REG_AIC_I2SSR REG32(AIC_I2SSR) 977 #define REG_AIC_ACCAR REG32(AIC_ACCAR) 978 #define REG_AIC_ACCDR REG32(AIC_ACCDR) 979 #define REG_AIC_ACSAR REG32(AIC_ACSAR) 980 #define REG_AIC_ACSDR REG32(AIC_ACSDR) 981 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 982 #define REG_AIC_DR REG32(AIC_DR) 983 984 /* AIC Controller Configuration Register (AIC_FR) */ 985 986 #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ 987 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) 988 #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ 989 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) 990 #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ 991 #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ 992 #define AIC_FR_RST (1 << 3) /* AIC registers reset */ 993 #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ 994 #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ 995 #define AIC_FR_ENB (1 << 0) /* AIC enable bit */ 996 997 /* AIC Controller Common Control Register (AIC_CR) */ 998 999 #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ 1000 #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) 1001 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) 1002 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) 1003 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) 1004 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) 1005 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) 1006 #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ 1007 #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) 1008 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) 1009 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) 1010 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) 1011 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) 1012 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) 1013 #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ 1014 #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ 1015 #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ 1016 #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ 1017 #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ 1018 #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ 1019 #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ 1020 #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ 1021 #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ 1022 #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ 1023 #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ 1024 #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ 1025 #define AIC_CR_EREC (1 << 0) /* Enable Record Function */ 1026 1027 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ 1028 1029 #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ 1030 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) 1031 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ 1032 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ 1033 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ 1034 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ 1035 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ 1036 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ 1037 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ 1038 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ 1039 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ 1040 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ 1041 #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ 1042 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) 1043 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ 1044 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ 1045 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ 1046 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ 1047 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ 1048 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ 1049 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ 1050 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ 1051 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ 1052 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ 1053 1054 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ 1055 1056 #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ 1057 #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ 1058 #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ 1059 #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ 1060 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) 1061 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ 1062 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ 1063 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ 1064 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ 1065 #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ 1066 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) 1067 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ 1068 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ 1069 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ 1070 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ 1071 #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ 1072 #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ 1073 #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ 1074 #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ 1075 1076 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ 1077 1078 #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ 1079 #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ 1080 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) 1081 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ 1082 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ 1083 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ 1084 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ 1085 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ 1086 #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ 1087 1088 /* AIC Controller FIFO Status Register (AIC_SR) */ 1089 1090 #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ 1091 #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) 1092 #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ 1093 #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) 1094 #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ 1095 #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ 1096 #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ 1097 #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ 1098 1099 /* AIC Controller AC-link Status Register (AIC_ACSR) */ 1100 1101 #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ 1102 #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ 1103 #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ 1104 #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ 1105 #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ 1106 #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ 1107 1108 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ 1109 1110 #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ 1111 1112 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ 1113 1114 #define AIC_ACCAR_CAR_BIT 0 1115 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) 1116 1117 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ 1118 1119 #define AIC_ACCDR_CDR_BIT 0 1120 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) 1121 1122 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ 1123 1124 #define AIC_ACSAR_SAR_BIT 0 1125 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) 1126 1127 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ 1128 1129 #define AIC_ACSDR_SDR_BIT 0 1130 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) 1131 1132 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ 1133 1134 #define AIC_I2SDIV_DIV_BIT 0 1135 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) 1136 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ 1137 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ 1138 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ 1139 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ 1140 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ 1141 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ 1142 1143 1144 /************************************************************************* 1145 * ICDC (Internal CODEC) 1146 *************************************************************************/ 1147 #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ 1148 #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ 1149 #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1150 #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ 1151 #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ 1152 #define ICDC_CDCCR1 (ICDC_BASE + 0x0080) 1153 #define ICDC_CDCCR2 (ICDC_BASE + 0x0084) 1154 1155 #define REG_ICDC_CR REG32(ICDC_CR) 1156 #define REG_ICDC_APWAIT REG32(ICDC_APWAIT) 1157 #define REG_ICDC_APPRE REG32(ICDC_APPRE) 1158 #define REG_ICDC_APHPEN REG32(ICDC_APHPEN) 1159 #define REG_ICDC_APSR REG32(ICDC_APSR) 1160 #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) 1161 #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) 1162 1163 /* ICDC Control Register */ 1164 #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ 1165 #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) 1166 #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ 1167 #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) 1168 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) 1169 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) 1170 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) 1171 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) 1172 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) 1173 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) 1174 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) 1175 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) 1176 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) 1177 #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ 1178 #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) 1179 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) 1180 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) 1181 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) 1182 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) 1183 #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ 1184 #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) 1185 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) 1186 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) 1187 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) 1188 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) 1189 #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ 1190 #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ 1191 #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ 1192 #define ICDC_CR_EADC (1 << 10) /* Enable ADC */ 1193 #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ 1194 #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ 1195 #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ 1196 #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ 1197 #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ 1198 #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ 1199 #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ 1200 #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ 1201 1202 /* Anti-Pop WAIT Stage Timing Control Register */ 1203 #define ICDC_APWAIT_WAITSN_BIT 0 1204 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) 1205 1206 /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1207 #define ICDC_APPRE_PRESN_BIT 0 1208 #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) 1209 1210 /* Anti-Pop HPEN Stage Timing Control Register */ 1211 #define ICDC_APHPEN_HPENSN_BIT 0 1212 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) 1213 1214 /* Anti-Pop Status Register */ 1215 #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ 1216 #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) 1217 #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ 1218 #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ 1219 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ 1220 #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ 1221 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ 1222 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ 1223 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ 1224 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ 1225 #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ 1226 #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) 1227 1228 1229 /************************************************************************* 1230 * I2C 1231 *************************************************************************/ 1232 #define I2C_DR (I2C_BASE + 0x000) 1233 #define I2C_CR (I2C_BASE + 0x004) 1234 #define I2C_SR (I2C_BASE + 0x008) 1235 #define I2C_GR (I2C_BASE + 0x00C) 1236 1237 #define REG_I2C_DR REG8(I2C_DR) 1238 #define REG_I2C_CR REG8(I2C_CR) 1239 #define REG_I2C_SR REG8(I2C_SR) 1240 #define REG_I2C_GR REG16(I2C_GR) 1241 1242 /* I2C Control Register (I2C_CR) */ 1243 1244 #define I2C_CR_IEN (1 << 4) 1245 #define I2C_CR_STA (1 << 3) 1246 #define I2C_CR_STO (1 << 2) 1247 #define I2C_CR_AC (1 << 1) 1248 #define I2C_CR_I2CE (1 << 0) 1249 1250 /* I2C Status Register (I2C_SR) */ 1251 1252 #define I2C_SR_STX (1 << 4) 1253 #define I2C_SR_BUSY (1 << 3) 1254 #define I2C_SR_TEND (1 << 2) 1255 #define I2C_SR_DRF (1 << 1) 1256 #define I2C_SR_ACKF (1 << 0) 1257 1258 1259 /************************************************************************* 1260 * SSI 1261 *************************************************************************/ 1262 #define SSI_DR (SSI_BASE + 0x000) 1263 #define SSI_CR0 (SSI_BASE + 0x004) 1264 #define SSI_CR1 (SSI_BASE + 0x008) 1265 #define SSI_SR (SSI_BASE + 0x00C) 1266 #define SSI_ITR (SSI_BASE + 0x010) 1267 #define SSI_ICR (SSI_BASE + 0x014) 1268 #define SSI_GR (SSI_BASE + 0x018) 1269 1270 #define REG_SSI_DR REG32(SSI_DR) 1271 #define REG_SSI_CR0 REG16(SSI_CR0) 1272 #define REG_SSI_CR1 REG32(SSI_CR1) 1273 #define REG_SSI_SR REG32(SSI_SR) 1274 #define REG_SSI_ITR REG16(SSI_ITR) 1275 #define REG_SSI_ICR REG8(SSI_ICR) 1276 #define REG_SSI_GR REG16(SSI_GR) 1277 1278 /* SSI Data Register (SSI_DR) */ 1279 1280 #define SSI_DR_GPC_BIT 0 1281 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) 1282 1283 /* SSI Control Register 0 (SSI_CR0) */ 1284 1285 #define SSI_CR0_SSIE (1 << 15) 1286 #define SSI_CR0_TIE (1 << 14) 1287 #define SSI_CR0_RIE (1 << 13) 1288 #define SSI_CR0_TEIE (1 << 12) 1289 #define SSI_CR0_REIE (1 << 11) 1290 #define SSI_CR0_LOOP (1 << 10) 1291 #define SSI_CR0_RFINE (1 << 9) 1292 #define SSI_CR0_RFINC (1 << 8) 1293 #define SSI_CR0_FSEL (1 << 6) 1294 #define SSI_CR0_TFLUSH (1 << 2) 1295 #define SSI_CR0_RFLUSH (1 << 1) 1296 #define SSI_CR0_DISREV (1 << 0) 1297 1298 /* SSI Control Register 1 (SSI_CR1) */ 1299 1300 #define SSI_CR1_FRMHL_BIT 30 1301 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) 1302 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ 1303 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ 1304 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ 1305 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ 1306 #define SSI_CR1_TFVCK_BIT 28 1307 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) 1308 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) 1309 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) 1310 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) 1311 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) 1312 #define SSI_CR1_TCKFI_BIT 26 1313 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) 1314 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) 1315 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) 1316 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) 1317 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) 1318 #define SSI_CR1_LFST (1 << 25) 1319 #define SSI_CR1_ITFRM (1 << 24) 1320 #define SSI_CR1_UNFIN (1 << 23) 1321 #define SSI_CR1_MULTS (1 << 22) 1322 #define SSI_CR1_FMAT_BIT 20 1323 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) 1324 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ 1325 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ 1326 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ 1327 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ 1328 #define SSI_CR1_TTRG_BIT 16 1329 #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) 1330 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) 1331 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) 1332 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) 1333 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) 1334 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) 1335 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) 1336 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) 1337 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) 1338 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) 1339 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) 1340 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) 1341 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) 1342 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) 1343 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) 1344 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) 1345 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) 1346 #define SSI_CR1_MCOM_BIT 12 1347 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) 1348 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ 1349 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ 1350 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ 1351 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ 1352 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ 1353 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ 1354 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ 1355 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ 1356 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ 1357 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ 1358 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ 1359 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ 1360 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ 1361 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ 1362 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ 1363 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ 1364 #define SSI_CR1_RTRG_BIT 8 1365 #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) 1366 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) 1367 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) 1368 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) 1369 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) 1370 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) 1371 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) 1372 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) 1373 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) 1374 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) 1375 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) 1376 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) 1377 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) 1378 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) 1379 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) 1380 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) 1381 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) 1382 #define SSI_CR1_FLEN_BIT 4 1383 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) 1384 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) 1385 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) 1386 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) 1387 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) 1388 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) 1389 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) 1390 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) 1391 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) 1392 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) 1393 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) 1394 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) 1395 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) 1396 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) 1397 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) 1398 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) 1399 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) 1400 #define SSI_CR1_PHA (1 << 1) 1401 #define SSI_CR1_POL (1 << 0) 1402 1403 /* SSI Status Register (SSI_SR) */ 1404 1405 #define SSI_SR_TFIFONUM_BIT 16 1406 #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) 1407 #define SSI_SR_RFIFONUM_BIT 8 1408 #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) 1409 #define SSI_SR_END (1 << 7) 1410 #define SSI_SR_BUSY (1 << 6) 1411 #define SSI_SR_TFF (1 << 5) 1412 #define SSI_SR_RFE (1 << 4) 1413 #define SSI_SR_TFHE (1 << 3) 1414 #define SSI_SR_RFHF (1 << 2) 1415 #define SSI_SR_UNDR (1 << 1) 1416 #define SSI_SR_OVER (1 << 0) 1417 1418 /* SSI Interval Time Control Register (SSI_ITR) */ 1419 1420 #define SSI_ITR_CNTCLK (1 << 15) 1421 #define SSI_ITR_IVLTM_BIT 0 1422 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) 1423 1424 1425 /************************************************************************* 1426 * MSC 1427 *************************************************************************/ 1428 #define MSC_STRPCL (MSC_BASE + 0x000) 1429 #define MSC_STAT (MSC_BASE + 0x004) 1430 #define MSC_CLKRT (MSC_BASE + 0x008) 1431 #define MSC_CMDAT (MSC_BASE + 0x00C) 1432 #define MSC_RESTO (MSC_BASE + 0x010) 1433 #define MSC_RDTO (MSC_BASE + 0x014) 1434 #define MSC_BLKLEN (MSC_BASE + 0x018) 1435 #define MSC_NOB (MSC_BASE + 0x01C) 1436 #define MSC_SNOB (MSC_BASE + 0x020) 1437 #define MSC_IMASK (MSC_BASE + 0x024) 1438 #define MSC_IREG (MSC_BASE + 0x028) 1439 #define MSC_CMD (MSC_BASE + 0x02C) 1440 #define MSC_ARG (MSC_BASE + 0x030) 1441 #define MSC_RES (MSC_BASE + 0x034) 1442 #define MSC_RXFIFO (MSC_BASE + 0x038) 1443 #define MSC_TXFIFO (MSC_BASE + 0x03C) 1444 1445 #define REG_MSC_STRPCL REG16(MSC_STRPCL) 1446 #define REG_MSC_STAT REG32(MSC_STAT) 1447 #define REG_MSC_CLKRT REG16(MSC_CLKRT) 1448 #define REG_MSC_CMDAT REG32(MSC_CMDAT) 1449 #define REG_MSC_RESTO REG16(MSC_RESTO) 1450 #define REG_MSC_RDTO REG16(MSC_RDTO) 1451 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) 1452 #define REG_MSC_NOB REG16(MSC_NOB) 1453 #define REG_MSC_SNOB REG16(MSC_SNOB) 1454 #define REG_MSC_IMASK REG16(MSC_IMASK) 1455 #define REG_MSC_IREG REG16(MSC_IREG) 1456 #define REG_MSC_CMD REG8(MSC_CMD) 1457 #define REG_MSC_ARG REG32(MSC_ARG) 1458 #define REG_MSC_RES REG16(MSC_RES) 1459 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) 1460 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) 1461 1462 /* MSC Clock and Control Register (MSC_STRPCL) */ 1463 1464 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) 1465 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) 1466 #define MSC_STRPCL_START_READWAIT (1 << 5) 1467 #define MSC_STRPCL_STOP_READWAIT (1 << 4) 1468 #define MSC_STRPCL_RESET (1 << 3) 1469 #define MSC_STRPCL_START_OP (1 << 2) 1470 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 1471 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) 1472 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ 1473 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ 1474 1475 /* MSC Status Register (MSC_STAT) */ 1476 1477 #define MSC_STAT_IS_RESETTING (1 << 15) 1478 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) 1479 #define MSC_STAT_PRG_DONE (1 << 13) 1480 #define MSC_STAT_DATA_TRAN_DONE (1 << 12) 1481 #define MSC_STAT_END_CMD_RES (1 << 11) 1482 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) 1483 #define MSC_STAT_IS_READWAIT (1 << 9) 1484 #define MSC_STAT_CLK_EN (1 << 8) 1485 #define MSC_STAT_DATA_FIFO_FULL (1 << 7) 1486 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) 1487 #define MSC_STAT_CRC_RES_ERR (1 << 5) 1488 #define MSC_STAT_CRC_READ_ERROR (1 << 4) 1489 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 1490 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) 1491 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ 1492 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ 1493 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ 1494 #define MSC_STAT_TIME_OUT_RES (1 << 1) 1495 #define MSC_STAT_TIME_OUT_READ (1 << 0) 1496 1497 /* MSC Bus Clock Control Register (MSC_CLKRT) */ 1498 1499 #define MSC_CLKRT_CLK_RATE_BIT 0 1500 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) 1501 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ 1502 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ 1503 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ 1504 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ 1505 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ 1506 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ 1507 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ 1508 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ 1509 1510 /* MSC Command Sequence Control Register (MSC_CMDAT) */ 1511 1512 #define MSC_CMDAT_IO_ABORT (1 << 11) 1513 #define MSC_CMDAT_BUS_WIDTH_BIT 9 1514 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) 1515 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) 1516 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) 1517 #define MSC_CMDAT_DMA_EN (1 << 8) 1518 #define MSC_CMDAT_INIT (1 << 7) 1519 #define MSC_CMDAT_BUSY (1 << 6) 1520 #define MSC_CMDAT_STREAM_BLOCK (1 << 5) 1521 #define MSC_CMDAT_WRITE (1 << 4) 1522 #define MSC_CMDAT_READ (0 << 4) 1523 #define MSC_CMDAT_DATA_EN (1 << 3) 1524 #define MSC_CMDAT_RESPONSE_BIT 0 1525 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) 1526 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) 1527 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) 1528 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) 1529 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) 1530 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) 1531 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) 1532 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) 1533 1534 /* MSC Interrupts Mask Register (MSC_IMASK) */ 1535 #define MSC_IMASK_SDIO (1 << 7) 1536 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) 1537 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) 1538 #define MSC_IMASK_END_CMD_RES (1 << 2) 1539 #define MSC_IMASK_PRG_DONE (1 << 1) 1540 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) 1541 1542 1543 /* MSC Interrupts Status Register (MSC_IREG) */ 1544 #define MSC_IREG_SDIO (1 << 7) 1545 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) 1546 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) 1547 #define MSC_IREG_END_CMD_RES (1 << 2) 1548 #define MSC_IREG_PRG_DONE (1 << 1) 1549 #define MSC_IREG_DATA_TRAN_DONE (1 << 0) 1550 1551 1552 /* 1553 * EMC (External Memory Controller) 1554 */ 1555 #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ 1556 1557 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ 1558 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ 1559 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ 1560 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ 1561 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ 1562 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ 1563 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ 1564 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ 1565 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ 1566 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ 1567 1568 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ 1569 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ 1570 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ 1571 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ 1572 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ 1573 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ 1574 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ 1575 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ 1576 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ 1577 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ 1578 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ 1579 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ 1580 1581 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ 1582 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ 1583 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ 1584 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ 1585 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ 1586 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ 1587 1588 #define REG_EMC_BCR REG32(EMC_BCR) 1589 1590 #define REG_EMC_SMCR0 REG32(EMC_SMCR0) 1591 #define REG_EMC_SMCR1 REG32(EMC_SMCR1) 1592 #define REG_EMC_SMCR2 REG32(EMC_SMCR2) 1593 #define REG_EMC_SMCR3 REG32(EMC_SMCR3) 1594 #define REG_EMC_SMCR4 REG32(EMC_SMCR4) 1595 #define REG_EMC_SACR0 REG32(EMC_SACR0) 1596 #define REG_EMC_SACR1 REG32(EMC_SACR1) 1597 #define REG_EMC_SACR2 REG32(EMC_SACR2) 1598 #define REG_EMC_SACR3 REG32(EMC_SACR3) 1599 #define REG_EMC_SACR4 REG32(EMC_SACR4) 1600 1601 #define REG_EMC_NFCSR REG32(EMC_NFCSR) 1602 #define REG_EMC_NFECR REG32(EMC_NFECR) 1603 #define REG_EMC_NFECC REG32(EMC_NFECC) 1604 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) 1605 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) 1606 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) 1607 #define REG_EMC_NFINTS REG32(EMC_NFINTS) 1608 #define REG_EMC_NFINTE REG32(EMC_NFINTE) 1609 #define REG_EMC_NFERR0 REG32(EMC_NFERR0) 1610 #define REG_EMC_NFERR1 REG32(EMC_NFERR1) 1611 #define REG_EMC_NFERR2 REG32(EMC_NFERR2) 1612 #define REG_EMC_NFERR3 REG32(EMC_NFERR3) 1613 1614 #define REG_EMC_DMCR REG32(EMC_DMCR) 1615 #define REG_EMC_RTCSR REG16(EMC_RTCSR) 1616 #define REG_EMC_RTCNT REG16(EMC_RTCNT) 1617 #define REG_EMC_RTCOR REG16(EMC_RTCOR) 1618 #define REG_EMC_DMAR0 REG32(EMC_DMAR0) 1619 1620 /* Static Memory Control Register */ 1621 #define EMC_SMCR_STRV_BIT 24 1622 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) 1623 #define EMC_SMCR_TAW_BIT 20 1624 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) 1625 #define EMC_SMCR_TBP_BIT 16 1626 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) 1627 #define EMC_SMCR_TAH_BIT 12 1628 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) 1629 #define EMC_SMCR_TAS_BIT 8 1630 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) 1631 #define EMC_SMCR_BW_BIT 6 1632 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) 1633 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) 1634 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) 1635 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) 1636 #define EMC_SMCR_BCM (1 << 3) 1637 #define EMC_SMCR_BL_BIT 1 1638 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) 1639 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) 1640 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) 1641 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) 1642 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) 1643 #define EMC_SMCR_SMT (1 << 0) 1644 1645 /* Static Memory Bank Addr Config Reg */ 1646 #define EMC_SACR_BASE_BIT 8 1647 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) 1648 #define EMC_SACR_MASK_BIT 0 1649 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) 1650 1651 /* NAND Flash Control/Status Register */ 1652 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ 1653 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ 1654 #define EMC_NFCSR_NFCE3 (1 << 5) 1655 #define EMC_NFCSR_NFE3 (1 << 4) 1656 #define EMC_NFCSR_NFCE2 (1 << 3) 1657 #define EMC_NFCSR_NFE2 (1 << 2) 1658 #define EMC_NFCSR_NFCE1 (1 << 1) 1659 #define EMC_NFCSR_NFE1 (1 << 0) 1660 1661 /* NAND Flash ECC Control Register */ 1662 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ 1663 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ 1664 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ 1665 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ 1666 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ 1667 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ 1668 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ 1669 1670 /* NAND Flash ECC Data Register */ 1671 #define EMC_NFECC_ECC2_BIT 16 1672 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) 1673 #define EMC_NFECC_ECC1_BIT 8 1674 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) 1675 #define EMC_NFECC_ECC0_BIT 0 1676 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) 1677 1678 /* NAND Flash Interrupt Status Register */ 1679 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ 1680 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) 1681 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ 1682 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ 1683 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ 1684 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ 1685 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ 1686 1687 /* NAND Flash Interrupt Enable Register */ 1688 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ 1689 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ 1690 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ 1691 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ 1692 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ 1693 1694 /* NAND Flash RS Error Report Register */ 1695 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ 1696 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) 1697 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ 1698 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) 1699 1700 1701 /* DRAM Control Register */ 1702 #define EMC_DMCR_BW_BIT 31 1703 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) 1704 #define EMC_DMCR_CA_BIT 26 1705 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) 1706 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) 1707 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) 1708 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) 1709 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) 1710 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) 1711 #define EMC_DMCR_RMODE (1 << 25) 1712 #define EMC_DMCR_RFSH (1 << 24) 1713 #define EMC_DMCR_MRSET (1 << 23) 1714 #define EMC_DMCR_RA_BIT 20 1715 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) 1716 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) 1717 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) 1718 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) 1719 #define EMC_DMCR_BA_BIT 19 1720 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) 1721 #define EMC_DMCR_PDM (1 << 18) 1722 #define EMC_DMCR_EPIN (1 << 17) 1723 #define EMC_DMCR_TRAS_BIT 13 1724 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) 1725 #define EMC_DMCR_RCD_BIT 11 1726 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) 1727 #define EMC_DMCR_TPC_BIT 8 1728 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) 1729 #define EMC_DMCR_TRWL_BIT 5 1730 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) 1731 #define EMC_DMCR_TRC_BIT 2 1732 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) 1733 #define EMC_DMCR_TCL_BIT 0 1734 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) 1735 1736 /* Refresh Time Control/Status Register */ 1737 #define EMC_RTCSR_CMF (1 << 7) 1738 #define EMC_RTCSR_CKS_BIT 0 1739 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) 1740 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) 1741 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) 1742 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) 1743 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) 1744 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) 1745 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) 1746 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) 1747 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) 1748 1749 /* SDRAM Bank Address Configuration Register */ 1750 #define EMC_DMAR_BASE_BIT 8 1751 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) 1752 #define EMC_DMAR_MASK_BIT 0 1753 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) 1754 1755 /* Mode Register of SDRAM bank 0 */ 1756 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ 1757 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ 1758 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) 1759 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) 1760 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ 1761 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) 1762 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) 1763 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) 1764 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) 1765 #define EMC_SDMR_BT_BIT 3 /* Burst Type */ 1766 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) 1767 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ 1768 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ 1769 #define EMC_SDMR_BL_BIT 0 /* Burst Length */ 1770 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) 1771 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) 1772 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) 1773 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) 1774 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) 1775 1776 #define EMC_SDMR_CAS2_16BIT \ 1777 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1778 #define EMC_SDMR_CAS2_32BIT \ 1779 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1780 #define EMC_SDMR_CAS3_16BIT \ 1781 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1782 #define EMC_SDMR_CAS3_32BIT \ 1783 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1784 1785 /************************************************************************* 1786 * CIM 1787 *************************************************************************/ 1788 #define CIM_CFG (CIM_BASE + 0x0000) 1789 #define CIM_CTRL (CIM_BASE + 0x0004) 1790 #define CIM_STATE (CIM_BASE + 0x0008) 1791 #define CIM_IID (CIM_BASE + 0x000C) 1792 #define CIM_RXFIFO (CIM_BASE + 0x0010) 1793 #define CIM_DA (CIM_BASE + 0x0020) 1794 #define CIM_FA (CIM_BASE + 0x0024) 1795 #define CIM_FID (CIM_BASE + 0x0028) 1796 #define CIM_CMD (CIM_BASE + 0x002C) 1797 1798 #define REG_CIM_CFG REG32(CIM_CFG) 1799 #define REG_CIM_CTRL REG32(CIM_CTRL) 1800 #define REG_CIM_STATE REG32(CIM_STATE) 1801 #define REG_CIM_IID REG32(CIM_IID) 1802 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) 1803 #define REG_CIM_DA REG32(CIM_DA) 1804 #define REG_CIM_FA REG32(CIM_FA) 1805 #define REG_CIM_FID REG32(CIM_FID) 1806 #define REG_CIM_CMD REG32(CIM_CMD) 1807 1808 /* CIM Configuration Register (CIM_CFG) */ 1809 1810 #define CIM_CFG_INV_DAT (1 << 15) 1811 #define CIM_CFG_VSP (1 << 14) 1812 #define CIM_CFG_HSP (1 << 13) 1813 #define CIM_CFG_PCP (1 << 12) 1814 #define CIM_CFG_DUMMY_ZERO (1 << 9) 1815 #define CIM_CFG_EXT_VSYNC (1 << 8) 1816 #define CIM_CFG_PACK_BIT 4 1817 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) 1818 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) 1819 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) 1820 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) 1821 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) 1822 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) 1823 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) 1824 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) 1825 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) 1826 #define CIM_CFG_DSM_BIT 0 1827 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) 1828 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ 1829 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ 1830 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ 1831 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ 1832 1833 /* CIM Control Register (CIM_CTRL) */ 1834 1835 #define CIM_CTRL_MCLKDIV_BIT 24 1836 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) 1837 #define CIM_CTRL_FRC_BIT 16 1838 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) 1839 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ 1840 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ 1841 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ 1842 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ 1843 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ 1844 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ 1845 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ 1846 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ 1847 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ 1848 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ 1849 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ 1850 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ 1851 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ 1852 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ 1853 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ 1854 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ 1855 #define CIM_CTRL_VDDM (1 << 13) 1856 #define CIM_CTRL_DMA_SOFM (1 << 12) 1857 #define CIM_CTRL_DMA_EOFM (1 << 11) 1858 #define CIM_CTRL_DMA_STOPM (1 << 10) 1859 #define CIM_CTRL_RXF_TRIGM (1 << 9) 1860 #define CIM_CTRL_RXF_OFM (1 << 8) 1861 #define CIM_CTRL_RXF_TRIG_BIT 4 1862 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) 1863 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ 1864 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ 1865 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ 1866 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ 1867 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ 1868 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ 1869 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ 1870 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ 1871 #define CIM_CTRL_DMA_EN (1 << 2) 1872 #define CIM_CTRL_RXF_RST (1 << 1) 1873 #define CIM_CTRL_ENA (1 << 0) 1874 1875 /* CIM State Register (CIM_STATE) */ 1876 1877 #define CIM_STATE_DMA_SOF (1 << 6) 1878 #define CIM_STATE_DMA_EOF (1 << 5) 1879 #define CIM_STATE_DMA_STOP (1 << 4) 1880 #define CIM_STATE_RXF_OF (1 << 3) 1881 #define CIM_STATE_RXF_TRIG (1 << 2) 1882 #define CIM_STATE_RXF_EMPTY (1 << 1) 1883 #define CIM_STATE_VDD (1 << 0) 1884 1885 /* CIM DMA Command Register (CIM_CMD) */ 1886 1887 #define CIM_CMD_SOFINT (1 << 31) 1888 #define CIM_CMD_EOFINT (1 << 30) 1889 #define CIM_CMD_STOP (1 << 28) 1890 #define CIM_CMD_LEN_BIT 0 1891 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) 1892 1893 1894 /************************************************************************* 1895 * SADC (Smart A/D Controller) 1896 *************************************************************************/ 1897 1898 #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ 1899 #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ 1900 #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ 1901 #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ 1902 #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ 1903 #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ 1904 #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ 1905 #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ 1906 #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ 1907 1908 #define REG_SADC_ENA REG8(SADC_ENA) 1909 #define REG_SADC_CFG REG32(SADC_CFG) 1910 #define REG_SADC_CTRL REG8(SADC_CTRL) 1911 #define REG_SADC_STATE REG8(SADC_STATE) 1912 #define REG_SADC_SAMETIME REG16(SADC_SAMETIME) 1913 #define REG_SADC_WAITTIME REG16(SADC_WAITTIME) 1914 #define REG_SADC_TSDAT REG32(SADC_TSDAT) 1915 #define REG_SADC_BATDAT REG16(SADC_BATDAT) 1916 #define REG_SADC_SADDAT REG16(SADC_SADDAT) 1917 1918 /* ADC Enable Register */ 1919 #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ 1920 #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ 1921 #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ 1922 #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ 1923 1924 /* ADC Configure Register */ 1925 #define SADC_CFG_CLKOUT_NUM_BIT 16 1926 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) 1927 #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ 1928 #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ 1929 #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) 1930 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) 1931 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) 1932 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) 1933 #define SADC_CFG_SNUM_BIT 10 /* Sample Number */ 1934 #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) 1935 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) 1936 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) 1937 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) 1938 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) 1939 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) 1940 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) 1941 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) 1942 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) 1943 #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ 1944 #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) 1945 #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ 1946 #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ 1947 #define SADC_CFG_CMD_BIT 0 /* ADC Command */ 1948 #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) 1949 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ 1950 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ 1951 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ 1952 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ 1953 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ 1954 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ 1955 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ 1956 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ 1957 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ 1958 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ 1959 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ 1960 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ 1961 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ 1962 1963 /* ADC Control Register */ 1964 #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ 1965 #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ 1966 #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ 1967 #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ 1968 #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ 1969 1970 /* ADC Status Register */ 1971 #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ 1972 #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ 1973 #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ 1974 #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ 1975 #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ 1976 #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ 1977 #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ 1978 #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ 1979 1980 /* ADC Touch Screen Data Register */ 1981 #define SADC_TSDAT_DATA0_BIT 0 1982 #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) 1983 #define SADC_TSDAT_TYPE0 (1 << 15) 1984 #define SADC_TSDAT_DATA1_BIT 16 1985 #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) 1986 #define SADC_TSDAT_TYPE1 (1 << 31) 1987 1988 1989 /************************************************************************* 1990 * SLCD (Smart LCD Controller) 1991 *************************************************************************/ 1992 1993 #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ 1994 #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ 1995 #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ 1996 #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ 1997 #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ 1998 1999 #define REG_SLCD_CFG REG32(SLCD_CFG) 2000 #define REG_SLCD_CTRL REG8(SLCD_CTRL) 2001 #define REG_SLCD_STATE REG8(SLCD_STATE) 2002 #define REG_SLCD_DATA REG32(SLCD_DATA) 2003 #define REG_SLCD_FIFO REG32(SLCD_FIFO) 2004 2005 /* SLCD Configure Register */ 2006 #define SLCD_CFG_BURST_BIT 14 2007 #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) 2008 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) 2009 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) 2010 #define SLCD_CFG_DWIDTH_BIT 10 2011 #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) 2012 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) 2013 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) 2014 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) 2015 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) 2016 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) 2017 #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) 2018 #define SLCD_CFG_CWIDTH_16BIT (0 << 8) 2019 #define SLCD_CFG_CWIDTH_8BIT (1 << 8) 2020 #define SLCD_CFG_CWIDTH_18BIT (2 << 8) 2021 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) 2022 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) 2023 #define SLCD_CFG_RS_CMD_LOW (0 << 3) 2024 #define SLCD_CFG_RS_CMD_HIGH (1 << 3) 2025 #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) 2026 #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) 2027 #define SLCD_CFG_TYPE_PARALLEL (0 << 0) 2028 #define SLCD_CFG_TYPE_SERIAL (1 << 0) 2029 2030 /* SLCD Control Register */ 2031 #define SLCD_CTRL_DMA_EN (1 << 0) 2032 2033 /* SLCD Status Register */ 2034 #define SLCD_STATE_BUSY (1 << 0) 2035 2036 /* SLCD Data Register */ 2037 #define SLCD_DATA_RS_DATA (0 << 31) 2038 #define SLCD_DATA_RS_COMMAND (1 << 31) 2039 2040 /* SLCD FIFO Register */ 2041 #define SLCD_FIFO_RS_DATA (0 << 31) 2042 #define SLCD_FIFO_RS_COMMAND (1 << 31) 2043 2044 2045 /************************************************************************* 2046 * LCD (LCD Controller) 2047 *************************************************************************/ 2048 2049 /* Register definitions with absolute positioning have been removed. */ 2050 2051 /* LCD Configure Register */ 2052 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ 2053 #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) 2054 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) 2055 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) 2056 #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ 2057 #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ 2058 #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ 2059 #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ 2060 #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ 2061 #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ 2062 #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ 2063 #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ 2064 #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ 2065 #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ 2066 #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ 2067 #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ 2068 #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ 2069 #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ 2070 #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ 2071 #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ 2072 #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ 2073 #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) 2074 #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ 2075 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ 2076 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ 2077 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ 2078 #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ 2079 #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) 2080 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ 2081 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) 2082 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) 2083 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) 2084 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) 2085 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) 2086 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) 2087 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) 2088 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) 2089 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) 2090 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) 2091 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) 2092 /* JZ47XX defines */ 2093 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) 2094 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) 2095 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) 2096 2097 2098 2099 /* Vertical Synchronize Register */ 2100 #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ 2101 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2102 #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ 2103 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2104 2105 /* Horizontal Synchronize Register */ 2106 #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ 2107 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) 2108 #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ 2109 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) 2110 2111 /* Virtual Area Setting Register */ 2112 #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ 2113 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) 2114 #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ 2115 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) 2116 2117 /* Display Area Horizontal Start/End Point Register */ 2118 #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ 2119 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) 2120 #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ 2121 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) 2122 2123 /* Display Area Vertical Start/End Point Register */ 2124 #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ 2125 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) 2126 #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ 2127 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) 2128 2129 /* PS Signal Setting */ 2130 #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ 2131 #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) 2132 #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ 2133 #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) 2134 2135 /* CLS Signal Setting */ 2136 #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ 2137 #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) 2138 #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ 2139 #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) 2140 2141 /* SPL Signal Setting */ 2142 #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ 2143 #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) 2144 #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ 2145 #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) 2146 2147 /* REV Signal Setting */ 2148 #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ 2149 #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) 2150 2151 /* LCD Control Register */ 2152 #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ 2153 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) 2154 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ 2155 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ 2156 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ 2157 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ 2158 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ 2159 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ 2160 #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ 2161 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) 2162 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ 2163 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ 2164 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ 2165 #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ 2166 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) 2167 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ 2168 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ 2169 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ 2170 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ 2171 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ 2172 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ 2173 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ 2174 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ 2175 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ 2176 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ 2177 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ 2178 #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ 2179 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) 2180 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ 2181 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ 2182 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ 2183 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ 2184 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ 2185 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ 2186 2187 /* LCD Status Register */ 2188 #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ 2189 #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ 2190 #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ 2191 #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ 2192 #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ 2193 #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ 2194 #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ 2195 2196 /* DMA Command Register */ 2197 #define LCD_CMD_SOFINT (1 << 31) 2198 #define LCD_CMD_EOFINT (1 << 30) 2199 #define LCD_CMD_PAL (1 << 28) 2200 #define LCD_CMD_LEN_BIT 0 2201 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) 2202 2203 2204 /************************************************************************* 2205 * USB Device 2206 *************************************************************************/ 2207 #define USB_BASE UDC_BASE 2208 2209 #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ 2210 #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ 2211 #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ 2212 #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ 2213 #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ 2214 #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ 2215 #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ 2216 #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ 2217 #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ 2218 #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ 2219 #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ 2220 2221 #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ 2222 #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ 2223 #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ 2224 #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ 2225 #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ 2226 #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ 2227 #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ 2228 #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ 2229 2230 #define USB_FIFO_EP0 (USB_BASE + 0x20) 2231 #define USB_FIFO_EP1 (USB_BASE + 0x24) 2232 #define USB_FIFO_EP2 (USB_BASE + 0x28) 2233 2234 #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ 2235 #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ 2236 2237 #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ 2238 #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ 2239 #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ 2240 #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ 2241 #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ 2242 #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ 2243 #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ 2244 2245 2246 /* Power register bit masks */ 2247 #define USB_POWER_SUSPENDM 0x01 2248 #define USB_POWER_RESUME 0x04 2249 #define USB_POWER_HSMODE 0x10 2250 #define USB_POWER_HSENAB 0x20 2251 #define USB_POWER_SOFTCONN 0x40 2252 2253 /* Interrupt register bit masks */ 2254 #define USB_INTR_SUSPEND 0x01 2255 #define USB_INTR_RESUME 0x02 2256 #define USB_INTR_RESET 0x04 2257 2258 #define USB_INTR_EP0 0x0001 2259 #define USB_INTR_INEP1 0x0002 2260 #define USB_INTR_INEP2 0x0004 2261 #define USB_INTR_OUTEP1 0x0002 2262 2263 /* CSR0 bit masks */ 2264 #define USB_CSR0_OUTPKTRDY 0x01 2265 #define USB_CSR0_INPKTRDY 0x02 2266 #define USB_CSR0_SENTSTALL 0x04 2267 #define USB_CSR0_DATAEND 0x08 2268 #define USB_CSR0_SETUPEND 0x10 2269 #define USB_CSR0_SENDSTALL 0x20 2270 #define USB_CSR0_SVDOUTPKTRDY 0x40 2271 #define USB_CSR0_SVDSETUPEND 0x80 2272 2273 /* Endpoint CSR register bits */ 2274 #define USB_INCSRH_AUTOSET 0x80 2275 #define USB_INCSRH_ISO 0x40 2276 #define USB_INCSRH_MODE 0x20 2277 #define USB_INCSRH_DMAREQENAB 0x10 2278 #define USB_INCSRH_DMAREQMODE 0x04 2279 #define USB_INCSR_CDT 0x40 2280 #define USB_INCSR_SENTSTALL 0x20 2281 #define USB_INCSR_SENDSTALL 0x10 2282 #define USB_INCSR_FF 0x08 2283 #define USB_INCSR_UNDERRUN 0x04 2284 #define USB_INCSR_FFNOTEMPT 0x02 2285 #define USB_INCSR_INPKTRDY 0x01 2286 #define USB_OUTCSRH_AUTOCLR 0x80 2287 #define USB_OUTCSRH_ISO 0x40 2288 #define USB_OUTCSRH_DMAREQENAB 0x20 2289 #define USB_OUTCSRH_DNYT 0x10 2290 #define USB_OUTCSRH_DMAREQMODE 0x08 2291 #define USB_OUTCSR_CDT 0x80 2292 #define USB_OUTCSR_SENTSTALL 0x40 2293 #define USB_OUTCSR_SENDSTALL 0x20 2294 #define USB_OUTCSR_FF 0x10 2295 #define USB_OUTCSR_DATAERR 0x08 2296 #define USB_OUTCSR_OVERRUN 0x04 2297 #define USB_OUTCSR_FFFULL 0x02 2298 #define USB_OUTCSR_OUTPKTRDY 0x01 2299 2300 /* Testmode register bits */ 2301 #define USB_TEST_SE0NAK 0x01 2302 #define USB_TEST_J 0x02 2303 #define USB_TEST_K 0x04 2304 #define USB_TEST_PACKET 0x08 2305 2306 /* DMA control bits */ 2307 #define USB_CNTL_ENA 0x01 2308 #define USB_CNTL_DIR_IN 0x02 2309 #define USB_CNTL_MODE_1 0x04 2310 #define USB_CNTL_INTR_EN 0x08 2311 #define USB_CNTL_EP(n) ((n) << 4) 2312 #define USB_CNTL_BURST_0 (0 << 9) 2313 #define USB_CNTL_BURST_4 (1 << 9) 2314 #define USB_CNTL_BURST_8 (2 << 9) 2315 #define USB_CNTL_BURST_16 (3 << 9) 2316 2317 2318 2319 /* Module Operation Definitions */ 2320 #ifndef __ASSEMBLY__ 2321 2322 2323 /* GPIO Pins Description */ 2324 /* PORT 0: */ 2325 /* PIN/BIT N FUNC0 FUNC1 */ 2326 /* 0 D0 - */ 2327 /* 1 D1 - */ 2328 /* 2 D2 - */ 2329 /* 3 D3 - */ 2330 /* 4 D4 - */ 2331 /* 5 D5 - */ 2332 /* 6 D6 - */ 2333 /* 7 D7 - */ 2334 /* 8 D8 - */ 2335 /* 9 D9 - */ 2336 /* 10 D10 - */ 2337 /* 11 D11 - */ 2338 /* 12 D12 - */ 2339 /* 13 D13 - */ 2340 /* 14 D14 - */ 2341 /* 15 D15 - */ 2342 /* 16 D16 - */ 2343 /* 17 D17 - */ 2344 /* 18 D18 - */ 2345 /* 19 D19 - */ 2346 /* 20 D20 - */ 2347 /* 21 D21 - */ 2348 /* 22 D22 - */ 2349 /* 23 D23 - */ 2350 /* 24 D24 - */ 2351 /* 25 D25 - */ 2352 /* 26 D26 - */ 2353 /* 27 D27 - */ 2354 /* 28 D28 - */ 2355 /* 29 D29 - */ 2356 /* 30 D30 - */ 2357 /* 31 D31 - */ 2358 /*------------------------------------------------------ */ 2359 /* PORT 1: */ 2360 /* */ 2361 /* PIN/BIT N FUNC0 FUNC1 */ 2362 /* 0 A0 - */ 2363 /* 1 A1 - */ 2364 /* 2 A2 - */ 2365 /* 3 A3 - */ 2366 /* 4 A4 - */ 2367 /* 5 A5 - */ 2368 /* 6 A6 - */ 2369 /* 7 A7 - */ 2370 /* 8 A8 - */ 2371 /* 9 A9 - */ 2372 /* 10 A10 - */ 2373 /* 11 A11 - */ 2374 /* 12 A12 - */ 2375 /* 13 A13 - */ 2376 /* 14 A14 - */ 2377 /* 15 A15/CL - */ 2378 /* 16 A16/AL - */ 2379 /* 17 LCD_CLS A21 */ 2380 /* 18 LCD_SPL A22 */ 2381 /* 19 DCS# - */ 2382 /* 20 RAS# - */ 2383 /* 21 CAS# - */ 2384 /* 22 RDWE#/BUFD# - */ 2385 /* 23 CKE - */ 2386 /* 24 CKO - */ 2387 /* 25 CS1# - */ 2388 /* 26 CS2# - */ 2389 /* 27 CS3# - */ 2390 /* 28 CS4# - */ 2391 /* 29 RD# - */ 2392 /* 30 WR# - */ 2393 /* 31 WE0# - */ 2394 /* Note: PIN15&16 are CL&AL when connecting to NAND flash. */ 2395 /*------------------------------------------------------ */ 2396 /* PORT 2: */ 2397 /* */ 2398 /* PIN/BIT N FUNC0 FUNC1 */ 2399 /* 0 LCD_D0 - */ 2400 /* 1 LCD_D1 - */ 2401 /* 2 LCD_D2 - */ 2402 /* 3 LCD_D3 - */ 2403 /* 4 LCD_D4 - */ 2404 /* 5 LCD_D5 - */ 2405 /* 6 LCD_D6 - */ 2406 /* 7 LCD_D7 - */ 2407 /* 8 LCD_D8 - */ 2408 /* 9 LCD_D9 - */ 2409 /* 10 LCD_D10 - */ 2410 /* 11 LCD_D11 - */ 2411 /* 12 LCD_D12 - */ 2412 /* 13 LCD_D13 - */ 2413 /* 14 LCD_D14 - */ 2414 /* 15 LCD_D15 - */ 2415 /* 16 LCD_D16 - */ 2416 /* 17 LCD_D17 - */ 2417 /* 18 LCD_PCLK - */ 2418 /* 19 LCD_HSYNC - */ 2419 /* 20 LCD_VSYNC - */ 2420 /* 21 LCD_DE - */ 2421 /* 22 LCD_PS A19 */ 2422 /* 23 LCD_REV A20 */ 2423 /* 24 WE1# - */ 2424 /* 25 WE2# - */ 2425 /* 26 WE3# - */ 2426 /* 27 WAIT# - */ 2427 /* 28 FRE# - */ 2428 /* 29 FWE# - */ 2429 /* 30(NOTE:FRB#) - - */ 2430 /* 31 - - */ 2431 /* NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. */ 2432 /*------------------------------------------------------ */ 2433 /* PORT 3: */ 2434 /* */ 2435 /* PIN/BIT N FUNC0 FUNC1 */ 2436 /* 0 CIM_D0 - */ 2437 /* 1 CIM_D1 - */ 2438 /* 2 CIM_D2 - */ 2439 /* 3 CIM_D3 - */ 2440 /* 4 CIM_D4 - */ 2441 /* 5 CIM_D5 - */ 2442 /* 6 CIM_D6 - */ 2443 /* 7 CIM_D7 - */ 2444 /* 8 MSC_CMD - */ 2445 /* 9 MSC_CLK - */ 2446 /* 10 MSC_D0 - */ 2447 /* 11 MSC_D1 - */ 2448 /* 12 MSC_D2 - */ 2449 /* 13 MSC_D3 - */ 2450 /* 14 CIM_MCLK - */ 2451 /* 15 CIM_PCLK - */ 2452 /* 16 CIM_VSYNC - */ 2453 /* 17 CIM_HSYNC - */ 2454 /* 18 SSI_CLK SCLK_RSTN */ 2455 /* 19 SSI_CE0# BIT_CLK(AIC) */ 2456 /* 20 SSI_DT SDATA_OUT(AIC) */ 2457 /* 21 SSI_DR SDATA_IN(AIC) */ 2458 /* 22 SSI_CE1#&GPC SYNC(AIC) */ 2459 /* 23 PWM0 I2C_SDA */ 2460 /* 24 PWM1 I2C_SCK */ 2461 /* 25 PWM2 UART0_TxD */ 2462 /* 26 PWM3 UART0_RxD */ 2463 /* 27 PWM4 A17 */ 2464 /* 28 PWM5 A18 */ 2465 /* 29 - - */ 2466 /* 30 PWM6 UART0_CTS/UART1_RxD */ 2467 /* 31 PWM7 UART0_RTS/UART1_TxD */ 2468 /* 2469 * p is the port number (0,1,2,3) 2470 * o is the pin offset (0-31) inside the port 2471 * n is the absolute number of a pin (0-127), regardless of the port 2472 */ 2473 2474 /* Function Pins Mode */ 2475 2476 #define __gpio_as_func0(n) \ 2477 do { \ 2478 unsigned int p, o; \ 2479 p = (n) / 32; \ 2480 o = (n) % 32; \ 2481 REG_GPIO_PXFUNS(p) = (1 << o); \ 2482 REG_GPIO_PXSELC(p) = (1 << o); \ 2483 } while (0) 2484 2485 #define __gpio_as_func1(n) \ 2486 do { \ 2487 unsigned int p, o; \ 2488 p = (n) / 32; \ 2489 o = (n) % 32; \ 2490 REG_GPIO_PXFUNS(p) = (1 << o); \ 2491 REG_GPIO_PXSELS(p) = (1 << o); \ 2492 } while (0) 2493 2494 /* 2495 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2496 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# 2497 */ 2498 #define __gpio_as_sdram_32bit() \ 2499 do { \ 2500 REG_GPIO_PXFUNS(0) = 0xffffffff; \ 2501 REG_GPIO_PXSELC(0) = 0xffffffff; \ 2502 REG_GPIO_PXPES(0) = 0xffffffff; \ 2503 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2504 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2505 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2506 REG_GPIO_PXFUNS(2) = 0x07000000; \ 2507 REG_GPIO_PXSELC(2) = 0x07000000; \ 2508 REG_GPIO_PXPES(2) = 0x07000000; \ 2509 } while (0) 2510 2511 /* 2512 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2513 * RDWE#, CKO#, WE0#, WE1# 2514 */ 2515 #define __gpio_as_sdram_16bit_4720() \ 2516 do { \ 2517 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ 2518 REG_GPIO_PXSELC(0) = 0x5442bfaa; \ 2519 REG_GPIO_PXPES(0) = 0x5442bfaa; \ 2520 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2521 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2522 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2523 REG_GPIO_PXFUNS(2) = 0x01000000; \ 2524 REG_GPIO_PXSELC(2) = 0x01000000; \ 2525 REG_GPIO_PXPES(2) = 0x01000000; \ 2526 } while (0) 2527 2528 /* 2529 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2530 * RDWE#, CKO#, WE0#, WE1# 2531 */ 2532 #define __gpio_as_sdram_16bit_4725() \ 2533 do { \ 2534 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2535 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2536 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2537 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2538 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2539 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2540 REG_GPIO_PXFUNS(2) = 0x01000000; \ 2541 REG_GPIO_PXSELC(2) = 0x01000000; \ 2542 REG_GPIO_PXPES(2) = 0x01000000; \ 2543 } while (0) 2544 2545 2546 /* 2547 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# 2548 */ 2549 #define __gpio_as_nand() \ 2550 do { \ 2551 REG_GPIO_PXFUNS(1) = 0x02018000; \ 2552 REG_GPIO_PXSELC(1) = 0x02018000; \ 2553 REG_GPIO_PXPES(1) = 0x02018000; \ 2554 REG_GPIO_PXFUNS(2) = 0x30000000; \ 2555 REG_GPIO_PXSELC(2) = 0x30000000; \ 2556 REG_GPIO_PXPES(2) = 0x30000000; \ 2557 REG_GPIO_PXFUNC(2) = 0x40000000; \ 2558 REG_GPIO_PXSELC(2) = 0x40000000; \ 2559 REG_GPIO_PXDIRC(2) = 0x40000000; \ 2560 REG_GPIO_PXPES(2) = 0x40000000; \ 2561 REG_GPIO_PXFUNS(1) = 0x00400000; \ 2562 REG_GPIO_PXSELC(1) = 0x00400000; \ 2563 } while (0) 2564 2565 /* 2566 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 2567 */ 2568 #define __gpio_as_nor_8bit() \ 2569 do { \ 2570 REG_GPIO_PXFUNS(0) = 0x000000ff; \ 2571 REG_GPIO_PXSELC(0) = 0x000000ff; \ 2572 REG_GPIO_PXPES(0) = 0x000000ff; \ 2573 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2574 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2575 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2576 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2577 REG_GPIO_PXSELS(1) = 0x00060000; \ 2578 REG_GPIO_PXPES(1) = 0x00060000; \ 2579 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2580 REG_GPIO_PXSELC(2) = 0x08000000; \ 2581 REG_GPIO_PXPES(2) = 0x08000000; \ 2582 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2583 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2584 REG_GPIO_PXPES(2) = 0x00c00000; \ 2585 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2586 REG_GPIO_PXSELS(3) = 0x18000000; \ 2587 REG_GPIO_PXPES(3) = 0x18000000; \ 2588 } while (0) 2589 2590 /* 2591 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 2592 */ 2593 #define __gpio_as_nor_16bit() \ 2594 do { \ 2595 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2596 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2597 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2598 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2599 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2600 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2601 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2602 REG_GPIO_PXSELS(1) = 0x00060000; \ 2603 REG_GPIO_PXPES(1) = 0x00060000; \ 2604 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2605 REG_GPIO_PXSELC(2) = 0x08000000; \ 2606 REG_GPIO_PXPES(2) = 0x08000000; \ 2607 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2608 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2609 REG_GPIO_PXPES(2) = 0x00c00000; \ 2610 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2611 REG_GPIO_PXSELS(3) = 0x18000000; \ 2612 REG_GPIO_PXPES(3) = 0x18000000; \ 2613 } while (0) 2614 2615 /* 2616 * UART0_TxD, UART_RxD0 2617 */ 2618 #define __gpio_as_uart0() \ 2619 do { \ 2620 REG_GPIO_PXFUNS(3) = 0x06000000; \ 2621 REG_GPIO_PXSELS(3) = 0x06000000; \ 2622 REG_GPIO_PXPES(3) = 0x06000000; \ 2623 } while (0) 2624 2625 #define __gpio_jtag_to_uart0() \ 2626 do { \ 2627 REG_GPIO_PXSELS(2) = 0x80000000; \ 2628 } while (0) 2629 2630 /* 2631 * UART0_CTS, UART0_RTS 2632 */ 2633 #define __gpio_as_ctsrts() \ 2634 do { \ 2635 REG_GPIO_PXFUNS(3) = 0xc0000000; \ 2636 REG_GPIO_PXSELS(3) = 0xc0000000; \ 2637 REG_GPIO_PXTRGC(3) = 0xc0000000; \ 2638 REG_GPIO_PXPES(3) = 0xc0000000; \ 2639 } while (0) 2640 2641 /* 2642 * UART1_TxD, UART1_RxD1 2643 */ 2644 #define __gpio_as_uart1() \ 2645 do { \ 2646 REG_GPIO_PXFUNS(3) = 0xc0000000; \ 2647 REG_GPIO_PXSELC(3) = 0xc0000000; \ 2648 REG_GPIO_PXTRGS(3) = 0xc0000000; \ 2649 REG_GPIO_PXPES(3) = 0xc0000000; \ 2650 } while (0) 2651 2652 /* 2653 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2654 */ 2655 #define __gpio_as_lcd_16bit() \ 2656 do { \ 2657 REG_GPIO_PXFUNS(2) = 0x003cffff; \ 2658 REG_GPIO_PXSELC(2) = 0x003cffff; \ 2659 REG_GPIO_PXPES(2) = 0x003cffff; \ 2660 } while (0) 2661 2662 /* 2663 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2664 */ 2665 #define __gpio_as_lcd_18bit() \ 2666 do { \ 2667 REG_GPIO_PXFUNS(2) = 0x003fffff; \ 2668 REG_GPIO_PXSELC(2) = 0x003fffff; \ 2669 REG_GPIO_PXPES(2) = 0x003fffff; \ 2670 } while (0) 2671 2672 2673 /* LCD_D0~LCD_D7, SLCD_CLK, SLCD_RS, SLCD_CS, LCD_DE */ 2674 #define __gpio_as_slcd_8bit() \ 2675 do { \ 2676 REG_GPIO_PXFUNS(2) = 0x003c00ff; \ 2677 REG_GPIO_PXSELC(2) = 0x003c00ff; \ 2678 } while (0) 2679 2680 /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ 2681 #define __gpio_as_slcd_9bit() \ 2682 do { \ 2683 REG_GPIO_PXFUNS(2) = 0x001801ff; \ 2684 REG_GPIO_PXSELC(2) = 0x001801ff; \ 2685 } while (0) 2686 2687 /* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */ 2688 #define __gpio_as_slcd_16bit() \ 2689 do { \ 2690 REG_GPIO_PXFUNS(2) = 0x0018ffff; \ 2691 REG_GPIO_PXSELC(2) = 0x0018ffff; \ 2692 } while (0) 2693 2694 /* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */ 2695 #define __gpio_as_slcd_18bit() \ 2696 do { \ 2697 REG_GPIO_PXFUNS(2) = 0x001bffff; \ 2698 REG_GPIO_PXSELC(2) = 0x001bffff; \ 2699 } while (0) 2700 /* 2701 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC 2702 */ 2703 #define __gpio_as_cim() \ 2704 do { \ 2705 REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ 2706 REG_GPIO_PXSELC(3) = 0x0003c0ff; \ 2707 REG_GPIO_PXPES(3) = 0x0003c0ff; \ 2708 } while (0) 2709 2710 /* 2711 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET 2712 */ 2713 #define __gpio_as_aic() \ 2714 do { \ 2715 REG_GPIO_PXFUNS(3) = 0x007c0000; \ 2716 REG_GPIO_PXSELS(3) = 0x007c0000; \ 2717 REG_GPIO_PXPES(3) = 0x007c0000; \ 2718 } while (0) 2719 2720 /* 2721 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 2722 */ 2723 #define __gpio_as_msc() \ 2724 do { \ 2725 REG_GPIO_PXFUNS(3) = 0x00003f00; \ 2726 REG_GPIO_PXSELC(3) = 0x00003f00; \ 2727 REG_GPIO_PXPES(3) = 0x00003f00; \ 2728 } while (0) 2729 2730 /* 2731 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR 2732 */ 2733 #define __gpio_as_ssi() \ 2734 do { \ 2735 REG_GPIO_PXFUNS(3) = 0x003c0000; \ 2736 REG_GPIO_PXSELC(3) = 0x003c0000; \ 2737 REG_GPIO_PXPES(3) = 0x003c0000; \ 2738 } while (0) 2739 2740 /* 2741 * I2C_SCK, I2C_SDA 2742 */ 2743 #define __gpio_as_i2c() \ 2744 do { \ 2745 REG_GPIO_PXFUNS(3) = 0x01800000; \ 2746 REG_GPIO_PXSELS(3) = 0x01800000; \ 2747 REG_GPIO_PXPES(3) = 0x01800000; \ 2748 } while (0) 2749 2750 /* 2751 * PWM0 2752 */ 2753 #define __gpio_as_pwm0() \ 2754 do { \ 2755 REG_GPIO_PXFUNS(3) = 0x00800000; \ 2756 REG_GPIO_PXSELC(3) = 0x00800000; \ 2757 REG_GPIO_PXPES(3) = 0x00800000; \ 2758 } while (0) 2759 2760 /* 2761 * PWM1 2762 */ 2763 #define __gpio_as_pwm1() \ 2764 do { \ 2765 REG_GPIO_PXFUNS(3) = 0x01000000; \ 2766 REG_GPIO_PXSELC(3) = 0x01000000; \ 2767 REG_GPIO_PXPES(3) = 0x01000000; \ 2768 } while (0) 2769 2770 /* 2771 * PWM2 2772 */ 2773 #define __gpio_as_pwm2() \ 2774 do { \ 2775 REG_GPIO_PXFUNS(3) = 0x02000000; \ 2776 REG_GPIO_PXSELC(3) = 0x02000000; \ 2777 REG_GPIO_PXPES(3) = 0x02000000; \ 2778 } while (0) 2779 2780 /* 2781 * PWM3 2782 */ 2783 #define __gpio_as_pwm3() \ 2784 do { \ 2785 REG_GPIO_PXFUNS(3) = 0x04000000; \ 2786 REG_GPIO_PXSELC(3) = 0x04000000; \ 2787 REG_GPIO_PXPES(3) = 0x04000000; \ 2788 } while (0) 2789 2790 /* 2791 * PWM4 2792 */ 2793 #define __gpio_as_pwm4() \ 2794 do { \ 2795 REG_GPIO_PXFUNS(3) = 0x08000000; \ 2796 REG_GPIO_PXSELC(3) = 0x08000000; \ 2797 REG_GPIO_PXPES(3) = 0x08000000; \ 2798 } while (0) 2799 2800 /* 2801 * PWM5 2802 */ 2803 #define __gpio_as_pwm5() \ 2804 do { \ 2805 REG_GPIO_PXFUNS(3) = 0x10000000; \ 2806 REG_GPIO_PXSELC(3) = 0x10000000; \ 2807 REG_GPIO_PXPES(3) = 0x10000000; \ 2808 } while (0) 2809 2810 /* 2811 * PWM6 2812 */ 2813 #define __gpio_as_pwm6() \ 2814 do { \ 2815 REG_GPIO_PXFUNS(3) = 0x40000000; \ 2816 REG_GPIO_PXSELC(3) = 0x40000000; \ 2817 REG_GPIO_PXPES(3) = 0x40000000; \ 2818 } while (0) 2819 2820 /* 2821 * PWM7 2822 */ 2823 #define __gpio_as_pwm7() \ 2824 do { \ 2825 REG_GPIO_PXFUNS(3) = 0x80000000; \ 2826 REG_GPIO_PXSELC(3) = 0x80000000; \ 2827 REG_GPIO_PXPES(3) = 0x80000000; \ 2828 } while (0) 2829 2830 /* 2831 * n = 0 ~ 7 2832 */ 2833 #define __gpio_as_pwm(n) __gpio_as_pwm##n() 2834 2835 /* GPIO or Interrupt Mode */ 2836 2837 #define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) 2838 2839 #define __gpio_port_as_output(p, o) \ 2840 do { \ 2841 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 2842 REG_GPIO_PXSELC(p) = (1 << (o)); \ 2843 REG_GPIO_PXDIRS(p) = (1 << (o)); \ 2844 } while (0) 2845 2846 #define __gpio_port_as_input(p, o) \ 2847 do { \ 2848 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 2849 REG_GPIO_PXSELC(p) = (1 << (o)); \ 2850 REG_GPIO_PXDIRC(p) = (1 << (o)); \ 2851 } while (0) 2852 2853 #define __gpio_as_output(n) \ 2854 do { \ 2855 unsigned int p, o; \ 2856 p = (n) / 32; \ 2857 o = (n) % 32; \ 2858 __gpio_port_as_output(p, o); \ 2859 } while (0) 2860 2861 #define __gpio_as_input(n) \ 2862 do { \ 2863 unsigned int p, o; \ 2864 p = (n) / 32; \ 2865 o = (n) % 32; \ 2866 __gpio_port_as_input(p, o); \ 2867 } while (0) 2868 2869 #define __gpio_set_pin(n) \ 2870 do { \ 2871 unsigned int p, o; \ 2872 p = (n) / 32; \ 2873 o = (n) % 32; \ 2874 REG_GPIO_PXDATS(p) = (1 << o); \ 2875 } while (0) 2876 2877 #define __gpio_clear_pin(n) \ 2878 do { \ 2879 unsigned int p, o; \ 2880 p = (n) / 32; \ 2881 o = (n) % 32; \ 2882 REG_GPIO_PXDATC(p) = (1 << o); \ 2883 } while (0) 2884 2885 #define __gpio_get_pin(n) \ 2886 ({ \ 2887 unsigned int p, o, v; \ 2888 p = (n) / 32; \ 2889 o = (n) % 32; \ 2890 if (__gpio_get_port(p) & (1 << o)) \ 2891 v = 1; \ 2892 else \ 2893 v = 0; \ 2894 v; \ 2895 }) 2896 2897 #define __gpio_as_irq_high_level(n) \ 2898 do { \ 2899 unsigned int p, o; \ 2900 p = (n) / 32; \ 2901 o = (n) % 32; \ 2902 REG_GPIO_PXIMS(p) = (1 << o); \ 2903 REG_GPIO_PXTRGC(p) = (1 << o); \ 2904 REG_GPIO_PXFUNC(p) = (1 << o); \ 2905 REG_GPIO_PXSELS(p) = (1 << o); \ 2906 REG_GPIO_PXDIRS(p) = (1 << o); \ 2907 REG_GPIO_PXFLGC(p) = (1 << o); \ 2908 REG_GPIO_PXIMC(p) = (1 << o); \ 2909 } while (0) 2910 2911 #define __gpio_as_irq_low_level(n) \ 2912 do { \ 2913 unsigned int p, o; \ 2914 p = (n) / 32; \ 2915 o = (n) % 32; \ 2916 REG_GPIO_PXIMS(p) = (1 << o); \ 2917 REG_GPIO_PXTRGC(p) = (1 << o); \ 2918 REG_GPIO_PXFUNC(p) = (1 << o); \ 2919 REG_GPIO_PXSELS(p) = (1 << o); \ 2920 REG_GPIO_PXDIRC(p) = (1 << o); \ 2921 REG_GPIO_PXFLGC(p) = (1 << o); \ 2922 REG_GPIO_PXIMC(p) = (1 << o); \ 2923 } while (0) 2924 2925 #define __gpio_as_irq_rise_edge(n) \ 2926 do { \ 2927 unsigned int p, o; \ 2928 p = (n) / 32; \ 2929 o = (n) % 32; \ 2930 REG_GPIO_PXIMS(p) = (1 << o); \ 2931 REG_GPIO_PXTRGS(p) = (1 << o); \ 2932 REG_GPIO_PXFUNC(p) = (1 << o); \ 2933 REG_GPIO_PXSELS(p) = (1 << o); \ 2934 REG_GPIO_PXDIRS(p) = (1 << o); \ 2935 REG_GPIO_PXFLGC(p) = (1 << o); \ 2936 REG_GPIO_PXIMC(p) = (1 << o); \ 2937 } while (0) 2938 2939 #define __gpio_as_irq_fall_edge(n) \ 2940 do { \ 2941 unsigned int p, o; \ 2942 p = (n) / 32; \ 2943 o = (n) % 32; \ 2944 REG_GPIO_PXIMS(p) = (1 << o); \ 2945 REG_GPIO_PXTRGS(p) = (1 << o); \ 2946 REG_GPIO_PXFUNC(p) = (1 << o); \ 2947 REG_GPIO_PXSELS(p) = (1 << o); \ 2948 REG_GPIO_PXDIRC(p) = (1 << o); \ 2949 REG_GPIO_PXFLGC(p) = (1 << o); \ 2950 REG_GPIO_PXIMC(p) = (1 << o); \ 2951 } while (0) 2952 2953 #define __gpio_mask_irq(n) \ 2954 do { \ 2955 unsigned int p, o; \ 2956 p = (n) / 32; \ 2957 o = (n) % 32; \ 2958 REG_GPIO_PXIMS(p) = (1 << o); \ 2959 } while (0) 2960 2961 #define __gpio_unmask_irq(n) \ 2962 do { \ 2963 unsigned int p, o; \ 2964 p = (n) / 32; \ 2965 o = (n) % 32; \ 2966 REG_GPIO_PXIMC(p) = (1 << o); \ 2967 } while (0) 2968 2969 #define __gpio_ack_irq(n) \ 2970 do { \ 2971 unsigned int p, o; \ 2972 p = (n) / 32; \ 2973 o = (n) % 32; \ 2974 REG_GPIO_PXFLGC(p) = (1 << o); \ 2975 } while (0) 2976 2977 #define __gpio_get_irq() \ 2978 ({ \ 2979 unsigned int p, i, tmp, v = 0; \ 2980 for (p = 3; p >= 0; p--) { \ 2981 tmp = REG_GPIO_PXFLG(p); \ 2982 for (i = 0; i < 32; i++) \ 2983 if (tmp & (1 << i)) \ 2984 v = (32*p + i); \ 2985 } \ 2986 v; \ 2987 }) 2988 2989 #define __gpio_group_irq(n) \ 2990 ({ \ 2991 register int tmp, i; \ 2992 tmp = REG_GPIO_PXFLG((n)); \ 2993 for (i=31;i>=0;i--) \ 2994 if (tmp & (1 << i)) \ 2995 break; \ 2996 i; \ 2997 }) 2998 2999 #define __gpio_enable_pull(n) \ 3000 do { \ 3001 unsigned int p, o; \ 3002 p = (n) / 32; \ 3003 o = (n) % 32; \ 3004 REG_GPIO_PXPEC(p) = (1 << o); \ 3005 } while (0) 3006 3007 #define __gpio_disable_pull(n) \ 3008 do { \ 3009 unsigned int p, o; \ 3010 p = (n) / 32; \ 3011 o = (n) % 32; \ 3012 REG_GPIO_PXPES(p) = (1 << o); \ 3013 } while (0) 3014 3015 3016 /*************************************************************************** 3017 * CPM 3018 ***************************************************************************/ 3019 3020 /* Register operations using absolute positioning have been removed. */ 3021 3022 /* 3023 * TCU 3024 */ 3025 /* where 'n' is the TCU channel */ 3026 #define __tcu_select_extalclk(n) \ 3027 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) 3028 #define __tcu_select_rtcclk(n) \ 3029 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) 3030 #define __tcu_select_pclk(n) \ 3031 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) 3032 3033 #define __tcu_select_clk_div1(n) \ 3034 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) 3035 #define __tcu_select_clk_div4(n) \ 3036 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) 3037 #define __tcu_select_clk_div16(n) \ 3038 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) 3039 #define __tcu_select_clk_div64(n) \ 3040 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) 3041 #define __tcu_select_clk_div256(n) \ 3042 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) 3043 #define __tcu_select_clk_div1024(n) \ 3044 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) 3045 3046 #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) 3047 #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) 3048 3049 #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) 3050 #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) 3051 3052 #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) 3053 #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) 3054 3055 #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) 3056 #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) 3057 3058 #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) 3059 #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) 3060 #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) 3061 #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) 3062 #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) 3063 #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) 3064 #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) 3065 #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) 3066 #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) 3067 #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) 3068 3069 #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) 3070 #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) 3071 3072 #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) 3073 #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) 3074 3075 #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) 3076 #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) 3077 3078 #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) 3079 #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) 3080 #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) 3081 #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) 3082 3083 3084 /*************************************************************************** 3085 * WDT 3086 ***************************************************************************/ 3087 #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) 3088 #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) 3089 #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) 3090 #define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) 3091 3092 #define __wdt_select_extalclk() \ 3093 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) 3094 #define __wdt_select_rtcclk() \ 3095 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) 3096 #define __wdt_select_pclk() \ 3097 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) 3098 3099 #define __wdt_select_clk_div1() \ 3100 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) 3101 #define __wdt_select_clk_div4() \ 3102 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) 3103 #define __wdt_select_clk_div16() \ 3104 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) 3105 #define __wdt_select_clk_div64() \ 3106 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) 3107 #define __wdt_select_clk_div256() \ 3108 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) 3109 #define __wdt_select_clk_div1024() \ 3110 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) 3111 3112 3113 /*************************************************************************** 3114 * UART 3115 ***************************************************************************/ 3116 3117 #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) 3118 #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) 3119 3120 #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) 3121 #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) 3122 3123 #define __uart_enable_receive_irq() \ 3124 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) 3125 #define __uart_disable_receive_irq() \ 3126 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) 3127 3128 #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) 3129 #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) 3130 3131 #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) 3132 3133 #define __uart_set_baud(devclk, baud) \ 3134 do { \ 3135 REG8(UART0_LCR) |= UARTLCR_DLAB; \ 3136 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ 3137 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ 3138 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ 3139 } while (0) 3140 3141 #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) 3142 #define __uart_clear_errors() \ 3143 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) 3144 3145 #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) 3146 #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) 3147 #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) 3148 #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3149 #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3150 #define __uart_receive_char() REG8(UART0_RDR) 3151 #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) 3152 #define __uart_enable_irda() \ 3153 /* Tx high pulse as 0, Rx low pulse as 0 */ \ 3154 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) 3155 3156 3157 /*************************************************************************** 3158 * DMAC 3159 ***************************************************************************/ 3160 3161 /* n is the DMA channel (0 - 5) */ 3162 3163 #define __dmac_enable_module() \ 3164 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) 3165 #define __dmac_disable_module() \ 3166 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) 3167 3168 /* p=0,1,2,3 */ 3169 #define __dmac_set_priority(p) \ 3170 do { \ 3171 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ 3172 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ 3173 } while (0) 3174 3175 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) 3176 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) 3177 3178 #define __dmac_enable_descriptor(n) \ 3179 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) 3180 #define __dmac_disable_descriptor(n) \ 3181 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) 3182 3183 #define __dmac_enable_channel(n) \ 3184 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) 3185 #define __dmac_disable_channel(n) \ 3186 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) 3187 #define __dmac_channel_enabled(n) \ 3188 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) 3189 3190 #define __dmac_channel_enable_irq(n) \ 3191 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) 3192 #define __dmac_channel_disable_irq(n) \ 3193 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) 3194 3195 #define __dmac_channel_transmit_halt_detected(n) \ 3196 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) 3197 #define __dmac_channel_transmit_end_detected(n) \ 3198 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) 3199 #define __dmac_channel_address_error_detected(n) \ 3200 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) 3201 #define __dmac_channel_count_terminated_detected(n) \ 3202 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) 3203 #define __dmac_channel_descriptor_invalid_detected(n) \ 3204 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) 3205 3206 #define __dmac_channel_clear_transmit_halt(n) \ 3207 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) 3208 #define __dmac_channel_clear_transmit_end(n) \ 3209 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) 3210 #define __dmac_channel_clear_address_error(n) \ 3211 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) 3212 #define __dmac_channel_clear_count_terminated(n) \ 3213 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) 3214 #define __dmac_channel_clear_descriptor_invalid(n) \ 3215 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) 3216 3217 #define __dmac_channel_set_single_mode(n) \ 3218 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) 3219 #define __dmac_channel_set_block_mode(n) \ 3220 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) 3221 3222 #define __dmac_channel_set_transfer_unit_32bit(n) \ 3223 do { \ 3224 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3225 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ 3226 } while (0) 3227 3228 #define __dmac_channel_set_transfer_unit_16bit(n) \ 3229 do { \ 3230 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3231 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ 3232 } while (0) 3233 3234 #define __dmac_channel_set_transfer_unit_8bit(n) \ 3235 do { \ 3236 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3237 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ 3238 } while (0) 3239 3240 #define __dmac_channel_set_transfer_unit_16byte(n) \ 3241 do { \ 3242 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3243 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ 3244 } while (0) 3245 3246 #define __dmac_channel_set_transfer_unit_32byte(n) \ 3247 do { \ 3248 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3249 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ 3250 } while (0) 3251 3252 /* w=8,16,32 */ 3253 #define __dmac_channel_set_dest_port_width(n,w) \ 3254 do { \ 3255 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ 3256 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ 3257 } while (0) 3258 3259 /* w=8,16,32 */ 3260 #define __dmac_channel_set_src_port_width(n,w) \ 3261 do { \ 3262 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ 3263 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ 3264 } while (0) 3265 3266 /* v=0-15 */ 3267 #define __dmac_channel_set_rdil(n,v) \ 3268 do { \ 3269 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ 3270 REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ 3271 } while (0) 3272 3273 #define __dmac_channel_dest_addr_fixed(n) \ 3274 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) 3275 #define __dmac_channel_dest_addr_increment(n) \ 3276 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) 3277 3278 #define __dmac_channel_src_addr_fixed(n) \ 3279 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) 3280 #define __dmac_channel_src_addr_increment(n) \ 3281 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) 3282 3283 #define __dmac_channel_set_doorbell(n) \ 3284 ( REG_DMAC_DMADBSR = (1 << (n)) ) 3285 3286 #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) 3287 #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) 3288 3289 static __inline__ int __dmac_get_irq(void) 3290 { 3291 int i; 3292 for (i = 0; i < MAX_DMA_NUM; i++) 3293 if (__dmac_channel_irq_detected(i)) 3294 return i; 3295 return -1; 3296 } 3297 3298 3299 /*************************************************************************** 3300 * AIC (AC'97 & I2S Controller) 3301 ***************************************************************************/ 3302 3303 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 3304 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 3305 3306 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 3307 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 3308 3309 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 3310 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 3311 #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) 3312 3313 #define __aic_reset() \ 3314 do { \ 3315 REG_AIC_FR |= AIC_FR_RST; \ 3316 } while(0) 3317 3318 3319 #define __aic_set_transmit_trigger(n) \ 3320 do { \ 3321 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 3322 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ 3323 } while(0) 3324 3325 #define __aic_set_receive_trigger(n) \ 3326 do { \ 3327 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 3328 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ 3329 } while(0) 3330 3331 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 3332 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 3333 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 3334 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 3335 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 3336 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 3337 3338 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) 3339 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) 3340 3341 #define __aic_enable_transmit_intr() \ 3342 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 3343 #define __aic_disable_transmit_intr() \ 3344 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 3345 #define __aic_enable_receive_intr() \ 3346 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 3347 #define __aic_disable_receive_intr() \ 3348 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 3349 3350 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 3351 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 3352 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 3353 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 3354 3355 #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) 3356 #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) 3357 #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) 3358 #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) 3359 #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) 3360 #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) 3361 3362 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 3363 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 3364 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 3365 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 3366 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 3367 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 3368 3369 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 3370 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 3371 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 3372 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 3373 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 3374 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 3375 3376 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 3377 #define __ac97_set_xs_mono() \ 3378 do { \ 3379 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3380 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 3381 } while(0) 3382 #define __ac97_set_xs_stereo() \ 3383 do { \ 3384 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3385 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 3386 } while(0) 3387 3388 /* In fact, only stereo is support now. */ 3389 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 3390 #define __ac97_set_rs_mono() \ 3391 do { \ 3392 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3393 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 3394 } while(0) 3395 #define __ac97_set_rs_stereo() \ 3396 do { \ 3397 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3398 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 3399 } while(0) 3400 3401 #define __ac97_warm_reset_codec() \ 3402 do { \ 3403 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 3404 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 3405 udelay(2); \ 3406 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 3407 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 3408 } while (0) 3409 3410 #define __ac97_cold_reset_codec() \ 3411 do { \ 3412 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 3413 udelay(2); \ 3414 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 3415 } while (0) 3416 3417 /* n=8,16,18,20 */ 3418 #define __ac97_set_iass(n) \ 3419 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 3420 #define __ac97_set_oass(n) \ 3421 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 3422 3423 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 3424 #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 3425 3426 /* n=8,16,18,20,24 */ 3427 /*#define __i2s_set_sample_size(n) \ 3428 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ 3429 3430 #define __i2s_set_oss_sample_size(n) \ 3431 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) 3432 #define __i2s_set_iss_sample_size(n) \ 3433 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) 3434 3435 #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 3436 #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 3437 3438 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 3439 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 3440 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 3441 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 3442 3443 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 3444 3445 #define __aic_get_transmit_resident() \ 3446 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) 3447 #define __aic_get_receive_count() \ 3448 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) 3449 3450 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 3451 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 3452 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 3453 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 3454 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 3455 #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) 3456 #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) 3457 3458 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 3459 3460 #define CODEC_READ_CMD (1 << 19) 3461 #define CODEC_WRITE_CMD (0 << 19) 3462 #define CODEC_REG_INDEX_BIT 12 3463 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ 3464 #define CODEC_REG_DATA_BIT 4 3465 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ 3466 3467 #define __ac97_out_rcmd_addr(reg) \ 3468 do { \ 3469 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3470 } while (0) 3471 3472 #define __ac97_out_wcmd_addr(reg) \ 3473 do { \ 3474 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3475 } while (0) 3476 3477 #define __ac97_out_data(value) \ 3478 do { \ 3479 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ 3480 } while (0) 3481 3482 #define __ac97_in_data() \ 3483 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) 3484 3485 #define __ac97_in_status_addr() \ 3486 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) 3487 3488 #define __i2s_set_sample_rate(i2sclk, sync) \ 3489 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 3490 3491 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 3492 #define __aic_read_rfifo() ( REG_AIC_DR ) 3493 3494 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) 3495 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) 3496 3497 /* Define next ops for AC97 compatible */ 3498 3499 #define AC97_ACSR AIC_ACSR 3500 3501 #define __ac97_enable() __aic_enable(); __aic_select_ac97() 3502 #define __ac97_disable() __aic_disable() 3503 #define __ac97_reset() __aic_reset() 3504 3505 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3506 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 3507 3508 #define __ac97_enable_record() __aic_enable_record() 3509 #define __ac97_disable_record() __aic_disable_record() 3510 #define __ac97_enable_replay() __aic_enable_replay() 3511 #define __ac97_disable_replay() __aic_disable_replay() 3512 #define __ac97_enable_loopback() __aic_enable_loopback() 3513 #define __ac97_disable_loopback() __aic_disable_loopback() 3514 3515 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 3516 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 3517 #define __ac97_enable_receive_dma() __aic_enable_receive_dma() 3518 #define __ac97_disable_receive_dma() __aic_disable_receive_dma() 3519 3520 #define __ac97_transmit_request() __aic_transmit_request() 3521 #define __ac97_receive_request() __aic_receive_request() 3522 #define __ac97_transmit_underrun() __aic_transmit_underrun() 3523 #define __ac97_receive_overrun() __aic_receive_overrun() 3524 3525 #define __ac97_clear_errors() __aic_clear_errors() 3526 3527 #define __ac97_get_transmit_resident() __aic_get_transmit_resident() 3528 #define __ac97_get_receive_count() __aic_get_receive_count() 3529 3530 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 3531 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 3532 #define __ac97_enable_receive_intr() __aic_enable_receive_intr() 3533 #define __ac97_disable_receive_intr() __aic_disable_receive_intr() 3534 3535 #define __ac97_write_tfifo(v) __aic_write_tfifo(v) 3536 #define __ac97_read_rfifo() __aic_read_rfifo() 3537 3538 /* Define next ops for I2S compatible */ 3539 3540 #define I2S_ACSR AIC_I2SSR 3541 3542 #define __i2s_enable() __aic_enable(); __aic_select_i2s() 3543 #define __i2s_disable() __aic_disable() 3544 #define __i2s_reset() __aic_reset() 3545 3546 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3547 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 3548 3549 #define __i2s_enable_record() __aic_enable_record() 3550 #define __i2s_disable_record() __aic_disable_record() 3551 #define __i2s_enable_replay() __aic_enable_replay() 3552 #define __i2s_disable_replay() __aic_disable_replay() 3553 #define __i2s_enable_loopback() __aic_enable_loopback() 3554 #define __i2s_disable_loopback() __aic_disable_loopback() 3555 3556 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 3557 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 3558 #define __i2s_enable_receive_dma() __aic_enable_receive_dma() 3559 #define __i2s_disable_receive_dma() __aic_disable_receive_dma() 3560 3561 #define __i2s_transmit_request() __aic_transmit_request() 3562 #define __i2s_receive_request() __aic_receive_request() 3563 #define __i2s_transmit_underrun() __aic_transmit_underrun() 3564 #define __i2s_receive_overrun() __aic_receive_overrun() 3565 3566 #define __i2s_clear_errors() __aic_clear_errors() 3567 3568 #define __i2s_get_transmit_resident() __aic_get_transmit_resident() 3569 #define __i2s_get_receive_count() __aic_get_receive_count() 3570 3571 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 3572 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 3573 #define __i2s_enable_receive_intr() __aic_enable_receive_intr() 3574 #define __i2s_disable_receive_intr() __aic_disable_receive_intr() 3575 3576 #define __i2s_write_tfifo(v) __aic_write_tfifo(v) 3577 #define __i2s_read_rfifo() __aic_read_rfifo() 3578 3579 #define __i2s_reset_codec() \ 3580 do { \ 3581 } while (0) 3582 3583 3584 /*************************************************************************** 3585 * ICDC 3586 ***************************************************************************/ 3587 #define __i2s_internal_codec() __aic_internal_codec() 3588 #define __i2s_external_codec() __aic_external_codec() 3589 3590 /*************************************************************************** 3591 * INTC 3592 ***************************************************************************/ 3593 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) 3594 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) 3595 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) 3596 3597 3598 /*************************************************************************** 3599 * I2C 3600 ***************************************************************************/ 3601 3602 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) 3603 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) 3604 3605 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) 3606 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) 3607 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) 3608 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) 3609 3610 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) 3611 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) 3612 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) 3613 3614 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) 3615 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) 3616 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) 3617 3618 #define __i2c_set_clk(dev_clk, i2c_clk) \ 3619 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) 3620 3621 #define __i2c_read() ( REG_I2C_DR ) 3622 #define __i2c_write(val) ( REG_I2C_DR = (val) ) 3623 3624 3625 /*************************************************************************** 3626 * MSC 3627 ***************************************************************************/ 3628 3629 #define __msc_start_op() \ 3630 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) 3631 3632 #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) 3633 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) 3634 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) 3635 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) 3636 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) 3637 #define __msc_get_nob() ( REG_MSC_NOB ) 3638 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) 3639 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) 3640 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) 3641 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) 3642 3643 #define __msc_set_cmdat_bus_width1() \ 3644 do { \ 3645 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 3646 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ 3647 } while(0) 3648 3649 #define __msc_set_cmdat_bus_width4() \ 3650 do { \ 3651 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 3652 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ 3653 } while(0) 3654 3655 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) 3656 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) 3657 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) 3658 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) 3659 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) 3660 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) 3661 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) 3662 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) 3663 3664 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ 3665 #define __msc_set_cmdat_res_format(r) \ 3666 do { \ 3667 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ 3668 REG_MSC_CMDAT |= (r); \ 3669 } while(0) 3670 3671 #define __msc_clear_cmdat() \ 3672 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ 3673 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ 3674 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) 3675 3676 #define __msc_get_imask() ( REG_MSC_IMASK ) 3677 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) 3678 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) 3679 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) 3680 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) 3681 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) 3682 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) 3683 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) 3684 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) 3685 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) 3686 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) 3687 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) 3688 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) 3689 3690 /* n=0,1,2,3,4,5,6,7 */ 3691 #define __msc_set_clkrt(n) \ 3692 do { \ 3693 REG_MSC_CLKRT = n; \ 3694 } while(0) 3695 3696 #define __msc_get_ireg() ( REG_MSC_IREG ) 3697 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) 3698 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) 3699 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) 3700 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) 3701 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) 3702 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) 3703 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) 3704 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) 3705 3706 #define __msc_get_stat() ( REG_MSC_STAT ) 3707 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) 3708 #define __msc_stat_crc_err() \ 3709 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) 3710 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) 3711 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) 3712 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) 3713 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) 3714 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) 3715 3716 #define __msc_rd_resfifo() ( REG_MSC_RES ) 3717 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 3718 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 3719 3720 #define __msc_reset() \ 3721 do { \ 3722 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 3723 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 3724 } while (0) 3725 3726 #define __msc_start_clk() \ 3727 do { \ 3728 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ 3729 } while (0) 3730 3731 #define __msc_stop_clk() \ 3732 do { \ 3733 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ 3734 } while (0) 3735 3736 #define MMC_CLK 19169200 3737 #define SD_CLK 24576000 3738 3739 /* msc_clk should little than pclk and little than clk retrieve from card */ 3740 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ 3741 do { \ 3742 unsigned int rate, pclk, i; \ 3743 pclk = dev_clk; \ 3744 rate = type?SD_CLK:MMC_CLK; \ 3745 if (msc_clk && msc_clk < pclk) \ 3746 pclk = msc_clk; \ 3747 i = 0; \ 3748 while (pclk < rate) \ 3749 { \ 3750 i ++; \ 3751 rate >>= 1; \ 3752 } \ 3753 lv = i; \ 3754 } while(0) 3755 3756 /* divide rate to little than or equal to 400kHz */ 3757 #define __msc_calc_slow_clk_divisor(type, lv) \ 3758 do { \ 3759 unsigned int rate, i; \ 3760 rate = (type?SD_CLK:MMC_CLK)/1000/400; \ 3761 i = 0; \ 3762 while (rate > 0) \ 3763 { \ 3764 rate >>= 1; \ 3765 i ++; \ 3766 } \ 3767 lv = i; \ 3768 } while(0) 3769 3770 3771 /*************************************************************************** 3772 * SSI 3773 ***************************************************************************/ 3774 3775 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) 3776 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) 3777 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) 3778 3779 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) 3780 3781 #define __ssi_select_ce2() \ 3782 do { \ 3783 REG_SSI_CR0 |= SSI_CR0_FSEL; \ 3784 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ 3785 } while (0) 3786 3787 #define __ssi_select_gpc() \ 3788 do { \ 3789 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ 3790 REG_SSI_CR1 |= SSI_CR1_MULTS; \ 3791 } while (0) 3792 3793 #define __ssi_enable_tx_intr() \ 3794 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) 3795 3796 #define __ssi_disable_tx_intr() \ 3797 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) 3798 3799 #define __ssi_enable_rx_intr() \ 3800 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) 3801 3802 #define __ssi_disable_rx_intr() \ 3803 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) 3804 3805 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) 3806 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) 3807 3808 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) 3809 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) 3810 3811 #define __ssi_finish_receive() \ 3812 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) 3813 3814 #define __ssi_disable_recvfinish() \ 3815 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) 3816 3817 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) 3818 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) 3819 3820 #define __ssi_flush_fifo() \ 3821 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) 3822 3823 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) 3824 3825 #define __ssi_spi_format() \ 3826 do { \ 3827 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 3828 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ 3829 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 3830 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ 3831 } while (0) 3832 3833 /* TI's SSP format, must clear SSI_CR1.UNFIN */ 3834 #define __ssi_ssp_format() \ 3835 do { \ 3836 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ 3837 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ 3838 } while (0) 3839 3840 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ 3841 #define __ssi_microwire_format() \ 3842 do { \ 3843 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 3844 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ 3845 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 3846 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ 3847 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ 3848 } while (0) 3849 3850 /* CE# level (FRMHL), CE# in interval time (ITFRM), 3851 clock phase and polarity (PHA POL), 3852 interval time (SSIITR), interval characters/frame (SSIICR) */ 3853 3854 /* frmhl,endian,mcom,flen,pha,pol MASK */ 3855 #define SSICR1_MISC_MASK \ 3856 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ 3857 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ 3858 3859 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ 3860 do { \ 3861 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ 3862 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ 3863 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ 3864 ((pha) << 1) | (pol); \ 3865 } while(0) 3866 3867 /* Transfer with MSB or LSB first */ 3868 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) 3869 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) 3870 3871 #define __ssi_set_frame_length(n) \ 3872 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) 3873 3874 /* n = 1 - 16 */ 3875 #define __ssi_set_microwire_command_length(n) \ 3876 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) 3877 3878 /* Set the clock phase for SPI */ 3879 #define __ssi_set_spi_clock_phase(n) \ 3880 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) 3881 3882 /* Set the clock polarity for SPI */ 3883 #define __ssi_set_spi_clock_polarity(n) \ 3884 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) 3885 3886 /* n = ix8 */ 3887 #define __ssi_set_tx_trigger(n) \ 3888 do { \ 3889 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ 3890 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ 3891 } while (0) 3892 3893 /* n = ix8 */ 3894 #define __ssi_set_rx_trigger(n) \ 3895 do { \ 3896 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ 3897 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ 3898 } while (0) 3899 3900 #define __ssi_get_txfifo_count() \ 3901 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) 3902 3903 #define __ssi_get_rxfifo_count() \ 3904 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) 3905 3906 #define __ssi_clear_errors() \ 3907 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) 3908 3909 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) 3910 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) 3911 3912 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) 3913 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) 3914 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) 3915 3916 #define __ssi_set_clk(dev_clk, ssi_clk) \ 3917 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) 3918 3919 #define __ssi_receive_data() REG_SSI_DR 3920 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) 3921 3922 3923 /*************************************************************************** 3924 * CIM 3925 ***************************************************************************/ 3926 3927 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) 3928 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) 3929 3930 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) 3931 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) 3932 3933 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) 3934 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) 3935 3936 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) 3937 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) 3938 3939 #define __cim_sample_data_at_pclk_falling_edge() \ 3940 ( REG_CIM_CFG |= CIM_CFG_PCP ) 3941 #define __cim_sample_data_at_pclk_rising_edge() \ 3942 ( REG_CIM_CFG &= ~CIM_CFG_PCP ) 3943 3944 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) 3945 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) 3946 3947 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) 3948 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) 3949 3950 /* n=0-7 */ 3951 #define __cim_set_data_packing_mode(n) \ 3952 do { \ 3953 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ 3954 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ 3955 } while (0) 3956 3957 #define __cim_enable_ccir656_progressive_mode() \ 3958 do { \ 3959 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3960 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ 3961 } while (0) 3962 3963 #define __cim_enable_ccir656_interlace_mode() \ 3964 do { \ 3965 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3966 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ 3967 } while (0) 3968 3969 #define __cim_enable_gated_clock_mode() \ 3970 do { \ 3971 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3972 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ 3973 } while (0) 3974 3975 #define __cim_enable_nongated_clock_mode() \ 3976 do { \ 3977 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3978 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ 3979 } while (0) 3980 3981 /* sclk:system bus clock 3982 * mclk: CIM master clock 3983 */ 3984 #define __cim_set_master_clk(sclk, mclk) \ 3985 do { \ 3986 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ 3987 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ 3988 } while (0) 3989 3990 #define __cim_enable_sof_intr() \ 3991 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) 3992 #define __cim_disable_sof_intr() \ 3993 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) 3994 3995 #define __cim_enable_eof_intr() \ 3996 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) 3997 #define __cim_disable_eof_intr() \ 3998 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) 3999 4000 #define __cim_enable_stop_intr() \ 4001 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) 4002 #define __cim_disable_stop_intr() \ 4003 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) 4004 4005 #define __cim_enable_trig_intr() \ 4006 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) 4007 #define __cim_disable_trig_intr() \ 4008 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) 4009 4010 #define __cim_enable_rxfifo_overflow_intr() \ 4011 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) 4012 #define __cim_disable_rxfifo_overflow_intr() \ 4013 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) 4014 4015 /* n=1-16 */ 4016 #define __cim_set_frame_rate(n) \ 4017 do { \ 4018 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ 4019 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ 4020 } while (0) 4021 4022 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) 4023 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) 4024 4025 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) 4026 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) 4027 4028 /* n=4,8,12,16,20,24,28,32 */ 4029 #define __cim_set_rxfifo_trigger(n) \ 4030 do { \ 4031 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ 4032 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ 4033 } while (0) 4034 4035 #define __cim_clear_state() ( REG_CIM_STATE = 0 ) 4036 4037 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) 4038 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) 4039 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) 4040 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) 4041 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) 4042 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) 4043 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) 4044 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) 4045 4046 #define __cim_get_iid() ( REG_CIM_IID ) 4047 #define __cim_get_image_data() ( REG_CIM_RXFIFO ) 4048 #define __cim_get_dam_cmd() ( REG_CIM_CMD ) 4049 4050 #define __cim_set_da(a) ( REG_CIM_DA = (a) ) 4051 4052 /*************************************************************************** 4053 * LCD 4054 ***************************************************************************/ 4055 4056 /* Register operations using absolute positioning have been removed. */ 4057 4058 /*************************************************************************** 4059 * RTC ops 4060 ***************************************************************************/ 4061 4062 #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) 4063 #define __rtc_enabled() \ 4064 do{ \ 4065 while(!__rtc_write_ready()); \ 4066 REG_RTC_RCR |= RTC_RCR_RTCE ; \ 4067 }while(0) \ 4068 4069 #define __rtc_disabled() \ 4070 do{ \ 4071 while(!__rtc_write_ready()); \ 4072 REG_RTC_RCR &= ~RTC_RCR_RTCE; \ 4073 }while(0) 4074 #define __rtc_enable_alarm() \ 4075 do{ \ 4076 while(!__rtc_write_ready()); \ 4077 REG_RTC_RCR |= RTC_RCR_AE; \ 4078 }while(0) 4079 4080 #define __rtc_disable_alarm() \ 4081 do{ \ 4082 while(!__rtc_write_ready()); \ 4083 REG_RTC_RCR &= ~RTC_RCR_AE; \ 4084 }while(0) 4085 4086 #define __rtc_enable_alarm_irq() \ 4087 do{ \ 4088 while(!__rtc_write_ready()); \ 4089 REG_RTC_RCR |= RTC_RCR_AIE; \ 4090 }while(0) 4091 4092 #define __rtc_disable_alarm_irq() \ 4093 do{ \ 4094 while(!__rtc_write_ready()); \ 4095 REG_RTC_RCR &= ~RTC_RCR_AIE; \ 4096 }while(0) 4097 #define __rtc_enable_Hz_irq() \ 4098 do{ \ 4099 while(!__rtc_write_ready()); \ 4100 REG_RTC_RCR |= RTC_RCR_HZIE; \ 4101 }while(0) 4102 4103 #define __rtc_disable_Hz_irq() \ 4104 do{ \ 4105 while(!__rtc_write_ready()); \ 4106 REG_RTC_RCR &= ~RTC_RCR_HZIE; \ 4107 }while(0) 4108 #define __rtc_get_1Hz_flag() \ 4109 do{ \ 4110 while(!__rtc_write_ready()); \ 4111 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ 4112 }while(0) 4113 #define __rtc_clear_1Hz_flag() \ 4114 do{ \ 4115 while(!__rtc_write_ready()); \ 4116 REG_RTC_RCR &= ~RTC_RCR_HZ; \ 4117 }while(0) 4118 #define __rtc_get_alarm_flag() \ 4119 do{ \ 4120 while(!__rtc_write_ready()); \ 4121 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \ 4122 while(0) 4123 #define __rtc_clear_alarm_flag() \ 4124 do{ \ 4125 while(!__rtc_write_ready()); \ 4126 REG_RTC_RCR &= ~RTC_RCR_AF; \ 4127 }while(0) 4128 #define __rtc_get_second() \ 4129 do{ \ 4130 while(!__rtc_write_ready());\ 4131 REG_RTC_RSR; \ 4132 }while(0) 4133 4134 #define __rtc_set_second(v) \ 4135 do{ \ 4136 while(!__rtc_write_ready()); \ 4137 REG_RTC_RSR = v; \ 4138 }while(0) 4139 4140 #define __rtc_get_alarm_second() \ 4141 do{ \ 4142 while(!__rtc_write_ready()); \ 4143 REG_RTC_RSAR; \ 4144 }while(0) 4145 4146 4147 #define __rtc_set_alarm_second(v) \ 4148 do{ \ 4149 while(!__rtc_write_ready()); \ 4150 REG_RTC_RSAR = v; \ 4151 }while(0) 4152 4153 #define __rtc_RGR_is_locked() \ 4154 do{ \ 4155 while(!__rtc_write_ready()); \ 4156 REG_RTC_RGR >> RTC_RGR_LOCK; \ 4157 }while(0) 4158 #define __rtc_lock_RGR() \ 4159 do{ \ 4160 while(!__rtc_write_ready()); \ 4161 REG_RTC_RGR |= RTC_RGR_LOCK; \ 4162 }while(0) 4163 4164 #define __rtc_unlock_RGR() \ 4165 do{ \ 4166 while(!__rtc_write_ready()); \ 4167 REG_RTC_RGR &= ~RTC_RGR_LOCK; \ 4168 }while(0) 4169 4170 #define __rtc_get_adjc_val() \ 4171 do{ \ 4172 while(!__rtc_write_ready()); \ 4173 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ 4174 }while(0) 4175 #define __rtc_set_adjc_val(v) \ 4176 do{ \ 4177 while(!__rtc_write_ready()); \ 4178 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \ 4179 }while(0) 4180 4181 #define __rtc_get_nc1Hz_val() \ 4182 while(!__rtc_write_ready()); \ 4183 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) 4184 4185 #define __rtc_set_nc1Hz_val(v) \ 4186 do{ \ 4187 while(!__rtc_write_ready()); \ 4188 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \ 4189 }while(0) 4190 #define __rtc_power_down() \ 4191 do{ \ 4192 while(!__rtc_write_ready()); \ 4193 REG_RTC_HCR |= RTC_HCR_PD; \ 4194 }while(0) 4195 4196 #define __rtc_get_hwfcr_val() \ 4197 do{ \ 4198 while(!__rtc_write_ready()); \ 4199 REG_RTC_HWFCR & RTC_HWFCR_MASK; \ 4200 }while(0) 4201 #define __rtc_set_hwfcr_val(v) \ 4202 do{ \ 4203 while(!__rtc_write_ready()); \ 4204 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ 4205 }while(0) 4206 4207 #define __rtc_get_hrcr_val() \ 4208 do{ \ 4209 while(!__rtc_write_ready()); \ 4210 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ 4211 }while(0) 4212 #define __rtc_set_hrcr_val(v) \ 4213 do{ \ 4214 while(!__rtc_write_ready()); \ 4215 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ 4216 }while(0) 4217 4218 #define __rtc_enable_alarm_wakeup() \ 4219 do{ \ 4220 while(!__rtc_write_ready()); \ 4221 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ 4222 }while(0) 4223 4224 #define __rtc_disable_alarm_wakeup() \ 4225 do{ \ 4226 while(!__rtc_write_ready()); \ 4227 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ 4228 }while(0) 4229 4230 #define __rtc_status_hib_reset_occur() \ 4231 do{ \ 4232 while(!__rtc_write_ready()); \ 4233 ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \ 4234 }while(0) 4235 #define __rtc_status_ppr_reset_occur() \ 4236 do{ \ 4237 while(!__rtc_write_ready()); \ 4238 ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \ 4239 }while(0) 4240 #define __rtc_status_wakeup_pin_waken_up() \ 4241 do{ \ 4242 while(!__rtc_write_ready()); \ 4243 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ 4244 }while(0) 4245 #define __rtc_status_alarm_waken_up() \ 4246 do{ \ 4247 while(!__rtc_write_ready()); \ 4248 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ 4249 }while(0) 4250 #define __rtc_clear_hib_stat_all() \ 4251 do{ \ 4252 while(!__rtc_write_ready()); \ 4253 ( REG_RTC_HWRSR = 0 ); \ 4254 }while(0) 4255 4256 #define __rtc_get_scratch_pattern() \ 4257 while(!__rtc_write_ready()); \ 4258 (REG_RTC_HSPR) 4259 #define __rtc_set_scratch_pattern(n) \ 4260 do{ \ 4261 while(!__rtc_write_ready()); \ 4262 (REG_RTC_HSPR = n ); \ 4263 }while(0) 4264 4265 4266 #endif /* !__ASSEMBLY__ */ 4267 4268 #endif /* __JZ4740_H__ */