1 /* 2 * CPU-specific routines from U-Boot. 3 * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c 4 * See: u-boot/arch/mips/include/asm/cacheops.h 5 * 6 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include "xburst_types.h" 25 #include "sdram.h" 26 27 void flush_icache_all(void) 28 { 29 u32 addr, t = 0; 30 31 asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ 32 asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ 33 34 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; 35 addr += CONFIG_SYS_CACHELINE_SIZE) { 36 asm volatile ( 37 ".set mips3\n\t" 38 " cache %0, 0(%1)\n\t" 39 ".set mips2\n\t" 40 : 41 : "I" (Index_Store_Tag_I), "r"(addr)); 42 } 43 44 /* invalicate btb */ 45 asm volatile ( 46 ".set mips32\n\t" 47 "mfc0 %0, $16, 7\n\t" 48 "nop\n\t" 49 "ori %0,2\n\t" 50 "mtc0 %0, $16, 7\n\t" 51 ".set mips2\n\t" 52 : 53 : "r" (t)); 54 } 55 56 void flush_dcache_all(void) 57 { 58 u32 addr; 59 60 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; 61 addr += CONFIG_SYS_CACHELINE_SIZE) { 62 asm volatile ( 63 ".set mips3\n\t" 64 " cache %0, 0(%1)\n\t" 65 ".set mips2\n\t" 66 : 67 : "I" (Index_Writeback_Inv_D), "r"(addr)); 68 } 69 70 asm volatile ("sync"); 71 } 72 73 void flush_cache_all(void) 74 { 75 flush_dcache_all(); 76 flush_icache_all(); 77 } 78 79 void handle_error_level(void) 80 { 81 asm volatile( 82 "mfc0 $t3, $12\n" /* CP0_STATUS */ 83 "nop\n" 84 "li $t4, 0xfffffffb\n" /* ERL = 0 */ 85 "and $t3, $t3, $t4\n" 86 "mtc0 $t3, $12\n" 87 "nop\n"); 88 } 89 90 void enable_interrupts(void) 91 { 92 asm volatile( 93 "mfc0 $t3, $12\n" /* CP0_STATUS */ 94 "nop\n" 95 "li $t4, 0x0000fc01\n" /* IE = enable interrupts */ 96 "or $t3, $t3, $t4\n" 97 "mtc0 $t3, $12\n" 98 "nop\n"); 99 } 100 101 void init_interrupts(void) 102 { 103 /* Set exception registers. */ 104 105 asm volatile( 106 "mtc0 $zero, $18\n" /* CP0_WATCHLO */ 107 "nop\n" 108 "li $t3, 0x00800000\n" /* IV = 1 (use 0x80000200 for interrupts) */ 109 "mtc0 $t3, $13\n" /* CP0_CAUSE */ 110 "nop\n" 111 "mtc0 $zero, $12\n" /* CP0_STATUS */ 112 "nop\n"); 113 } 114 115 void init_tlb(void) 116 { 117 asm volatile( 118 "li $t0, 0x001fe000\n" /* 1MB */ 119 "mtc0 $t0, $5\n" /* CP0_PAGEMASK */ 120 "nop\n" 121 "mtc0 $zero, $6\n" /* CP0_WIRED */ 122 "nop\n" 123 124 /* Set physical address. */ 125 126 "li $t0, 0x0000001f\n" /* 0x000000.. C=3, dirty, global, valid */ 127 "mtc0 $t0, $2\n" /* CP0_ENTRYLO0 */ 128 "nop\n" 129 "li $t0, 0x0000001f\n" /* 0x000000.. C=3, dirty, global, valid */ 130 "mtc0 $zero, $3\n" /* CP0_ENTRYLO1 */ 131 "nop\n" 132 133 /* Set virtual address. */ 134 135 "li $t0, 0x80000000\n" /* 0x80000... ASID=0 */ 136 "mtc0 $t0, $10\n" /* CP0_ENTRYHI */ 137 "nop\n" 138 139 "tlbwr\n" 140 "nop"); 141 }