1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "jz4740.h" 24 #include "configs.h" 25 #include "nanonote.h" 26 27 void gpio_init(void) 28 { 29 /* 30 * Initialize NAND Flash Pins 31 */ 32 __gpio_as_nand(); 33 34 /* 35 * Initialize SDRAM pins 36 */ 37 __gpio_as_sdram_32bit(); 38 } 39 40 void gpio_init2(void) 41 { 42 /* 43 * Initialize LCD pins 44 */ 45 __gpio_as_slcd_8bit(); 46 47 /* 48 * Initialize MSC pins 49 */ 50 __gpio_as_msc(); 51 52 /* 53 * Initialize Other pins 54 */ 55 unsigned int i; 56 for (i = 0; i < 7; i++){ 57 __gpio_as_input(GPIO_KEYIN_BASE + i); 58 __gpio_enable_pull(GPIO_KEYIN_BASE + i); 59 } 60 61 for (i = 0; i < 8; i++) { 62 __gpio_as_output(GPIO_KEYOUT_BASE + i); 63 __gpio_clear_pin(GPIO_KEYOUT_BASE + i); 64 } 65 66 /* enable the TP4, TP5 as UART0 */ 67 __gpio_jtag_to_uart0(); 68 69 __gpio_as_input(GPIO_KEYIN_8); 70 __gpio_enable_pull(GPIO_KEYIN_8); 71 72 __gpio_as_output(GPIO_AUDIO_POP); 73 __gpio_set_pin(GPIO_AUDIO_POP); 74 75 __gpio_as_output(GPIO_LCD_CS); 76 __gpio_clear_pin(GPIO_LCD_CS); 77 78 __gpio_as_output(GPIO_AMP_EN); 79 __gpio_clear_pin(GPIO_AMP_EN); 80 81 __gpio_as_output(GPIO_SDPW_EN); 82 __gpio_disable_pull(GPIO_SDPW_EN); 83 __gpio_clear_pin(GPIO_SDPW_EN); 84 85 __gpio_as_input(GPIO_SD_DETECT); 86 __gpio_disable_pull(GPIO_SD_DETECT); 87 88 __gpio_as_input(GPIO_USB_DETECT); 89 __gpio_enable_pull(GPIO_USB_DETECT); 90 } 91 92 void cpm_init(void) 93 { 94 __cpm_stop_ipu(); 95 __cpm_stop_cim(); 96 __cpm_stop_i2c(); 97 __cpm_stop_ssi(); 98 __cpm_stop_uart1(); 99 __cpm_stop_sadc(); 100 __cpm_stop_uhc(); 101 __cpm_stop_udc(); 102 __cpm_stop_aic1(); 103 /* __cpm_stop_aic2();*/ 104 } 105 106 void pll_init(void) 107 { 108 register unsigned int cfcr, plcr1; 109 int n2FR[33] = { 110 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 111 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 112 9 113 }; 114 int nf, pllout2; 115 116 cfcr = CPM_CPCCR_CLKOEN | 117 (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | 118 (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | 119 (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | 120 (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | 121 (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); 122 123 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); 124 125 /* Init USB Host clock, pllout2 must be n*48MHz */ 126 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 127 128 nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; 129 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 130 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 131 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 132 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ 133 CPM_CPPCR_PLLEN; /* enable PLL */ 134 135 /* init PLL */ 136 REG_CPM_CPCCR = cfcr; 137 REG_CPM_CPPCR = plcr1; 138 } 139 140 void sdram_init(void) 141 { 142 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 143 144 unsigned int cas_latency_sdmr[2] = { 145 EMC_SDMR_CAS_2, 146 EMC_SDMR_CAS_3, 147 }; 148 149 unsigned int cas_latency_dmcr[2] = { 150 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 151 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 152 }; 153 154 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 155 156 cpu_clk = CFG_CPU_SPEED; 157 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; 158 159 REG_EMC_BCR = 0; /* Disable bus release */ 160 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 161 162 /* Fault DMCR value for mode register setting*/ 163 #define SDRAM_ROW0 11 164 #define SDRAM_COL0 8 165 #define SDRAM_BANK40 0 166 167 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | 168 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | 169 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | 170 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 171 EMC_DMCR_EPIN | 172 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 173 174 /* Basic DMCR value */ 175 dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | 176 ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | 177 (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | 178 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 179 EMC_DMCR_EPIN | 180 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 181 182 /* SDRAM timimg */ 183 ns = 1000000000 / mem_clk; 184 tmp = SDRAM_TRAS/ns; 185 if (tmp < 4) tmp = 4; 186 if (tmp > 11) tmp = 11; 187 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 188 tmp = SDRAM_RCD/ns; 189 if (tmp > 3) tmp = 3; 190 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 191 tmp = SDRAM_TPC/ns; 192 if (tmp > 7) tmp = 7; 193 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 194 tmp = SDRAM_TRWL/ns; 195 if (tmp > 3) tmp = 3; 196 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 197 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 198 if (tmp > 14) tmp = 14; 199 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 200 201 /* SDRAM mode value */ 202 sdmode = EMC_SDMR_BT_SEQ | 203 EMC_SDMR_OM_NORMAL | 204 EMC_SDMR_BL_4 | 205 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 206 207 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 208 REG_EMC_DMCR = dmcr; 209 REG8(EMC_SDMR0|sdmode) = 0; 210 211 /* Wait for precharge, > 200us */ 212 tmp = (cpu_clk / 1000000) * 1000; 213 while (tmp--); 214 215 /* Stage 2. Enable auto-refresh */ 216 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 217 218 tmp = SDRAM_TREF/ns; 219 tmp = tmp/64 + 1; 220 if (tmp > 0xff) tmp = 0xff; 221 REG_EMC_RTCOR = tmp; 222 REG_EMC_RTCNT = 0; 223 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 224 225 /* Wait for number of auto-refresh cycles */ 226 tmp = (cpu_clk / 1000000) * 1000; 227 while (tmp--); 228 229 /* Stage 3. Mode Register Set */ 230 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 231 REG8(EMC_SDMR0|sdmode) = 0; 232 233 /* Set back to basic DMCR value */ 234 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 235 236 /* everything is ok now */ 237 } 238 239 void rtc_init(void) 240 { 241 while ( !__rtc_write_ready()) ; 242 __rtc_enable_alarm(); /* enable alarm */ 243 244 while ( !__rtc_write_ready()) 245 ; 246 REG_RTC_RGR = 0x00007fff; /* type value */ 247 248 while ( !__rtc_write_ready()) 249 ; 250 REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ 251 252 while ( !__rtc_write_ready()) 253 ; 254 REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ 255 } 256 257 /* 258 * Timer routines 259 */ 260 261 #define TIMER_CHAN 0 262 #define TIMER_FDATA 0xffff /* Timer full data value */ 263 #define TIMER_HZ CONFIG_SYS_HZ 264 265 #define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ 266 267 static unsigned long timestamp; 268 static unsigned long lastdec; 269 270 void reset_timer_masked(void); 271 unsigned long get_timer_masked(void); 272 void udelay_masked(unsigned long usec); 273 274 /* 275 * timer without interrupts 276 */ 277 278 int timer_init(void) 279 { 280 REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; 281 REG_TCU_TCNT(TIMER_CHAN) = 0; 282 REG_TCU_TDHR(TIMER_CHAN) = 0; 283 REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; 284 285 REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ 286 REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ 287 REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ 288 289 lastdec = 0; 290 timestamp = 0; 291 292 return 0; 293 } 294 295 void reset_timer(void) 296 { 297 reset_timer_masked (); 298 } 299 300 unsigned long get_timer(unsigned long base) 301 { 302 return get_timer_masked () - base; 303 } 304 305 void set_timer(unsigned long t) 306 { 307 timestamp = t; 308 } 309 310 void udelay (unsigned long usec) 311 { 312 unsigned long tmo,tmp; 313 314 /* normalize */ 315 if (usec >= 1000) { 316 tmo = usec / 1000; 317 tmo *= TIMER_HZ; 318 tmo /= 1000; 319 } 320 else { 321 if (usec >= 1) { 322 tmo = usec * TIMER_HZ; 323 tmo /= (1000*1000); 324 } 325 else 326 tmo = 1; 327 } 328 329 /* check for rollover during this delay */ 330 tmp = get_timer (0); 331 if ((tmp + tmo) < tmp ) 332 reset_timer_masked(); /* timer would roll over */ 333 else 334 tmo += tmp; 335 336 while (get_timer_masked () < tmo); 337 } 338 339 void reset_timer_masked (void) 340 { 341 /* reset time */ 342 lastdec = READ_TIMER; 343 timestamp = 0; 344 } 345 346 unsigned long get_timer_masked (void) 347 { 348 unsigned long now = READ_TIMER; 349 350 if (lastdec <= now) { 351 /* normal mode */ 352 timestamp += (now - lastdec); 353 } else { 354 /* we have an overflow ... */ 355 timestamp += TIMER_FDATA + now - lastdec; 356 } 357 lastdec = now; 358 359 return timestamp; 360 } 361 362 void udelay_masked (unsigned long usec) 363 { 364 unsigned long tmo; 365 unsigned long endtime; 366 signed long diff; 367 368 /* normalize */ 369 if (usec >= 1000) { 370 tmo = usec / 1000; 371 tmo *= TIMER_HZ; 372 tmo /= 1000; 373 } else { 374 if (usec > 1) { 375 tmo = usec * TIMER_HZ; 376 tmo /= (1000*1000); 377 } else { 378 tmo = 1; 379 } 380 } 381 382 endtime = get_timer_masked () + tmo; 383 384 do { 385 unsigned long now = get_timer_masked (); 386 diff = endtime - now; 387 } while (diff >= 0); 388 } 389 390 /* 391 * This function is derived from PowerPC code (read timebase as long long). 392 * On MIPS it just returns the timer value. 393 */ 394 unsigned long long get_ticks(void) 395 { 396 return get_timer(0); 397 } 398 399 /* 400 * This function is derived from PowerPC code (timebase clock frequency). 401 * On MIPS it returns the number of timer ticks per second. 402 */ 403 unsigned long get_tbclk (void) 404 { 405 return TIMER_HZ; 406 } 407 408 /* CPU-specific routines from U-Boot. 409 See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c 410 See: u-boot/arch/mips/include/asm/cacheops.h 411 */ 412 413 #define Index_Store_Tag_I 0x08 414 #define Index_Writeback_Inv_D 0x15 415 416 void flush_icache_all(void) 417 { 418 u32 addr, t = 0; 419 420 asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ 421 asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ 422 423 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; 424 addr += CONFIG_SYS_CACHELINE_SIZE) { 425 asm volatile ( 426 ".set mips3\n\t" 427 " cache %0, 0(%1)\n\t" 428 ".set mips2\n\t" 429 : 430 : "I" (Index_Store_Tag_I), "r"(addr)); 431 } 432 433 /* invalicate btb */ 434 asm volatile ( 435 ".set mips32\n\t" 436 "mfc0 %0, $16, 7\n\t" 437 "nop\n\t" 438 "ori %0,2\n\t" 439 "mtc0 %0, $16, 7\n\t" 440 ".set mips2\n\t" 441 : 442 : "r" (t)); 443 } 444 445 void flush_dcache_all(void) 446 { 447 u32 addr; 448 449 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; 450 addr += CONFIG_SYS_CACHELINE_SIZE) { 451 asm volatile ( 452 ".set mips3\n\t" 453 " cache %0, 0(%1)\n\t" 454 ".set mips2\n\t" 455 : 456 : "I" (Index_Writeback_Inv_D), "r"(addr)); 457 } 458 459 asm volatile ("sync"); 460 } 461 462 void flush_cache_all(void) 463 { 464 flush_dcache_all(); 465 flush_icache_all(); 466 }