1 /* 2 * CPU-specific routines from U-Boot. 3 * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c 4 * See: u-boot/arch/mips/include/asm/cacheops.h 5 * 6 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include "xburst_types.h" 25 #include "sdram.h" 26 27 #define Index_Store_Tag_I 0x08 28 #define Index_Writeback_Inv_D 0x15 29 30 void flush_icache_all(void) 31 { 32 u32 addr, t = 0; 33 34 asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ 35 asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ 36 37 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; 38 addr += CONFIG_SYS_CACHELINE_SIZE) { 39 asm volatile ( 40 ".set mips3\n\t" 41 " cache %0, 0(%1)\n\t" 42 ".set mips2\n\t" 43 : 44 : "I" (Index_Store_Tag_I), "r"(addr)); 45 } 46 47 /* invalicate btb */ 48 asm volatile ( 49 ".set mips32\n\t" 50 "mfc0 %0, $16, 7\n\t" 51 "nop\n\t" 52 "ori %0,2\n\t" 53 "mtc0 %0, $16, 7\n\t" 54 ".set mips2\n\t" 55 : 56 : "r" (t)); 57 } 58 59 void flush_dcache_all(void) 60 { 61 u32 addr; 62 63 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; 64 addr += CONFIG_SYS_CACHELINE_SIZE) { 65 asm volatile ( 66 ".set mips3\n\t" 67 " cache %0, 0(%1)\n\t" 68 ".set mips2\n\t" 69 : 70 : "I" (Index_Writeback_Inv_D), "r"(addr)); 71 } 72 73 asm volatile ("sync"); 74 } 75 76 void flush_cache_all(void) 77 { 78 flush_dcache_all(); 79 flush_icache_all(); 80 }