1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "jz4740.h" 24 #include "configs.h" 25 #include "nanonote.h" 26 #include "usb_boot_defines.h" 27 28 /* These arguments are initialised by usbboot and are defined in... 29 /etc/xburst-tools/usbboot.cfg. */ 30 31 struct fw_args *fw_args; 32 volatile u32 CPU_ID; 33 volatile u8 SDRAM_BW16; 34 volatile u8 SDRAM_BANK4; 35 volatile u8 SDRAM_ROW; 36 volatile u8 SDRAM_COL; 37 volatile u8 CONFIG_MOBILE_SDRAM; 38 volatile u8 IS_SHARE; 39 40 void load_args(void) 41 { 42 /* Get the fw args from memory. See head1.S for the memory layout. */ 43 44 fw_args = (struct fw_args *)0x80002008; 45 CPU_ID = fw_args->cpu_id ; 46 SDRAM_BW16 = fw_args->bus_width; 47 SDRAM_BANK4 = fw_args->bank_num; 48 SDRAM_ROW = fw_args->row_addr; 49 SDRAM_COL = fw_args->col_addr; 50 CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 51 IS_SHARE = fw_args->is_busshare; 52 } 53 54 /* Initialisation functions. */ 55 56 void gpio_init(void) 57 { 58 /* 59 * Initialize NAND Flash Pins 60 */ 61 __gpio_as_nand(); 62 63 /* 64 * Initialize SDRAM pins 65 */ 66 __gpio_as_sdram_16bit_4720(); 67 } 68 69 void pll_init(void) 70 { 71 register unsigned int cfcr, plcr1; 72 int nf, pllout2; 73 74 /* See CPCCR (Clock Control Register). 75 * 0 == same frequency; 2 == f/3 76 */ 77 78 cfcr = CPM_CPCCR_CLKOEN | 79 CPM_CPCCR_PCS | 80 (0 << CPM_CPCCR_CDIV_BIT) | 81 (2 << CPM_CPCCR_HDIV_BIT) | 82 (2 << CPM_CPCCR_PDIV_BIT) | 83 (2 << CPM_CPCCR_MDIV_BIT) | 84 (2 << CPM_CPCCR_LDIV_BIT); 85 86 /* Determine the divider clock output based on the PCS bit. */ 87 88 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 89 90 /* Init USB Host clock. 91 * Divisor == UHCCDR + 1 92 * Desired frequency == 48MHz 93 */ 94 95 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 96 97 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 98 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 99 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 100 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 101 CPM_CPPCR_PLLEN; /* enable PLL */ 102 103 /* Update PLL and wait. */ 104 105 REG_CPM_CPCCR = cfcr; 106 REG_CPM_CPPCR = plcr1; 107 while (!__cpm_pll_is_on()); 108 } 109 110 void sdram_init(void) 111 { 112 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 113 unsigned int pllout = __cpm_get_pllout(); 114 115 unsigned int cas_latency_sdmr[2] = { 116 EMC_SDMR_CAS_2, 117 EMC_SDMR_CAS_3, 118 }; 119 120 unsigned int cas_latency_dmcr[2] = { 121 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 122 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 123 }; 124 125 /* Divisors for CPCCR values. */ 126 127 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 128 129 cpu_clk = pllout / div[__cpm_get_cdiv()]; 130 mem_clk = pllout / div[__cpm_get_mdiv()]; 131 132 REG_EMC_BCR = 0; /* Disable bus release */ 133 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 134 135 /* Fault DMCR value for mode register setting*/ 136 #define SDRAM_ROW0 11 137 #define SDRAM_COL0 8 138 #define SDRAM_BANK40 0 139 140 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | 141 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | 142 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | 143 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 144 EMC_DMCR_EPIN | 145 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 146 147 /* Basic DMCR value */ 148 dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | 149 ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | 150 (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | 151 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 152 EMC_DMCR_EPIN | 153 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 154 155 /* SDRAM timimg */ 156 ns = 1000000000 / mem_clk; 157 tmp = SDRAM_TRAS/ns; 158 if (tmp < 4) tmp = 4; 159 if (tmp > 11) tmp = 11; 160 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 161 tmp = SDRAM_RCD/ns; 162 if (tmp > 3) tmp = 3; 163 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 164 tmp = SDRAM_TPC/ns; 165 if (tmp > 7) tmp = 7; 166 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 167 tmp = SDRAM_TRWL/ns; 168 if (tmp > 3) tmp = 3; 169 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 170 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 171 if (tmp > 14) tmp = 14; 172 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 173 174 /* SDRAM mode value */ 175 sdmode = EMC_SDMR_BT_SEQ | 176 EMC_SDMR_OM_NORMAL | 177 EMC_SDMR_BL_4 | 178 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 179 180 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 181 REG_EMC_DMCR = dmcr; 182 REG8(EMC_SDMR0|sdmode) = 0; 183 184 /* Wait for precharge, > 200us */ 185 tmp = (cpu_clk / 1000000) * 1000; 186 while (tmp--); 187 188 /* Stage 2. Enable auto-refresh */ 189 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 190 191 tmp = SDRAM_TREF/ns; 192 tmp = tmp/64 + 1; 193 if (tmp > 0xff) tmp = 0xff; 194 REG_EMC_RTCOR = tmp; 195 REG_EMC_RTCNT = 0; 196 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 197 198 /* Wait for number of auto-refresh cycles */ 199 tmp = (cpu_clk / 1000000) * 1000; 200 while (tmp--); 201 202 /* Stage 3. Mode Register Set */ 203 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 204 REG8(EMC_SDMR0|sdmode) = 0; 205 206 /* Set back to basic DMCR value */ 207 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 208 209 /* everything is ok now */ 210 }