1 /* 2 * JzRISC LCD controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 */ 22 23 #include "sdram.h" 24 #include "jzlcd.h" 25 #include "cpu.h" 26 #include "board.h" 27 28 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 29 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 30 31 #define align2(n) (n)=((((n)+1)>>1)<<1) 32 #define align4(n) (n)=((((n)+3)>>2)<<2) 33 #define align8(n) (n)=((((n)+7)>>3)<<3) 34 35 extern struct jzfb_info jzfb; 36 extern vidinfo_t panel_info; 37 38 static unsigned long lcd_get_size(vidinfo_t *vid) 39 { 40 int line_length = (vid->vl_col * NBITS(vid->vl_bpix)) / 8; 41 return line_length * vid->vl_row; 42 } 43 44 static unsigned long lcd_get_total_size(vidinfo_t *vid) 45 { 46 /* Round up to nearest full page, or MMU section if defined */ 47 return ALIGN(lcd_get_size(vid), PAGE_SIZE); 48 } 49 50 static unsigned long lcd_setmem(unsigned long addr) 51 { 52 /* Allocate pages for the frame buffer. */ 53 return ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE) - lcd_get_total_size(&panel_info); 54 } 55 56 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 57 static void jz_lcd_desc_init(vidinfo_t *vid); 58 static int jz_lcd_hw_init(vidinfo_t *vid); 59 60 void lcd_ctrl_init(void **lcdbase) 61 { 62 /* Start from the top of memory and obtain a framebuffer region. */ 63 *lcdbase = (void *) lcd_setmem(get_memory_size()); 64 65 jz_lcd_init_mem(*lcdbase, &panel_info); 66 jz_lcd_desc_init(&panel_info); 67 jz_lcd_hw_init(&panel_info); 68 } 69 70 /* 71 * Before enabling the LCD controller, LCD registers should be configured correctly. 72 */ 73 void lcd_enable(void) 74 { 75 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 76 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 77 } 78 79 void lcd_disable(void) 80 { 81 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 82 } 83 84 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 85 { 86 unsigned long palette_mem_size; 87 struct jz_fb_info *fbi = &vid->jz_fb; 88 int fb_size = lcd_get_size(vid); 89 90 fbi->screen = (unsigned long)lcdbase; 91 fbi->palette_size = 256; 92 palette_mem_size = fbi->palette_size * sizeof(u16); 93 94 /* locate palette and descs at end of page following fb */ 95 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 96 97 return 0; 98 } 99 100 static void jz_lcd_desc_init(vidinfo_t *vid) 101 { 102 struct jz_fb_info * fbi; 103 fbi = &vid->jz_fb; 104 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 105 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 106 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 107 108 /* populate descriptors */ 109 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 110 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + lcd_get_size(vid))); 111 fbi->dmadesc_fblow->fidr = 0; 112 fbi->dmadesc_fblow->ldcmd = lcd_get_size(vid) / 4 ; 113 114 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 115 116 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 117 fbi->dmadesc_fbhigh->fidr = 0; 118 fbi->dmadesc_fbhigh->ldcmd = lcd_get_size(vid) / 4; /* length in word */ 119 120 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 121 fbi->dmadesc_palette->fidr = 0; 122 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 123 124 if(NBITS(vid->vl_bpix) < 12) 125 { 126 /* assume any mode with <12 bpp is palette driven */ 127 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 128 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 129 /* flips back and forth between pal and fbhigh */ 130 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 131 } else { 132 /* palette shouldn't be loaded in true-color mode */ 133 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 134 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 135 } 136 137 flush_cache_all(); 138 } 139 140 static int jz_lcd_hw_init(vidinfo_t *vid) 141 { 142 struct jz_fb_info *fbi = &vid->jz_fb; 143 unsigned int val = 0; 144 unsigned int pclk; 145 unsigned int stnH; 146 #ifndef CONFIG_CPU_JZ4730 147 int pll_div; 148 #endif 149 150 /* Setting Control register */ 151 switch (jzfb.bpp) { 152 case 1: 153 val |= LCD_CTRL_BPP_1; 154 break; 155 case 2: 156 val |= LCD_CTRL_BPP_2; 157 break; 158 case 4: 159 val |= LCD_CTRL_BPP_4; 160 break; 161 case 8: 162 val |= LCD_CTRL_BPP_8; 163 break; 164 case 15: 165 val |= LCD_CTRL_RGB555; 166 case 16: 167 val |= LCD_CTRL_BPP_16; 168 break; 169 #ifndef CONFIG_CPU_JZ4730 170 case 17 ... 32: 171 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 172 break; 173 #endif 174 default: 175 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 176 val |= LCD_CTRL_BPP_16; 177 break; 178 } 179 180 switch (jzfb.cfg & MODE_MASK) { 181 case MODE_STN_MONO_DUAL: 182 case MODE_STN_COLOR_DUAL: 183 case MODE_STN_MONO_SINGLE: 184 case MODE_STN_COLOR_SINGLE: 185 switch (jzfb.bpp) { 186 case 1: 187 /* val |= LCD_CTRL_PEDN; */ 188 case 2: 189 val |= LCD_CTRL_FRC_2; 190 break; 191 case 4: 192 val |= LCD_CTRL_FRC_4; 193 break; 194 case 8: 195 default: 196 val |= LCD_CTRL_FRC_16; 197 break; 198 } 199 break; 200 } 201 202 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 203 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 204 205 switch (jzfb.cfg & MODE_MASK) { 206 case MODE_STN_MONO_DUAL: 207 case MODE_STN_COLOR_DUAL: 208 case MODE_STN_MONO_SINGLE: 209 case MODE_STN_COLOR_SINGLE: 210 switch (jzfb.cfg & STN_DAT_PINMASK) { 211 case STN_DAT_PIN1: 212 /* Do not adjust the hori-param value. */ 213 break; 214 case STN_DAT_PIN2: 215 align2(jzfb.hsw); 216 align2(jzfb.elw); 217 align2(jzfb.blw); 218 break; 219 case STN_DAT_PIN4: 220 align4(jzfb.hsw); 221 align4(jzfb.elw); 222 align4(jzfb.blw); 223 break; 224 case STN_DAT_PIN8: 225 align8(jzfb.hsw); 226 align8(jzfb.elw); 227 align8(jzfb.blw); 228 break; 229 } 230 break; 231 } 232 233 REG_LCD_CTRL = val; 234 235 switch (jzfb.cfg & MODE_MASK) { 236 case MODE_STN_MONO_DUAL: 237 case MODE_STN_COLOR_DUAL: 238 case MODE_STN_MONO_SINGLE: 239 case MODE_STN_COLOR_SINGLE: 240 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 241 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 242 stnH = jzfb.h >> 1; 243 else 244 stnH = jzfb.h; 245 246 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 247 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 248 249 /* Screen setting */ 250 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 251 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 252 REG_LCD_DAV = (0 << 16) | (stnH); 253 254 /* AC BIAs signal */ 255 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 256 257 break; 258 259 case MODE_TFT_GEN: 260 case MODE_TFT_SHARP: 261 case MODE_TFT_CASIO: 262 case MODE_TFT_SAMSUNG: 263 case MODE_8BIT_SERIAL_TFT: 264 case MODE_TFT_18BIT: 265 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 266 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 267 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 268 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 269 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 270 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 271 break; 272 } 273 274 switch (jzfb.cfg & MODE_MASK) { 275 case MODE_TFT_SAMSUNG: 276 { 277 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 278 unsigned int rev_s, rev_e, inv_s, inv_e; 279 280 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 281 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 282 283 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 284 tp_s = jzfb.blw + jzfb.w + 1; 285 tp_e = tp_s + 1; 286 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 287 ckv_s = tp_s - pclk/(1000000000/4100); 288 ckv_e = tp_s + total; 289 rev_s = tp_s - 11; /* -11.5 clk */ 290 rev_e = rev_s + total; 291 inv_s = tp_s; 292 inv_e = inv_s + total; 293 REG_LCD_CLS = (tp_s << 16) | tp_e; 294 REG_LCD_PS = (ckv_s << 16) | ckv_e; 295 REG_LCD_SPL = (rev_s << 16) | rev_e; 296 REG_LCD_REV = (inv_s << 16) | inv_e; 297 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 298 break; 299 } 300 case MODE_TFT_SHARP: 301 { 302 unsigned int total, cls_s, cls_e, ps_s, ps_e; 303 unsigned int spl_s, spl_e, rev_s, rev_e; 304 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 305 spl_s = 1; 306 spl_e = spl_s + 1; 307 cls_s = 0; 308 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 309 ps_s = cls_s; 310 ps_e = cls_e; 311 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 312 rev_e = rev_s + total; 313 jzfb.cfg |= STFT_PSHI; 314 REG_LCD_SPL = (spl_s << 16) | spl_e; 315 REG_LCD_CLS = (cls_s << 16) | cls_e; 316 REG_LCD_PS = (ps_s << 16) | ps_e; 317 REG_LCD_REV = (rev_s << 16) | rev_e; 318 break; 319 } 320 case MODE_TFT_CASIO: 321 break; 322 } 323 324 /* Configure the LCD panel */ 325 REG_LCD_CFG = jzfb.cfg; 326 327 /* Timing setting */ 328 __cpm_stop_lcd(); 329 330 val = jzfb.fclk; /* frame clk */ 331 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 332 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 333 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 334 } else { 335 /* serial mode: Hsync period = 3*Width_Pixel */ 336 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 337 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 338 } 339 340 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 341 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 342 pclk = (pclk * 3); 343 344 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 345 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 346 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 347 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 348 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 349 350 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 351 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 352 pclk >>= 1; 353 354 #ifdef CONFIG_CPU_JZ4730 355 val = __cpm_get_pllout() / pclk; 356 REG_CPM_CFCR2 = val - 1; 357 val = pclk * 4 ; 358 if ( val > 150000000 ) { 359 val = 150000000; 360 } 361 val = __cpm_get_pllout() / val; 362 val--; 363 if ( val > 0xF ) 364 val = 0xF; 365 #else 366 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 367 pll_div = pll_div ? 1 : 2 ; 368 val = ( __cpm_get_pllout()/pll_div ) / pclk; 369 val--; 370 if ( val > 0x1ff ) { 371 val = 0x1ff; 372 } 373 __cpm_set_pixdiv(val); 374 375 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 376 if ( val > 150000000 ) { 377 val = 150000000; 378 } 379 val = ( __cpm_get_pllout()/pll_div ) / val; 380 val--; 381 if ( val > 0x1f ) { 382 val = 0x1f; 383 } 384 #endif 385 __cpm_set_ldiv( val ); 386 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 387 388 __cpm_start_lcd(); 389 udelay(1000); 390 391 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 392 393 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 394 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 395 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 396 397 return 0; 398 } 399 400 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 401 { 402 } 403 404 void lcd_initcolregs (void) 405 { 406 }