1 /* 2 * JzRISC LCD controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 */ 22 23 #include "sdram.h" 24 #include "jzlcd.h" 25 #include "cpu.h" 26 #include "board.h" 27 28 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 29 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 30 31 #define align2(n) (n)=((((n)+1)>>1)<<1) 32 #define align4(n) (n)=((((n)+3)>>2)<<2) 33 #define align8(n) (n)=((((n)+7)>>3)<<3) 34 35 extern struct jzfb_info jzfb; 36 extern vidinfo_t panel_info; 37 38 static unsigned long lcd_get_size(vidinfo_t *vid) 39 { 40 int line_length = (vid->vl_col * NBITS(vid->vl_bpix)) / 8; 41 return line_length * vid->vl_row; 42 } 43 44 static unsigned long lcd_get_total_size(vidinfo_t *vid) 45 { 46 /* Round up to nearest full page, or MMU section if defined */ 47 return ALIGN(lcd_get_size(vid), PAGE_SIZE); 48 } 49 50 static unsigned long lcd_setmem(unsigned long addr) 51 { 52 /* Allocate pages for the frame buffer. */ 53 return ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE) - lcd_get_total_size(&panel_info); 54 } 55 56 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 57 static void jz_lcd_desc_init(vidinfo_t *vid); 58 static int jz_lcd_hw_init(vidinfo_t *vid); 59 60 void lcd_ctrl_init(void **lcdbase) 61 { 62 /* Start from the top of memory and obtain a framebuffer region. */ 63 *lcdbase = (void *) lcd_setmem(get_memory_size()); 64 65 jz_lcd_init_mem(*lcdbase, &panel_info); 66 jz_lcd_desc_init(&panel_info); 67 jz_lcd_hw_init(&panel_info); 68 } 69 70 /* 71 * Before enabling the LCD controller, LCD registers should be configured correctly. 72 */ 73 void lcd_enable(void) 74 { 75 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 76 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 77 } 78 79 void lcd_disable(void) 80 { 81 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 82 } 83 84 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 85 { 86 unsigned long palette_mem_size; 87 struct jz_fb_info *fbi = &vid->jz_fb; 88 int fb_size = lcd_get_size(vid); 89 90 fbi->screen = (unsigned long)lcdbase; 91 fbi->palette_size = 256; 92 palette_mem_size = fbi->palette_size * sizeof(u16); 93 94 /* locate palette and descs at end of page following fb */ 95 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 96 97 return 0; 98 } 99 100 static void jz_lcd_desc_init(vidinfo_t *vid) 101 { 102 struct jz_fb_dma_descriptor *descriptors; 103 struct jz_fb_info * fbi; 104 fbi = &vid->jz_fb; 105 descriptors = ((struct jz_fb_dma_descriptor *) fbi->palette) - 3; 106 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *) &descriptors[0]; 107 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *) &descriptors[1]; 108 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *) &descriptors[2]; 109 110 /* populate descriptors */ 111 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 112 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + lcd_get_size(vid))); 113 fbi->dmadesc_fblow->fidr = 0; 114 fbi->dmadesc_fblow->ldcmd = lcd_get_size(vid) / 4 ; 115 116 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 117 118 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 119 fbi->dmadesc_fbhigh->fidr = 0; 120 fbi->dmadesc_fbhigh->ldcmd = lcd_get_size(vid) / 4; /* length in word */ 121 122 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 123 fbi->dmadesc_palette->fidr = 0; 124 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 125 126 if(NBITS(vid->vl_bpix) < 12) 127 { 128 /* assume any mode with <12 bpp is palette driven */ 129 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 130 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 131 /* flips back and forth between pal and fbhigh */ 132 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 133 } else { 134 /* palette shouldn't be loaded in true-color mode */ 135 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 136 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 137 } 138 139 flush_cache_all(); 140 } 141 142 static int jz_lcd_hw_init(vidinfo_t *vid) 143 { 144 struct jz_fb_info *fbi = &vid->jz_fb; 145 unsigned int val = 0; 146 unsigned int pclk; 147 unsigned int stnH; 148 #ifndef CONFIG_CPU_JZ4730 149 int pll_div; 150 #endif 151 152 /* Setting Control register */ 153 switch (jzfb.bpp) { 154 case 1: 155 val |= LCD_CTRL_BPP_1; 156 break; 157 case 2: 158 val |= LCD_CTRL_BPP_2; 159 break; 160 case 4: 161 val |= LCD_CTRL_BPP_4; 162 break; 163 case 8: 164 val |= LCD_CTRL_BPP_8; 165 break; 166 case 15: 167 val |= LCD_CTRL_RGB555; 168 case 16: 169 val |= LCD_CTRL_BPP_16; 170 break; 171 #ifndef CONFIG_CPU_JZ4730 172 case 17 ... 32: 173 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 174 break; 175 #endif 176 default: 177 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 178 val |= LCD_CTRL_BPP_16; 179 break; 180 } 181 182 switch (jzfb.cfg & MODE_MASK) { 183 case MODE_STN_MONO_DUAL: 184 case MODE_STN_COLOR_DUAL: 185 case MODE_STN_MONO_SINGLE: 186 case MODE_STN_COLOR_SINGLE: 187 switch (jzfb.bpp) { 188 case 1: 189 /* val |= LCD_CTRL_PEDN; */ 190 case 2: 191 val |= LCD_CTRL_FRC_2; 192 break; 193 case 4: 194 val |= LCD_CTRL_FRC_4; 195 break; 196 case 8: 197 default: 198 val |= LCD_CTRL_FRC_16; 199 break; 200 } 201 break; 202 } 203 204 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 205 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 206 207 switch (jzfb.cfg & MODE_MASK) { 208 case MODE_STN_MONO_DUAL: 209 case MODE_STN_COLOR_DUAL: 210 case MODE_STN_MONO_SINGLE: 211 case MODE_STN_COLOR_SINGLE: 212 switch (jzfb.cfg & STN_DAT_PINMASK) { 213 case STN_DAT_PIN1: 214 /* Do not adjust the hori-param value. */ 215 break; 216 case STN_DAT_PIN2: 217 align2(jzfb.hsw); 218 align2(jzfb.elw); 219 align2(jzfb.blw); 220 break; 221 case STN_DAT_PIN4: 222 align4(jzfb.hsw); 223 align4(jzfb.elw); 224 align4(jzfb.blw); 225 break; 226 case STN_DAT_PIN8: 227 align8(jzfb.hsw); 228 align8(jzfb.elw); 229 align8(jzfb.blw); 230 break; 231 } 232 break; 233 } 234 235 REG_LCD_CTRL = val; 236 237 switch (jzfb.cfg & MODE_MASK) { 238 case MODE_STN_MONO_DUAL: 239 case MODE_STN_COLOR_DUAL: 240 case MODE_STN_MONO_SINGLE: 241 case MODE_STN_COLOR_SINGLE: 242 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 243 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 244 stnH = jzfb.h >> 1; 245 else 246 stnH = jzfb.h; 247 248 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 249 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 250 251 /* Screen setting */ 252 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 253 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 254 REG_LCD_DAV = (0 << 16) | (stnH); 255 256 /* AC BIAs signal */ 257 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 258 259 break; 260 261 case MODE_TFT_GEN: 262 case MODE_TFT_SHARP: 263 case MODE_TFT_CASIO: 264 case MODE_TFT_SAMSUNG: 265 case MODE_8BIT_SERIAL_TFT: 266 case MODE_TFT_18BIT: 267 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 268 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 269 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 270 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 271 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 272 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 273 break; 274 } 275 276 switch (jzfb.cfg & MODE_MASK) { 277 case MODE_TFT_SAMSUNG: 278 { 279 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 280 unsigned int rev_s, rev_e, inv_s, inv_e; 281 282 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 283 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 284 285 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 286 tp_s = jzfb.blw + jzfb.w + 1; 287 tp_e = tp_s + 1; 288 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 289 ckv_s = tp_s - pclk/(1000000000/4100); 290 ckv_e = tp_s + total; 291 rev_s = tp_s - 11; /* -11.5 clk */ 292 rev_e = rev_s + total; 293 inv_s = tp_s; 294 inv_e = inv_s + total; 295 REG_LCD_CLS = (tp_s << 16) | tp_e; 296 REG_LCD_PS = (ckv_s << 16) | ckv_e; 297 REG_LCD_SPL = (rev_s << 16) | rev_e; 298 REG_LCD_REV = (inv_s << 16) | inv_e; 299 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 300 break; 301 } 302 case MODE_TFT_SHARP: 303 { 304 unsigned int total, cls_s, cls_e, ps_s, ps_e; 305 unsigned int spl_s, spl_e, rev_s, rev_e; 306 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 307 spl_s = 1; 308 spl_e = spl_s + 1; 309 cls_s = 0; 310 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 311 ps_s = cls_s; 312 ps_e = cls_e; 313 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 314 rev_e = rev_s + total; 315 jzfb.cfg |= STFT_PSHI; 316 REG_LCD_SPL = (spl_s << 16) | spl_e; 317 REG_LCD_CLS = (cls_s << 16) | cls_e; 318 REG_LCD_PS = (ps_s << 16) | ps_e; 319 REG_LCD_REV = (rev_s << 16) | rev_e; 320 break; 321 } 322 case MODE_TFT_CASIO: 323 break; 324 } 325 326 /* Configure the LCD panel */ 327 REG_LCD_CFG = jzfb.cfg; 328 329 /* Timing setting */ 330 __cpm_stop_lcd(); 331 332 val = jzfb.fclk; /* frame clk */ 333 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 334 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 335 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 336 } else { 337 /* serial mode: Hsync period = 3*Width_Pixel */ 338 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 339 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 340 } 341 342 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 343 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 344 pclk = (pclk * 3); 345 346 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 347 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 348 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 349 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 350 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 351 352 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 353 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 354 pclk >>= 1; 355 356 #ifdef CONFIG_CPU_JZ4730 357 val = __cpm_get_pllout() / pclk; 358 REG_CPM_CFCR2 = val - 1; 359 val = pclk * 4 ; 360 if ( val > 150000000 ) { 361 val = 150000000; 362 } 363 val = __cpm_get_pllout() / val; 364 val--; 365 if ( val > 0xF ) 366 val = 0xF; 367 #else 368 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 369 pll_div = pll_div ? 1 : 2 ; 370 val = ( __cpm_get_pllout()/pll_div ) / pclk; 371 val--; 372 if ( val > 0x1ff ) { 373 val = 0x1ff; 374 } 375 __cpm_set_pixdiv(val); 376 377 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 378 if ( val > 150000000 ) { 379 val = 150000000; 380 } 381 val = ( __cpm_get_pllout()/pll_div ) / val; 382 val--; 383 if ( val > 0x1f ) { 384 val = 0x1f; 385 } 386 #endif 387 __cpm_set_ldiv( val ); 388 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 389 390 __cpm_start_lcd(); 391 udelay(1000); 392 393 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 394 395 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 396 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 397 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 398 399 return 0; 400 } 401 402 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 403 { 404 } 405 406 void lcd_initcolregs (void) 407 { 408 }