1 /* 2 * U-Boot and jz4740 LCD controller definitions. 3 * 4 * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. 6 * Copyright (C) 2009 Qi Hardware Inc. 7 * Author: Xiangfu Liu <xiangfu@sharism.cc> 8 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 9 * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 24 * Boston, MA 02110-1301, USA 25 */ 26 27 #ifndef __JZLCD_H__ 28 #define __JZLCD_H__ 29 30 #include <stdint.h> 31 32 /* Framebuffer characteristics. */ 33 34 struct jzfb_info { 35 uint32_t cfg; /* panel mode and pin usage etc. */ 36 uint16_t w; /* display width in pixels */ 37 uint16_t h; /* display height in pixels */ 38 uint8_t bpp; /* bits per pixel */ 39 uint32_t fclk; /* frame clock */ 40 uint32_t hsw; /* hsync width, in pixel clock */ 41 uint32_t vsw; /* vsync width, in line count */ 42 uint32_t elw; /* end of line, in pixel clock */ 43 uint32_t blw; /* begin of line, in pixel clock */ 44 uint32_t efw; /* end of frame, in line count */ 45 uint32_t bfw; /* begin of frame, in line count */ 46 }; 47 48 /* LCD controller stucture for jz4740. */ 49 50 struct jz_fb_dma_descriptor { 51 struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */ 52 uint32_t fsadr; /* frame source address register */ 53 uint32_t fidr; /* frame identifier register */ 54 uint32_t ldcmd; /* command register */ 55 }; 56 57 /* Framebuffer and controller memory information. */ 58 59 struct jz_mem_info { 60 61 /* DMA descriptor references (updated for transfers). */ 62 63 struct jz_fb_dma_descriptor *fdadr0; /* physical address of frame descriptor */ 64 struct jz_fb_dma_descriptor *fdadr1; /* physical address of frame/palette descriptor */ 65 66 /* DMA descriptor references (indicating allocated regions). */ 67 68 struct jz_fb_dma_descriptor *dmadesc_fb0; 69 struct jz_fb_dma_descriptor *dmadesc_fb1; 70 struct jz_fb_dma_descriptor *dmadesc_palette; 71 72 /* Region addresses. */ 73 74 uint32_t screen; /* address of first frame buffer (base of memory used) */ 75 uint32_t palette; /* address of palette memory */ 76 uint32_t total; /* total memory used */ 77 }; 78 79 /* Display characteristics and memory resources. */ 80 81 typedef struct vidinfo { 82 struct jzfb_info *jz_fb; /* framebuffer and panel properties */ 83 struct jz_mem_info jz_mem; /* framebuffer memory information */ 84 void *lcd; /* address of LCD controller registers */ 85 } vidinfo_t; 86 87 88 89 /* Public functions. */ 90 91 uint32_t jz4740_lcd_get_total_size(vidinfo_t *vid); 92 uint32_t jz4740_lcd_get_pixel_clock(vidinfo_t *vid); 93 void jz4740_lcd_ctrl_init(void *lcd_base, void *fb_vaddr, vidinfo_t *vid); 94 void jz4740_lcd_hw_init(vidinfo_t *vid); 95 void jz4740_lcd_dma_init(vidinfo_t *vid); 96 void jz4740_lcd_set_bpp(uint8_t bpp, vidinfo_t *vid); 97 void jz4740_lcd_enable(vidinfo_t *vid); 98 void jz4740_lcd_disable(vidinfo_t *vid); 99 void jz4740_lcd_quick_disable(vidinfo_t *vid); 100 101 102 103 /* Alignment/rounding macros. */ 104 105 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 106 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 107 108 /* Display device mode select (LCD_CFG.MODE). */ 109 110 #define MODE_MASK 0x0f 111 #define MODE_TFT_GEN 0x00 112 #define MODE_TFT_SHARP 0x01 113 #define MODE_TFT_CASIO 0x02 114 #define MODE_TFT_SAMSUNG 0x03 115 #define MODE_CCIR656_NONINT 0x04 116 #define MODE_CCIR656_INT 0x05 117 #define MODE_STN_COLOR_SINGLE 0x08 118 #define MODE_STN_MONO_SINGLE 0x09 119 #define MODE_STN_COLOR_DUAL 0x0a 120 #define MODE_STN_MONO_DUAL 0x0b 121 #define MODE_8BIT_SERIAL_TFT 0x0c 122 123 /* 16-bit or 18-bit TFT panel selection (LCD_CFG.18/16). */ 124 125 #define MODE_TFT_18BIT (1<<7) 126 127 /* STN pin utilisation (LCD_CFG.PDW). */ 128 129 #define STN_DAT_PIN1 (0x00 << 4) 130 #define STN_DAT_PIN2 (0x01 << 4) 131 #define STN_DAT_PIN4 (0x02 << 4) 132 #define STN_DAT_PIN8 (0x03 << 4) 133 #define STN_DAT_PINMASK STN_DAT_PIN8 134 135 /* Pin reset states (LCD_CFG). */ 136 137 #define STFT_PSHI (1 << 15) 138 #define STFT_CLSHI (1 << 14) 139 #define STFT_SPLHI (1 << 13) 140 #define STFT_REVHI (1 << 12) 141 142 /* Sync direction (LCD_CFG.SYNDIR). */ 143 144 #define SYNC_MASTER (0 << 16) 145 #define SYNC_SLAVE (1 << 16) 146 147 /* Data enable polarity (LCD_CFG.DEP). */ 148 149 #define DE_P (0 << 9) 150 #define DE_N (1 << 9) 151 152 /* Pixel clock polarity (LCD_CFG.PCP). */ 153 154 #define PCLK_P (0 << 10) 155 #define PCLK_N (1 << 10) 156 157 /* Horizontal sync polarity (LCD_CFG.HSP). */ 158 159 #define HSYNC_P (0 << 11) 160 #define HSYNC_N (1 << 11) 161 162 /* Vertical sync polarity (LCD_CFG.VSP). */ 163 164 #define VSYNC_P (0 << 8) 165 #define VSYNC_N (1 << 8) 166 167 /* Inverse output data (LCD_CFG.INVDAT). */ 168 169 #define DATA_NORMAL (0 << 17) 170 #define DATA_INVERSE (1 << 17) 171 172 /* Register offsets. */ 173 174 #define LCD_CFG 0x00 /* LCD Configure Register */ 175 #define LCD_VSYNC 0x04 /* Vertical Synchronize Register */ 176 #define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */ 177 #define LCD_VAT 0x0c /* Virtual Area Setting Register */ 178 #define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */ 179 #define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */ 180 #define LCD_PS 0x18 /* PS Signal Setting */ 181 #define LCD_CLS 0x1c /* CLS Signal Setting */ 182 #define LCD_SPL 0x20 /* SPL Signal Setting */ 183 #define LCD_REV 0x24 /* REV Signal Setting */ 184 #define LCD_CTRL 0x30 /* LCD Control Register */ 185 #define LCD_STATE 0x34 /* LCD Status Register */ 186 #define LCD_IID 0x38 /* Interrupt ID Register */ 187 #define LCD_DA0 0x40 /* Descriptor Address Register 0 */ 188 #define LCD_SA0 0x44 /* Source Address Register 0 */ 189 #define LCD_FID0 0x48 /* Frame ID Register 0 */ 190 #define LCD_CMD0 0x4c /* DMA Command Register 0 */ 191 #define LCD_DA1 0x50 /* Descriptor Address Register 1 */ 192 #define LCD_SA1 0x54 /* Source Address Register 1 */ 193 #define LCD_FID1 0x58 /* Frame ID Register 1 */ 194 #define LCD_CMD1 0x5c /* DMA Command Register 1 */ 195 196 /* Palette buffer (LCD_CMDx.PAL). */ 197 198 #define LCD_CMD_PAL (1 << 28) 199 200 #endif /* __JZLCD_H__ */