1 /* 2 * JzRISC lcd controller 3 * 4 * Xiangfu Liu <xiangfu@sharism.cc> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __QI_LB60_GPM940B0_H__ 23 #define __QI_LB60_GPM940B0_H__ 24 25 #include "nanonote.h" 26 #include "jz4740_lcd.h" 27 28 unsigned long lcd_get_size(void); 29 void lcd_ctrl_init(void *lcdbase); 30 void lcd_enable(void); 31 void lcd_disable(void); 32 33 struct lcd_desc{ 34 unsigned int next_desc; /* LCDDAx */ 35 unsigned int databuf; /* LCDSAx */ 36 unsigned int frame_id; /* LCDFIDx */ 37 unsigned int cmd; /* LCDCMDx */ 38 }; 39 40 #define MODE_MASK 0x0f 41 #define MODE_TFT_GEN 0x00 42 #define MODE_TFT_SHARP 0x01 43 #define MODE_TFT_CASIO 0x02 44 #define MODE_TFT_SAMSUNG 0x03 45 #define MODE_CCIR656_NONINT 0x04 46 #define MODE_CCIR656_INT 0x05 47 #define MODE_STN_COLOR_SINGLE 0x08 48 #define MODE_STN_MONO_SINGLE 0x09 49 #define MODE_STN_COLOR_DUAL 0x0a 50 #define MODE_STN_MONO_DUAL 0x0b 51 #define MODE_8BIT_SERIAL_TFT 0x0c 52 53 #define MODE_TFT_18BIT (1<<7) 54 55 #define STN_DAT_PIN1 (0x00 << 4) 56 #define STN_DAT_PIN2 (0x01 << 4) 57 #define STN_DAT_PIN4 (0x02 << 4) 58 #define STN_DAT_PIN8 (0x03 << 4) 59 #define STN_DAT_PINMASK STN_DAT_PIN8 60 61 #define STFT_PSHI (1 << 15) 62 #define STFT_CLSHI (1 << 14) 63 #define STFT_SPLHI (1 << 13) 64 #define STFT_REVHI (1 << 12) 65 66 #define SYNC_MASTER (0 << 16) 67 #define SYNC_SLAVE (1 << 16) 68 69 #define DE_P (0 << 9) 70 #define DE_N (1 << 9) 71 72 #define PCLK_P (0 << 10) 73 #define PCLK_N (1 << 10) 74 75 #define HSYNC_P (0 << 11) 76 #define HSYNC_N (1 << 11) 77 78 #define VSYNC_P (0 << 8) 79 #define VSYNC_N (1 << 8) 80 81 #define DATA_NORMAL (0 << 17) 82 #define DATA_INVERSE (1 << 17) 83 84 85 /* Jz LCDFB supported I/O controls. */ 86 #define FBIOSETBACKLIGHT 0x4688 87 #define FBIODISPON 0x4689 88 #define FBIODISPOFF 0x468a 89 #define FBIORESET 0x468b 90 #define FBIOPRINT_REG 0x468c 91 92 /* 93 * LCD panel specific definition 94 */ 95 #define MODE (0xc9) /* 8bit serial RGB */ 96 97 #define __spi_write_reg1(reg, val) \ 98 do { \ 99 unsigned char no; \ 100 unsigned short value; \ 101 unsigned char a=reg; \ 102 unsigned char b=val; \ 103 __gpio_set_pin(SPEN); \ 104 __gpio_set_pin(SPCK); \ 105 __gpio_clear_pin(SPDA); \ 106 __gpio_clear_pin(SPEN); \ 107 value=((a<<8)|(b&0xFF)); \ 108 for(no=0;no<16;no++) \ 109 { \ 110 __gpio_clear_pin(SPCK); \ 111 if((value&0x8000)==0x8000) \ 112 __gpio_set_pin(SPDA); \ 113 else \ 114 __gpio_clear_pin(SPDA); \ 115 __gpio_set_pin(SPCK); \ 116 value=(value<<1); \ 117 } \ 118 __gpio_set_pin(SPEN); \ 119 } while (0) 120 121 #define __lcd_display_pin_init() \ 122 do { \ 123 __cpm_start_tcu(); \ 124 __gpio_as_output(SPEN); /* use SPDA */ \ 125 __gpio_as_output(SPCK); /* use SPCK */ \ 126 __gpio_as_output(SPDA); /* use SPDA */ \ 127 } while (0) 128 129 #define __lcd_display_on() \ 130 do { \ 131 __spi_write_reg1(0x05, 0x1e); \ 132 __spi_write_reg1(0x05, 0x5e); \ 133 __spi_write_reg1(0x07, 0x8d); \ 134 __spi_write_reg1(0x13, 0x01); \ 135 __spi_write_reg1(0x05, 0x5f); \ 136 } while (0) 137 138 #define __lcd_display_off() \ 139 do { \ 140 __spi_write_reg1(0x05, 0x5e); \ 141 } while (0) 142 143 #endif /* __QI_LB60_GPM940B0_H__ */