NanoPayload

stage2/head2.S

77:7e61adf1e166
2015-07-03 Paul Boddie Experiment with loading the program at 0x80001000. stage2-non-pic
     1 /*     2  * Initialisation code for the stage 2 payload.     3  *     4  * Copyright 2009 (C) Qi Hardware Inc.     5  * Author: Wolfgang Spraul <wolfgang@sharism.cc>     6  *     7  * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>     8  *     9  * This program is free software: you can redistribute it and/or modify    10  * it under the terms of the GNU General Public License as published by    11  * the Free Software Foundation, either version 3 of the License, or    12  * (at your option) any later version.    13  *    14  * This program is distributed in the hope that it will be useful,    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    17  * GNU General Public License for more details.    18  *    19  * You should have received a copy of the GNU General Public License    20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.    21  */    22     23 #include "sdram.h"    24     25 .text    26 .extern c_main    27 .extern _tlb_entry    28 .extern _exc_entry    29 .extern _irq_entry    30 .extern _end_entries    31 .globl _start    32 .set noreorder    33     34 _start:    35 	/* Initialise the stack. */    36     37 	la $sp, 0x80004000    38     39 	/* Initialise the globals pointer. */    40     41 	lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)    42 	ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)    43     44 	move $k0, $ra    45     46 	/* Copy TLB handling instructions. */    47     48 	la $t0, _tlb_entry		/* start */    49 	li $t1, 0x80000000    50 	la $t2, _cache_entry		/* end */    51 	jal _copy    52 	nop    53     54 	/* Copy cache handling instructions. */    55     56 	move $t0, $t2			/* start */    57 	li $t1, 0x80000100    58 	la $t2, _exc_entry		/* end */    59 	jal _copy    60 	nop    61     62 	/* Copy exception handling instructions. */    63     64 	move $t0, $t2			/* start */    65 	li $t1, 0x80000180    66 	la $t2, _irq_entry		/* end */    67 	jal _copy    68 	nop    69     70 	/* Copy IRQ handling instructions. */    71     72 	move $t0, $t2			/* start */    73 	li $t1, 0x80000200    74 	la $t2, _end_entries		/* end */    75 	jal _copy    76 	nop    77     78 	move $ra, $k0    79     80 	/* Enable caching. */    81     82 	li $t0, CONFIG_CM_CACHABLE_NONCOHERENT    83 	mtc0 $t0, $16			/* CP0_CONFIG */    84 	nop    85     86 	/* Start the program. */    87     88 	j c_main    89 	nop    90     91 _copy:    92 	/* Copy via $t3 the region from $t0 to $t2 into $t1. */    93     94 	lw $t3, 0($t0)    95 	addiu $t0, $t0, 4    96 	sw $t3, 0($t1)    97 	bne $t0, $t2, _copy    98 	addiu $t1, $t1, 4		/* executed in delay slot before branch */    99 	j $ra   100 	nop   101    102 .set reorder