1 /* 2 * JzRISC lcd controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h 24 via u-boot/arch/mips/include/asm/io.h */ 25 /* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */ 26 #define virt_to_phys(n) ((int) n) 27 28 #include "jz4740.h" 29 #include "nanonote_gpm940b0.h" 30 #include "board-nanonote.h" 31 32 #define align2(n) (n)=((((n)+1)>>1)<<1) 33 #define align4(n) (n)=((((n)+3)>>2)<<2) 34 #define align8(n) (n)=((((n)+7)>>3)<<3) 35 36 struct jzfb_info { 37 unsigned int cfg; /* panel mode and pin usage etc. */ 38 unsigned int w; 39 unsigned int h; 40 unsigned int bpp; /* bit per pixel */ 41 unsigned int fclk; /* frame clk */ 42 unsigned int hsw; /* hsync width, in pclk */ 43 unsigned int vsw; /* vsync width, in line count */ 44 unsigned int elw; /* end of line, in pclk */ 45 unsigned int blw; /* begin of line, in pclk */ 46 unsigned int efw; /* end of frame, in line count */ 47 unsigned int bfw; /* begin of frame, in line count */ 48 }; 49 50 static struct jzfb_info jzfb = { 51 MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, 52 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 53 }; 54 55 vidinfo_t panel_info = { 56 320, 240, LCD_BPP, 57 }; 58 59 unsigned long lcd_get_size(void) 60 { 61 int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; 62 return line_length * panel_info.vl_row; 63 } 64 65 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 66 static void jz_lcd_desc_init(vidinfo_t *vid); 67 static int jz_lcd_hw_init(vidinfo_t *vid); 68 69 void lcd_ctrl_init (void *lcdbase) 70 { 71 jz_lcd_init_mem(lcdbase, &panel_info); 72 jz_lcd_desc_init(&panel_info); 73 jz_lcd_hw_init(&panel_info); 74 } 75 76 /* 77 * Before enabled lcd controller, lcd registers should be configured correctly. 78 */ 79 void lcd_enable (void) 80 { 81 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 82 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 83 } 84 85 void lcd_disable (void) 86 { 87 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 88 /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ 89 } 90 91 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 92 { 93 unsigned long palette_mem_size; 94 struct jz_fb_info *fbi = &vid->jz_fb; 95 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; 96 97 fbi->screen = (unsigned long)lcdbase; 98 fbi->palette_size = 256; 99 palette_mem_size = fbi->palette_size * sizeof(u16); 100 101 /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ 102 /* locate palette and descs at end of page following fb */ 103 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 104 105 return 0; 106 } 107 108 static void jz_lcd_desc_init(vidinfo_t *vid) 109 { 110 struct jz_fb_info * fbi; 111 fbi = &vid->jz_fb; 112 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 113 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 114 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 115 116 #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) 117 118 /* populate descriptors */ 119 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 120 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); 121 fbi->dmadesc_fblow->fidr = 0; 122 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; 123 124 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 125 126 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 127 fbi->dmadesc_fbhigh->fidr = 0; 128 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ 129 130 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 131 fbi->dmadesc_palette->fidr = 0; 132 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 133 134 if(NBITS(vid->vl_bpix) < 12) 135 { 136 /* assume any mode with <12 bpp is palette driven */ 137 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 138 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 139 /* flips back and forth between pal and fbhigh */ 140 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 141 } else { 142 /* palette shouldn't be loaded in true-color mode */ 143 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 144 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 145 } 146 147 flush_cache_all(); 148 } 149 150 static int jz_lcd_hw_init(vidinfo_t *vid) 151 { 152 struct jz_fb_info *fbi = &vid->jz_fb; 153 unsigned int val = 0; 154 unsigned int pclk; 155 unsigned int stnH; 156 int pll_div; 157 158 /* Setting Control register */ 159 switch (jzfb.bpp) { 160 case 1: 161 val |= LCD_CTRL_BPP_1; 162 break; 163 case 2: 164 val |= LCD_CTRL_BPP_2; 165 break; 166 case 4: 167 val |= LCD_CTRL_BPP_4; 168 break; 169 case 8: 170 val |= LCD_CTRL_BPP_8; 171 break; 172 case 15: 173 val |= LCD_CTRL_RGB555; 174 case 16: 175 val |= LCD_CTRL_BPP_16; 176 break; 177 case 17 ... 32: 178 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 179 break; 180 181 default: 182 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 183 val |= LCD_CTRL_BPP_16; 184 break; 185 } 186 187 switch (jzfb.cfg & MODE_MASK) { 188 case MODE_STN_MONO_DUAL: 189 case MODE_STN_COLOR_DUAL: 190 case MODE_STN_MONO_SINGLE: 191 case MODE_STN_COLOR_SINGLE: 192 switch (jzfb.bpp) { 193 case 1: 194 /* val |= LCD_CTRL_PEDN; */ 195 case 2: 196 val |= LCD_CTRL_FRC_2; 197 break; 198 case 4: 199 val |= LCD_CTRL_FRC_4; 200 break; 201 case 8: 202 default: 203 val |= LCD_CTRL_FRC_16; 204 break; 205 } 206 break; 207 } 208 209 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 210 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 211 212 switch (jzfb.cfg & MODE_MASK) { 213 case MODE_STN_MONO_DUAL: 214 case MODE_STN_COLOR_DUAL: 215 case MODE_STN_MONO_SINGLE: 216 case MODE_STN_COLOR_SINGLE: 217 switch (jzfb.cfg & STN_DAT_PINMASK) { 218 case STN_DAT_PIN1: 219 /* Do not adjust the hori-param value. */ 220 break; 221 case STN_DAT_PIN2: 222 align2(jzfb.hsw); 223 align2(jzfb.elw); 224 align2(jzfb.blw); 225 break; 226 case STN_DAT_PIN4: 227 align4(jzfb.hsw); 228 align4(jzfb.elw); 229 align4(jzfb.blw); 230 break; 231 case STN_DAT_PIN8: 232 align8(jzfb.hsw); 233 align8(jzfb.elw); 234 align8(jzfb.blw); 235 break; 236 } 237 break; 238 } 239 240 REG_LCD_CTRL = val; 241 242 switch (jzfb.cfg & MODE_MASK) { 243 case MODE_STN_MONO_DUAL: 244 case MODE_STN_COLOR_DUAL: 245 case MODE_STN_MONO_SINGLE: 246 case MODE_STN_COLOR_SINGLE: 247 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 248 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 249 stnH = jzfb.h >> 1; 250 else 251 stnH = jzfb.h; 252 253 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 254 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 255 256 /* Screen setting */ 257 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 258 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 259 REG_LCD_DAV = (0 << 16) | (stnH); 260 261 /* AC BIAs signal */ 262 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 263 264 break; 265 266 case MODE_TFT_GEN: 267 case MODE_TFT_SHARP: 268 case MODE_TFT_CASIO: 269 case MODE_TFT_SAMSUNG: 270 case MODE_8BIT_SERIAL_TFT: 271 case MODE_TFT_18BIT: 272 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 273 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 274 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 275 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 276 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 277 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 278 break; 279 } 280 281 switch (jzfb.cfg & MODE_MASK) { 282 case MODE_TFT_SAMSUNG: 283 { 284 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 285 unsigned int rev_s, rev_e, inv_s, inv_e; 286 287 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 288 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 289 290 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 291 tp_s = jzfb.blw + jzfb.w + 1; 292 tp_e = tp_s + 1; 293 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 294 ckv_s = tp_s - pclk/(1000000000/4100); 295 ckv_e = tp_s + total; 296 rev_s = tp_s - 11; /* -11.5 clk */ 297 rev_e = rev_s + total; 298 inv_s = tp_s; 299 inv_e = inv_s + total; 300 REG_LCD_CLS = (tp_s << 16) | tp_e; 301 REG_LCD_PS = (ckv_s << 16) | ckv_e; 302 REG_LCD_SPL = (rev_s << 16) | rev_e; 303 REG_LCD_REV = (inv_s << 16) | inv_e; 304 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 305 break; 306 } 307 case MODE_TFT_SHARP: 308 { 309 unsigned int total, cls_s, cls_e, ps_s, ps_e; 310 unsigned int spl_s, spl_e, rev_s, rev_e; 311 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 312 spl_s = 1; 313 spl_e = spl_s + 1; 314 cls_s = 0; 315 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 316 ps_s = cls_s; 317 ps_e = cls_e; 318 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 319 rev_e = rev_s + total; 320 jzfb.cfg |= STFT_PSHI; 321 REG_LCD_SPL = (spl_s << 16) | spl_e; 322 REG_LCD_CLS = (cls_s << 16) | cls_e; 323 REG_LCD_PS = (ps_s << 16) | ps_e; 324 REG_LCD_REV = (rev_s << 16) | rev_e; 325 break; 326 } 327 case MODE_TFT_CASIO: 328 break; 329 } 330 331 /* Configure the LCD panel */ 332 REG_LCD_CFG = jzfb.cfg; 333 334 /* Timing setting */ 335 __cpm_stop_lcd(); 336 337 val = jzfb.fclk; /* frame clk */ 338 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 339 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 340 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 341 } else { 342 /* serial mode: Hsync period = 3*Width_Pixel */ 343 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 344 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 345 } 346 347 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 348 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 349 pclk = (pclk * 3); 350 351 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 352 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 353 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 354 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 355 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 356 357 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 358 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 359 pclk >>= 1; 360 361 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 362 pll_div = pll_div ? 1 : 2 ; 363 val = ( __cpm_get_pllout()/pll_div ) / pclk; 364 val--; 365 if ( val > 0x1ff ) { 366 /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */ 367 val = 0x1ff; 368 } 369 __cpm_set_pixdiv(val); 370 371 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 372 if ( val > 150000000 ) { 373 /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */ 374 /* printf("Change LCDClock to 150MHz\n"); */ 375 val = 150000000; 376 } 377 val = ( __cpm_get_pllout()/pll_div ) / val; 378 val--; 379 if ( val > 0x1f ) { 380 /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */ 381 val = 0x1f; 382 } 383 __cpm_set_ldiv( val ); 384 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 385 386 __cpm_start_lcd(); 387 udelay(1000); 388 389 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 390 391 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 392 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 393 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 394 395 return 0; 396 } 397 398 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 399 { 400 } 401 402 void lcd_initcolregs (void) 403 { 404 }