1 /* 2 * Include file for Ingenic Semiconductor's JZ4740 CPU. 3 * 4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. 5 * Copyright (C) 2009 Qi Hardware Inc. 6 * Author: Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 #ifndef __JZ4740_H__ 25 #define __JZ4740_H__ 26 27 #include "xburst_types.h" 28 29 /* NOTE: Independent of usbboot parameters. */ 30 31 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ 32 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ 33 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ 34 35 #define JZ_EXTAL CONFIG_SYS_EXTAL 36 #define JZ_EXTAL2 32768 /* RTC clock */ 37 38 /* Boot ROM Specification */ 39 /* NOR Boot config */ 40 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ 41 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ 42 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ 43 44 /* NAND Boot config */ 45 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ 46 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ 47 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ 48 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ 49 50 51 /* Register Definitions */ 52 #define CPM_BASE 0xB0000000 53 #define INTC_BASE 0xB0001000 54 #define TCU_BASE 0xB0002000 55 #define WDT_BASE 0xB0002000 56 #define RTC_BASE 0xB0003000 57 #define GPIO_BASE 0xB0010000 58 #define AIC_BASE 0xB0020000 59 #define ICDC_BASE 0xB0020000 60 #define MSC_BASE 0xB0021000 61 #define UART0_BASE 0xB0030000 62 #define I2C_BASE 0xB0042000 63 #define SSI_BASE 0xB0043000 64 #define SADC_BASE 0xB0070000 65 #define EMC_BASE 0xB3010000 66 #define DMAC_BASE 0xB3020000 67 #define UHC_BASE 0xB3030000 68 #define UDC_BASE 0xB3040000 69 #define LCD_BASE 0xB3050000 70 #define SLCD_BASE 0xB3050000 71 #define CIM_BASE 0xB3060000 72 #define ETH_BASE 0xB3100000 73 74 75 /* 76 * INTC (Interrupt Controller) 77 */ 78 #define INTC_ISR (INTC_BASE + 0x00) 79 #define INTC_IMR (INTC_BASE + 0x04) 80 #define INTC_IMSR (INTC_BASE + 0x08) 81 #define INTC_IMCR (INTC_BASE + 0x0c) 82 #define INTC_IPR (INTC_BASE + 0x10) 83 84 #define REG_INTC_ISR REG32(INTC_ISR) 85 #define REG_INTC_IMR REG32(INTC_IMR) 86 #define REG_INTC_IMSR REG32(INTC_IMSR) 87 #define REG_INTC_IMCR REG32(INTC_IMCR) 88 #define REG_INTC_IPR REG32(INTC_IPR) 89 90 /* 1st-level interrupts */ 91 #define IRQ_I2C 1 92 #define IRQ_UHC 3 93 #define IRQ_UART0 9 94 #define IRQ_SADC 12 95 #define IRQ_MSC 14 96 #define IRQ_RTC 15 97 #define IRQ_SSI 16 98 #define IRQ_CIM 17 99 #define IRQ_AIC 18 100 #define IRQ_ETH 19 101 #define IRQ_DMAC 20 102 #define IRQ_TCU2 21 103 #define IRQ_TCU1 22 104 #define IRQ_TCU0 23 105 #define IRQ_UDC 24 106 #define IRQ_GPIO3 25 107 #define IRQ_GPIO2 26 108 #define IRQ_GPIO1 27 109 #define IRQ_GPIO0 28 110 #define IRQ_IPU 29 111 #define IRQ_LCD 30 112 113 /* 2nd-level interrupts */ 114 #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ 115 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ 116 117 118 /* 119 * RTC 120 */ 121 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ 122 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ 123 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ 124 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ 125 126 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ 127 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ 128 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ 129 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ 130 #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ 131 #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ 132 133 #define REG_RTC_RCR REG32(RTC_RCR) 134 #define REG_RTC_RSR REG32(RTC_RSR) 135 #define REG_RTC_RSAR REG32(RTC_RSAR) 136 #define REG_RTC_RGR REG32(RTC_RGR) 137 #define REG_RTC_HCR REG32(RTC_HCR) 138 #define REG_RTC_HWFCR REG32(RTC_HWFCR) 139 #define REG_RTC_HRCR REG32(RTC_HRCR) 140 #define REG_RTC_HWCR REG32(RTC_HWCR) 141 #define REG_RTC_HWRSR REG32(RTC_HWRSR) 142 #define REG_RTC_HSPR REG32(RTC_HSPR) 143 144 /* RTC Control Register */ 145 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ 146 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ 147 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ 148 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */ 149 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ 150 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ 151 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ 152 153 /* RTC Regulator Register */ 154 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ 155 #define RTC_RGR_ADJC_BIT 16 156 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) 157 #define RTC_RGR_NC1HZ_BIT 0 158 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) 159 160 /* Hibernate Control Register */ 161 #define RTC_HCR_PD (1 << 0) /* Power Down */ 162 163 /* Hibernate Wakeup Filter Counter Register */ 164 #define RTC_HWFCR_BIT 5 165 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) 166 167 /* Hibernate Reset Counter Register */ 168 #define RTC_HRCR_BIT 5 169 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) 170 171 /* Hibernate Wakeup Control Register */ 172 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ 173 174 /* Hibernate Wakeup Status Register */ 175 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ 176 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ 177 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ 178 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ 179 180 /************************************************************************* 181 * CPM (Clock reset and Power control Management) 182 *************************************************************************/ 183 184 /* Register definitions with absolute positioning have been removed. */ 185 186 /* Clock Control Register */ 187 #define CPM_CPCCR_I2CS (1 << 31) 188 #define CPM_CPCCR_CLKOEN (1 << 30) 189 #define CPM_CPCCR_UCS (1 << 29) 190 #define CPM_CPCCR_UDIV_BIT 23 191 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) 192 #define CPM_CPCCR_CE (1 << 22) 193 #define CPM_CPCCR_PCS (1 << 21) 194 #define CPM_CPCCR_LDIV_BIT 16 195 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) 196 #define CPM_CPCCR_MDIV_BIT 12 197 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) 198 #define CPM_CPCCR_PDIV_BIT 8 199 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) 200 #define CPM_CPCCR_HDIV_BIT 4 201 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) 202 #define CPM_CPCCR_CDIV_BIT 0 203 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) 204 205 /* I2S Clock Divider Register */ 206 #define CPM_I2SCDR_I2SDIV_BIT 0 207 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) 208 209 /* LCD Pixel Clock Divider Register */ 210 #define CPM_LPCDR_PIXDIV_BIT 0 211 #define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT) 212 213 /* MSC Clock Divider Register */ 214 #define CPM_MSCCDR_MSCDIV_BIT 0 215 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) 216 217 /* PLL Control Register */ 218 #define CPM_CPPCR_PLLM_BIT 23 219 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) 220 #define CPM_CPPCR_PLLN_BIT 18 221 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) 222 #define CPM_CPPCR_PLLOD_BIT 16 223 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) 224 #define CPM_CPPCR_PLLS (1 << 10) 225 #define CPM_CPPCR_PLLBP (1 << 9) 226 #define CPM_CPPCR_PLLEN (1 << 8) 227 #define CPM_CPPCR_PLLST_BIT 0 228 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) 229 230 /* Low Power Control Register */ 231 #define CPM_LCR_DOZE_DUTY_BIT 3 232 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) 233 #define CPM_LCR_DOZE_ON (1 << 2) 234 #define CPM_LCR_LPM_BIT 0 235 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) 236 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) 237 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) 238 239 /* Clock Gate Register */ 240 #define CPM_CLKGR_UART1 (1 << 15) 241 #define CPM_CLKGR_UHC (1 << 14) 242 #define CPM_CLKGR_IPU (1 << 13) 243 #define CPM_CLKGR_DMAC (1 << 12) 244 #define CPM_CLKGR_UDC (1 << 11) 245 #define CPM_CLKGR_LCD (1 << 10) 246 #define CPM_CLKGR_CIM (1 << 9) 247 #define CPM_CLKGR_SADC (1 << 8) 248 #define CPM_CLKGR_MSC (1 << 7) 249 #define CPM_CLKGR_AIC1 (1 << 6) 250 #define CPM_CLKGR_AIC2 (1 << 5) 251 #define CPM_CLKGR_SSI (1 << 4) 252 #define CPM_CLKGR_I2C (1 << 3) 253 #define CPM_CLKGR_RTC (1 << 2) 254 #define CPM_CLKGR_TCU (1 << 1) 255 #define CPM_CLKGR_UART0 (1 << 0) 256 257 /* Sleep Control Register */ 258 #define CPM_SCR_O1ST_BIT 8 259 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) 260 #define CPM_SCR_UDCPHY_ENABLE (1 << 6) 261 #define CPM_SCR_USBPHY_DISABLE (1 << 7) 262 #define CPM_SCR_OSC_ENABLE (1 << 4) 263 264 /* Hibernate Control Register */ 265 #define CPM_HCR_PD (1 << 0) 266 267 /* Wakeup Filter Counter Register in Hibernate Mode */ 268 #define CPM_HWFCR_TIME_BIT 0 269 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) 270 271 /* Reset Counter Register in Hibernate Mode */ 272 #define CPM_HRCR_TIME_BIT 0 273 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) 274 275 /* Wakeup Control Register in Hibernate Mode */ 276 #define CPM_HWCR_WLE_LOW (0 << 2) 277 #define CPM_HWCR_WLE_HIGH (1 << 2) 278 #define CPM_HWCR_PIN_WAKEUP (1 << 1) 279 #define CPM_HWCR_RTC_WAKEUP (1 << 0) 280 281 /* Wakeup Status Register in Hibernate Mode */ 282 #define CPM_HWSR_WSR_PIN (1 << 1) 283 #define CPM_HWSR_WSR_RTC (1 << 0) 284 285 /* Reset Status Register */ 286 #define CPM_RSR_HR (1 << 2) 287 #define CPM_RSR_WR (1 << 1) 288 #define CPM_RSR_PR (1 << 0) 289 290 291 /************************************************************************* 292 * TCU (Timer Counter Unit) 293 *************************************************************************/ 294 #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ 295 #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ 296 #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ 297 #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ 298 #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ 299 #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ 300 #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ 301 #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ 302 #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ 303 #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ 304 #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ 305 #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ 306 #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ 307 #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ 308 #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ 309 #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ 310 #define TCU_TDFR1 (TCU_BASE + 0x50) 311 #define TCU_TDHR1 (TCU_BASE + 0x54) 312 #define TCU_TCNT1 (TCU_BASE + 0x58) 313 #define TCU_TCSR1 (TCU_BASE + 0x5C) 314 #define TCU_TDFR2 (TCU_BASE + 0x60) 315 #define TCU_TDHR2 (TCU_BASE + 0x64) 316 #define TCU_TCNT2 (TCU_BASE + 0x68) 317 #define TCU_TCSR2 (TCU_BASE + 0x6C) 318 #define TCU_TDFR3 (TCU_BASE + 0x70) 319 #define TCU_TDHR3 (TCU_BASE + 0x74) 320 #define TCU_TCNT3 (TCU_BASE + 0x78) 321 #define TCU_TCSR3 (TCU_BASE + 0x7C) 322 #define TCU_TDFR4 (TCU_BASE + 0x80) 323 #define TCU_TDHR4 (TCU_BASE + 0x84) 324 #define TCU_TCNT4 (TCU_BASE + 0x88) 325 #define TCU_TCSR4 (TCU_BASE + 0x8C) 326 #define TCU_TDFR5 (TCU_BASE + 0x90) 327 #define TCU_TDHR5 (TCU_BASE + 0x94) 328 #define TCU_TCNT5 (TCU_BASE + 0x98) 329 #define TCU_TCSR5 (TCU_BASE + 0x9C) 330 331 #define REG_TCU_TSR REG32(TCU_TSR) 332 #define REG_TCU_TSSR REG32(TCU_TSSR) 333 #define REG_TCU_TSCR REG32(TCU_TSCR) 334 #define REG_TCU_TER REG8(TCU_TER) 335 #define REG_TCU_TESR REG8(TCU_TESR) 336 #define REG_TCU_TECR REG8(TCU_TECR) 337 #define REG_TCU_TFR REG32(TCU_TFR) 338 #define REG_TCU_TFSR REG32(TCU_TFSR) 339 #define REG_TCU_TFCR REG32(TCU_TFCR) 340 #define REG_TCU_TMR REG32(TCU_TMR) 341 #define REG_TCU_TMSR REG32(TCU_TMSR) 342 #define REG_TCU_TMCR REG32(TCU_TMCR) 343 #define REG_TCU_TDFR0 REG16(TCU_TDFR0) 344 #define REG_TCU_TDHR0 REG16(TCU_TDHR0) 345 #define REG_TCU_TCNT0 REG16(TCU_TCNT0) 346 #define REG_TCU_TCSR0 REG16(TCU_TCSR0) 347 #define REG_TCU_TDFR1 REG16(TCU_TDFR1) 348 #define REG_TCU_TDHR1 REG16(TCU_TDHR1) 349 #define REG_TCU_TCNT1 REG16(TCU_TCNT1) 350 #define REG_TCU_TCSR1 REG16(TCU_TCSR1) 351 #define REG_TCU_TDFR2 REG16(TCU_TDFR2) 352 #define REG_TCU_TDHR2 REG16(TCU_TDHR2) 353 #define REG_TCU_TCNT2 REG16(TCU_TCNT2) 354 #define REG_TCU_TCSR2 REG16(TCU_TCSR2) 355 #define REG_TCU_TDFR3 REG16(TCU_TDFR3) 356 #define REG_TCU_TDHR3 REG16(TCU_TDHR3) 357 #define REG_TCU_TCNT3 REG16(TCU_TCNT3) 358 #define REG_TCU_TCSR3 REG16(TCU_TCSR3) 359 #define REG_TCU_TDFR4 REG16(TCU_TDFR4) 360 #define REG_TCU_TDHR4 REG16(TCU_TDHR4) 361 #define REG_TCU_TCNT4 REG16(TCU_TCNT4) 362 #define REG_TCU_TCSR4 REG16(TCU_TCSR4) 363 364 /* n = 0,1,2,3,4,5 */ 365 #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ 366 #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ 367 #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ 368 #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ 369 370 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) 371 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) 372 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) 373 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) 374 375 /* Register definitions */ 376 #define TCU_TCSR_PWM_SD (1 << 9) 377 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) 378 #define TCU_TCSR_PWM_EN (1 << 7) 379 #define TCU_TCSR_PRESCALE_BIT 3 380 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) 381 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) 382 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) 383 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) 384 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) 385 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) 386 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) 387 #define TCU_TCSR_EXT_EN (1 << 2) 388 #define TCU_TCSR_RTC_EN (1 << 1) 389 #define TCU_TCSR_PCK_EN (1 << 0) 390 391 #define TCU_TER_TCEN5 (1 << 5) 392 #define TCU_TER_TCEN4 (1 << 4) 393 #define TCU_TER_TCEN3 (1 << 3) 394 #define TCU_TER_TCEN2 (1 << 2) 395 #define TCU_TER_TCEN1 (1 << 1) 396 #define TCU_TER_TCEN0 (1 << 0) 397 398 #define TCU_TESR_TCST5 (1 << 5) 399 #define TCU_TESR_TCST4 (1 << 4) 400 #define TCU_TESR_TCST3 (1 << 3) 401 #define TCU_TESR_TCST2 (1 << 2) 402 #define TCU_TESR_TCST1 (1 << 1) 403 #define TCU_TESR_TCST0 (1 << 0) 404 405 #define TCU_TECR_TCCL5 (1 << 5) 406 #define TCU_TECR_TCCL4 (1 << 4) 407 #define TCU_TECR_TCCL3 (1 << 3) 408 #define TCU_TECR_TCCL2 (1 << 2) 409 #define TCU_TECR_TCCL1 (1 << 1) 410 #define TCU_TECR_TCCL0 (1 << 0) 411 412 #define TCU_TFR_HFLAG5 (1 << 21) 413 #define TCU_TFR_HFLAG4 (1 << 20) 414 #define TCU_TFR_HFLAG3 (1 << 19) 415 #define TCU_TFR_HFLAG2 (1 << 18) 416 #define TCU_TFR_HFLAG1 (1 << 17) 417 #define TCU_TFR_HFLAG0 (1 << 16) 418 #define TCU_TFR_FFLAG5 (1 << 5) 419 #define TCU_TFR_FFLAG4 (1 << 4) 420 #define TCU_TFR_FFLAG3 (1 << 3) 421 #define TCU_TFR_FFLAG2 (1 << 2) 422 #define TCU_TFR_FFLAG1 (1 << 1) 423 #define TCU_TFR_FFLAG0 (1 << 0) 424 425 #define TCU_TFSR_HFLAG5 (1 << 21) 426 #define TCU_TFSR_HFLAG4 (1 << 20) 427 #define TCU_TFSR_HFLAG3 (1 << 19) 428 #define TCU_TFSR_HFLAG2 (1 << 18) 429 #define TCU_TFSR_HFLAG1 (1 << 17) 430 #define TCU_TFSR_HFLAG0 (1 << 16) 431 #define TCU_TFSR_FFLAG5 (1 << 5) 432 #define TCU_TFSR_FFLAG4 (1 << 4) 433 #define TCU_TFSR_FFLAG3 (1 << 3) 434 #define TCU_TFSR_FFLAG2 (1 << 2) 435 #define TCU_TFSR_FFLAG1 (1 << 1) 436 #define TCU_TFSR_FFLAG0 (1 << 0) 437 438 #define TCU_TFCR_HFLAG5 (1 << 21) 439 #define TCU_TFCR_HFLAG4 (1 << 20) 440 #define TCU_TFCR_HFLAG3 (1 << 19) 441 #define TCU_TFCR_HFLAG2 (1 << 18) 442 #define TCU_TFCR_HFLAG1 (1 << 17) 443 #define TCU_TFCR_HFLAG0 (1 << 16) 444 #define TCU_TFCR_FFLAG5 (1 << 5) 445 #define TCU_TFCR_FFLAG4 (1 << 4) 446 #define TCU_TFCR_FFLAG3 (1 << 3) 447 #define TCU_TFCR_FFLAG2 (1 << 2) 448 #define TCU_TFCR_FFLAG1 (1 << 1) 449 #define TCU_TFCR_FFLAG0 (1 << 0) 450 451 #define TCU_TMR_HMASK5 (1 << 21) 452 #define TCU_TMR_HMASK4 (1 << 20) 453 #define TCU_TMR_HMASK3 (1 << 19) 454 #define TCU_TMR_HMASK2 (1 << 18) 455 #define TCU_TMR_HMASK1 (1 << 17) 456 #define TCU_TMR_HMASK0 (1 << 16) 457 #define TCU_TMR_FMASK5 (1 << 5) 458 #define TCU_TMR_FMASK4 (1 << 4) 459 #define TCU_TMR_FMASK3 (1 << 3) 460 #define TCU_TMR_FMASK2 (1 << 2) 461 #define TCU_TMR_FMASK1 (1 << 1) 462 #define TCU_TMR_FMASK0 (1 << 0) 463 464 #define TCU_TMSR_HMST5 (1 << 21) 465 #define TCU_TMSR_HMST4 (1 << 20) 466 #define TCU_TMSR_HMST3 (1 << 19) 467 #define TCU_TMSR_HMST2 (1 << 18) 468 #define TCU_TMSR_HMST1 (1 << 17) 469 #define TCU_TMSR_HMST0 (1 << 16) 470 #define TCU_TMSR_FMST5 (1 << 5) 471 #define TCU_TMSR_FMST4 (1 << 4) 472 #define TCU_TMSR_FMST3 (1 << 3) 473 #define TCU_TMSR_FMST2 (1 << 2) 474 #define TCU_TMSR_FMST1 (1 << 1) 475 #define TCU_TMSR_FMST0 (1 << 0) 476 477 #define TCU_TMCR_HMCL5 (1 << 21) 478 #define TCU_TMCR_HMCL4 (1 << 20) 479 #define TCU_TMCR_HMCL3 (1 << 19) 480 #define TCU_TMCR_HMCL2 (1 << 18) 481 #define TCU_TMCR_HMCL1 (1 << 17) 482 #define TCU_TMCR_HMCL0 (1 << 16) 483 #define TCU_TMCR_FMCL5 (1 << 5) 484 #define TCU_TMCR_FMCL4 (1 << 4) 485 #define TCU_TMCR_FMCL3 (1 << 3) 486 #define TCU_TMCR_FMCL2 (1 << 2) 487 #define TCU_TMCR_FMCL1 (1 << 1) 488 #define TCU_TMCR_FMCL0 (1 << 0) 489 490 #define TCU_TSR_WDTS (1 << 16) 491 #define TCU_TSR_STOP5 (1 << 5) 492 #define TCU_TSR_STOP4 (1 << 4) 493 #define TCU_TSR_STOP3 (1 << 3) 494 #define TCU_TSR_STOP2 (1 << 2) 495 #define TCU_TSR_STOP1 (1 << 1) 496 #define TCU_TSR_STOP0 (1 << 0) 497 498 #define TCU_TSSR_WDTSS (1 << 16) 499 #define TCU_TSSR_STPS5 (1 << 5) 500 #define TCU_TSSR_STPS4 (1 << 4) 501 #define TCU_TSSR_STPS3 (1 << 3) 502 #define TCU_TSSR_STPS2 (1 << 2) 503 #define TCU_TSSR_STPS1 (1 << 1) 504 #define TCU_TSSR_STPS0 (1 << 0) 505 506 #define TCU_TSSR_WDTSC (1 << 16) 507 #define TCU_TSSR_STPC5 (1 << 5) 508 #define TCU_TSSR_STPC4 (1 << 4) 509 #define TCU_TSSR_STPC3 (1 << 3) 510 #define TCU_TSSR_STPC2 (1 << 2) 511 #define TCU_TSSR_STPC1 (1 << 1) 512 #define TCU_TSSR_STPC0 (1 << 0) 513 514 515 /* 516 * WDT (WatchDog Timer) 517 */ 518 #define WDT_TDR (WDT_BASE + 0x00) 519 #define WDT_TCER (WDT_BASE + 0x04) 520 #define WDT_TCNT (WDT_BASE + 0x08) 521 #define WDT_TCSR (WDT_BASE + 0x0C) 522 523 #define REG_WDT_TDR REG16(WDT_TDR) 524 #define REG_WDT_TCER REG8(WDT_TCER) 525 #define REG_WDT_TCNT REG16(WDT_TCNT) 526 #define REG_WDT_TCSR REG16(WDT_TCSR) 527 528 /* Register definition */ 529 #define WDT_TCSR_PRESCALE_BIT 3 530 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) 531 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) 532 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) 533 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) 534 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) 535 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) 536 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) 537 #define WDT_TCSR_EXT_EN (1 << 2) 538 #define WDT_TCSR_RTC_EN (1 << 1) 539 #define WDT_TCSR_PCK_EN (1 << 0) 540 541 #define WDT_TCER_TCEN (1 << 0) 542 543 544 /* 545 * DMAC (DMA Controller) 546 */ 547 548 #define MAX_DMA_NUM 6 /* max 6 channels */ 549 550 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ 551 #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ 552 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ 553 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ 554 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ 555 #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ 556 #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ 557 #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ 558 #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ 559 #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ 560 #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ 561 562 /* channel 0 */ 563 #define DMAC_DSAR0 DMAC_DSAR(0) 564 #define DMAC_DTAR0 DMAC_DTAR(0) 565 #define DMAC_DTCR0 DMAC_DTCR(0) 566 #define DMAC_DRSR0 DMAC_DRSR(0) 567 #define DMAC_DCCSR0 DMAC_DCCSR(0) 568 #define DMAC_DCMD0 DMAC_DCMD(0) 569 #define DMAC_DDA0 DMAC_DDA(0) 570 571 /* channel 1 */ 572 #define DMAC_DSAR1 DMAC_DSAR(1) 573 #define DMAC_DTAR1 DMAC_DTAR(1) 574 #define DMAC_DTCR1 DMAC_DTCR(1) 575 #define DMAC_DRSR1 DMAC_DRSR(1) 576 #define DMAC_DCCSR1 DMAC_DCCSR(1) 577 #define DMAC_DCMD1 DMAC_DCMD(1) 578 #define DMAC_DDA1 DMAC_DDA(1) 579 580 /* channel 2 */ 581 #define DMAC_DSAR2 DMAC_DSAR(2) 582 #define DMAC_DTAR2 DMAC_DTAR(2) 583 #define DMAC_DTCR2 DMAC_DTCR(2) 584 #define DMAC_DRSR2 DMAC_DRSR(2) 585 #define DMAC_DCCSR2 DMAC_DCCSR(2) 586 #define DMAC_DCMD2 DMAC_DCMD(2) 587 #define DMAC_DDA2 DMAC_DDA(2) 588 589 /* channel 3 */ 590 #define DMAC_DSAR3 DMAC_DSAR(3) 591 #define DMAC_DTAR3 DMAC_DTAR(3) 592 #define DMAC_DTCR3 DMAC_DTCR(3) 593 #define DMAC_DRSR3 DMAC_DRSR(3) 594 #define DMAC_DCCSR3 DMAC_DCCSR(3) 595 #define DMAC_DCMD3 DMAC_DCMD(3) 596 #define DMAC_DDA3 DMAC_DDA(3) 597 598 /* channel 4 */ 599 #define DMAC_DSAR4 DMAC_DSAR(4) 600 #define DMAC_DTAR4 DMAC_DTAR(4) 601 #define DMAC_DTCR4 DMAC_DTCR(4) 602 #define DMAC_DRSR4 DMAC_DRSR(4) 603 #define DMAC_DCCSR4 DMAC_DCCSR(4) 604 #define DMAC_DCMD4 DMAC_DCMD(4) 605 #define DMAC_DDA4 DMAC_DDA(4) 606 607 /* channel 5 */ 608 #define DMAC_DSAR5 DMAC_DSAR(5) 609 #define DMAC_DTAR5 DMAC_DTAR(5) 610 #define DMAC_DTCR5 DMAC_DTCR(5) 611 #define DMAC_DRSR5 DMAC_DRSR(5) 612 #define DMAC_DCCSR5 DMAC_DCCSR(5) 613 #define DMAC_DCMD5 DMAC_DCMD(5) 614 #define DMAC_DDA5 DMAC_DDA(5) 615 616 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) 617 #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) 618 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) 619 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) 620 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) 621 #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) 622 #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) 623 #define REG_DMAC_DMACR REG32(DMAC_DMACR) 624 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) 625 #define REG_DMAC_DMADBR REG32(DMAC_DMADBR) 626 #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) 627 628 /* DMA request source register */ 629 #define DMAC_DRSR_RS_BIT 0 630 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) 631 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) 632 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) 633 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) 634 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) 635 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) 636 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) 637 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) 638 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) 639 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) 640 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) 641 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) 642 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) 643 644 /* DMA channel control/status register */ 645 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ 646 #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ 647 #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) 648 #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ 649 #define DMAC_DCCSR_AR (1 << 4) /* address error */ 650 #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ 651 #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ 652 #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ 653 #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ 654 655 /* DMA channel command register */ 656 #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ 657 #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ 658 #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ 659 #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) 660 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) 661 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) 662 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) 663 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) 664 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) 665 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) 666 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) 667 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) 668 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) 669 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) 670 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) 671 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) 672 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) 673 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) 674 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) 675 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) 676 #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ 677 #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) 678 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) 679 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) 680 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) 681 #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ 682 #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) 683 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) 684 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) 685 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) 686 #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ 687 #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) 688 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) 689 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) 690 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) 691 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) 692 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) 693 #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ 694 #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ 695 #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ 696 #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ 697 #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ 698 #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ 699 700 /* DMA descriptor address register */ 701 #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ 702 #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) 703 #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ 704 #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) 705 706 /* DMA control register */ 707 #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ 708 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) 709 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) 710 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) 711 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) 712 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ 713 #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ 714 #define DMAC_DMACR_AR (1 << 2) /* address error flag */ 715 #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ 716 717 /* DMA doorbell register */ 718 #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ 719 #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ 720 #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ 721 #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ 722 #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ 723 #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ 724 725 /* DMA doorbell set register */ 726 #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ 727 #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ 728 #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ 729 #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ 730 #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ 731 #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ 732 733 /* DMA interrupt pending register */ 734 #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ 735 #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ 736 #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ 737 #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ 738 #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ 739 #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ 740 741 742 /************************************************************************* 743 * GPIO (General-Purpose I/O Ports) 744 *************************************************************************/ 745 746 /* Register definitions with absolute positioning have been removed. */ 747 748 #define MAX_GPIO_NUM 128 749 750 /************************************************************************* 751 * UART 752 *************************************************************************/ 753 754 #define IRDA_BASE UART0_BASE 755 /* #define UART_BASE UART0_BASE */ 756 #define UART_OFF 0x1000 757 758 /* Register Offset */ 759 #define OFF_RDR (0x00) /* R 8b H'xx */ 760 #define OFF_TDR (0x00) /* W 8b H'xx */ 761 #define OFF_DLLR (0x00) /* RW 8b H'00 */ 762 #define OFF_DLHR (0x04) /* RW 8b H'00 */ 763 #define OFF_IER (0x04) /* RW 8b H'00 */ 764 #define OFF_ISR (0x08) /* R 8b H'01 */ 765 #define OFF_FCR (0x08) /* W 8b H'00 */ 766 #define OFF_LCR (0x0C) /* RW 8b H'00 */ 767 #define OFF_MCR (0x10) /* RW 8b H'00 */ 768 #define OFF_LSR (0x14) /* R 8b H'00 */ 769 #define OFF_MSR (0x18) /* R 8b H'00 */ 770 #define OFF_SPR (0x1C) /* RW 8b H'00 */ 771 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ 772 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ 773 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ 774 775 /* Register Address */ 776 #define UART0_RDR (UART0_BASE + OFF_RDR) 777 #define UART0_TDR (UART0_BASE + OFF_TDR) 778 #define UART0_DLLR (UART0_BASE + OFF_DLLR) 779 #define UART0_DLHR (UART0_BASE + OFF_DLHR) 780 #define UART0_IER (UART0_BASE + OFF_IER) 781 #define UART0_ISR (UART0_BASE + OFF_ISR) 782 #define UART0_FCR (UART0_BASE + OFF_FCR) 783 #define UART0_LCR (UART0_BASE + OFF_LCR) 784 #define UART0_MCR (UART0_BASE + OFF_MCR) 785 #define UART0_LSR (UART0_BASE + OFF_LSR) 786 #define UART0_MSR (UART0_BASE + OFF_MSR) 787 #define UART0_SPR (UART0_BASE + OFF_SPR) 788 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) 789 #define UART0_UMR (UART0_BASE + OFF_UMR) 790 #define UART0_UACR (UART0_BASE + OFF_UACR) 791 792 /* 793 * Define macros for UART_IER 794 * UART Interrupt Enable Register 795 */ 796 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ 797 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ 798 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ 799 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ 800 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ 801 802 /* 803 * Define macros for UART_ISR 804 * UART Interrupt Status Register 805 */ 806 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ 807 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ 808 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ 809 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ 810 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ 811 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ 812 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ 813 #define UART_ISR_FFMS_NO_FIFO (0 << 6) 814 #define UART_ISR_FFMS_FIFO_MODE (3 << 6) 815 816 /* 817 * Define macros for UART_FCR 818 * UART FIFO Control Register 819 */ 820 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ 821 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ 822 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ 823 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ 824 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ 825 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ 826 #define UART_FCR_RTRG_1 (0 << 6) 827 #define UART_FCR_RTRG_4 (1 << 6) 828 #define UART_FCR_RTRG_8 (2 << 6) 829 #define UART_FCR_RTRG_15 (3 << 6) 830 831 /* 832 * Define macros for UART_LCR 833 * UART Line Control Register 834 */ 835 #define UART_LCR_WLEN (3 << 0) /* word length */ 836 #define UART_LCR_WLEN_5 (0 << 0) 837 #define UART_LCR_WLEN_6 (1 << 0) 838 #define UART_LCR_WLEN_7 (2 << 0) 839 #define UART_LCR_WLEN_8 (3 << 0) 840 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 841 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 842 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 843 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 844 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 845 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 846 847 #define UART_LCR_PE (1 << 3) /* 0: parity disable */ 848 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ 849 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ 850 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ 851 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ 852 853 /* 854 * Define macros for UART_LSR 855 * UART Line Status Register 856 */ 857 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ 858 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ 859 #define UART_LSR_PER (1 << 2) /* 0: no parity error */ 860 #define UART_LSR_FER (1 << 3) /* 0; no framing error */ 861 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ 862 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ 863 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ 864 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ 865 866 /* 867 * Define macros for UART_MCR 868 * UART Modem Control Register 869 */ 870 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ 871 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ 872 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ 873 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ 874 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ 875 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ 876 877 /* 878 * Define macros for UART_MSR 879 * UART Modem Status Register 880 */ 881 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ 882 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ 883 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ 884 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ 885 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ 886 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ 887 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ 888 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ 889 890 /* 891 * Define macros for SIRCR 892 * Slow IrDA Control Register 893 */ 894 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ 895 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ 896 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length 897 1: 0 pulse width is 1.6us for 115.2Kbps */ 898 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ 899 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ 900 901 902 /************************************************************************* 903 * AIC (AC97/I2S Controller) 904 *************************************************************************/ 905 #define AIC_FR (AIC_BASE + 0x000) 906 #define AIC_CR (AIC_BASE + 0x004) 907 #define AIC_ACCR1 (AIC_BASE + 0x008) 908 #define AIC_ACCR2 (AIC_BASE + 0x00C) 909 #define AIC_I2SCR (AIC_BASE + 0x010) 910 #define AIC_SR (AIC_BASE + 0x014) 911 #define AIC_ACSR (AIC_BASE + 0x018) 912 #define AIC_I2SSR (AIC_BASE + 0x01C) 913 #define AIC_ACCAR (AIC_BASE + 0x020) 914 #define AIC_ACCDR (AIC_BASE + 0x024) 915 #define AIC_ACSAR (AIC_BASE + 0x028) 916 #define AIC_ACSDR (AIC_BASE + 0x02C) 917 #define AIC_I2SDIV (AIC_BASE + 0x030) 918 #define AIC_DR (AIC_BASE + 0x034) 919 920 #define REG_AIC_FR REG32(AIC_FR) 921 #define REG_AIC_CR REG32(AIC_CR) 922 #define REG_AIC_ACCR1 REG32(AIC_ACCR1) 923 #define REG_AIC_ACCR2 REG32(AIC_ACCR2) 924 #define REG_AIC_I2SCR REG32(AIC_I2SCR) 925 #define REG_AIC_SR REG32(AIC_SR) 926 #define REG_AIC_ACSR REG32(AIC_ACSR) 927 #define REG_AIC_I2SSR REG32(AIC_I2SSR) 928 #define REG_AIC_ACCAR REG32(AIC_ACCAR) 929 #define REG_AIC_ACCDR REG32(AIC_ACCDR) 930 #define REG_AIC_ACSAR REG32(AIC_ACSAR) 931 #define REG_AIC_ACSDR REG32(AIC_ACSDR) 932 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 933 #define REG_AIC_DR REG32(AIC_DR) 934 935 /* AIC Controller Configuration Register (AIC_FR) */ 936 937 #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ 938 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) 939 #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ 940 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) 941 #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ 942 #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ 943 #define AIC_FR_RST (1 << 3) /* AIC registers reset */ 944 #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ 945 #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ 946 #define AIC_FR_ENB (1 << 0) /* AIC enable bit */ 947 948 /* AIC Controller Common Control Register (AIC_CR) */ 949 950 #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ 951 #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) 952 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) 953 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) 954 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) 955 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) 956 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) 957 #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ 958 #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) 959 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) 960 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) 961 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) 962 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) 963 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) 964 #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ 965 #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ 966 #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ 967 #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ 968 #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ 969 #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ 970 #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ 971 #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ 972 #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ 973 #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ 974 #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ 975 #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ 976 #define AIC_CR_EREC (1 << 0) /* Enable Record Function */ 977 978 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ 979 980 #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ 981 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) 982 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ 983 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ 984 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ 985 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ 986 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ 987 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ 988 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ 989 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ 990 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ 991 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ 992 #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ 993 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) 994 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ 995 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ 996 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ 997 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ 998 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ 999 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ 1000 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ 1001 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ 1002 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ 1003 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ 1004 1005 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ 1006 1007 #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ 1008 #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ 1009 #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ 1010 #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ 1011 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) 1012 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ 1013 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ 1014 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ 1015 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ 1016 #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ 1017 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) 1018 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ 1019 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ 1020 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ 1021 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ 1022 #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ 1023 #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ 1024 #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ 1025 #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ 1026 1027 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ 1028 1029 #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ 1030 #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ 1031 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) 1032 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ 1033 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ 1034 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ 1035 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ 1036 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ 1037 #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ 1038 1039 /* AIC Controller FIFO Status Register (AIC_SR) */ 1040 1041 #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ 1042 #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) 1043 #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ 1044 #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) 1045 #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ 1046 #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ 1047 #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ 1048 #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ 1049 1050 /* AIC Controller AC-link Status Register (AIC_ACSR) */ 1051 1052 #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ 1053 #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ 1054 #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ 1055 #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ 1056 #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ 1057 #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ 1058 1059 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ 1060 1061 #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ 1062 1063 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ 1064 1065 #define AIC_ACCAR_CAR_BIT 0 1066 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) 1067 1068 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ 1069 1070 #define AIC_ACCDR_CDR_BIT 0 1071 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) 1072 1073 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ 1074 1075 #define AIC_ACSAR_SAR_BIT 0 1076 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) 1077 1078 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ 1079 1080 #define AIC_ACSDR_SDR_BIT 0 1081 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) 1082 1083 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ 1084 1085 #define AIC_I2SDIV_DIV_BIT 0 1086 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) 1087 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ 1088 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ 1089 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ 1090 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ 1091 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ 1092 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ 1093 1094 1095 /************************************************************************* 1096 * ICDC (Internal CODEC) 1097 *************************************************************************/ 1098 #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ 1099 #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ 1100 #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1101 #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ 1102 #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ 1103 #define ICDC_CDCCR1 (ICDC_BASE + 0x0080) 1104 #define ICDC_CDCCR2 (ICDC_BASE + 0x0084) 1105 1106 #define REG_ICDC_CR REG32(ICDC_CR) 1107 #define REG_ICDC_APWAIT REG32(ICDC_APWAIT) 1108 #define REG_ICDC_APPRE REG32(ICDC_APPRE) 1109 #define REG_ICDC_APHPEN REG32(ICDC_APHPEN) 1110 #define REG_ICDC_APSR REG32(ICDC_APSR) 1111 #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) 1112 #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) 1113 1114 /* ICDC Control Register */ 1115 #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ 1116 #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) 1117 #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ 1118 #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) 1119 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) 1120 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) 1121 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) 1122 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) 1123 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) 1124 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) 1125 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) 1126 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) 1127 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) 1128 #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ 1129 #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) 1130 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) 1131 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) 1132 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) 1133 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) 1134 #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ 1135 #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) 1136 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) 1137 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) 1138 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) 1139 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) 1140 #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ 1141 #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ 1142 #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ 1143 #define ICDC_CR_EADC (1 << 10) /* Enable ADC */ 1144 #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ 1145 #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ 1146 #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ 1147 #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ 1148 #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ 1149 #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ 1150 #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ 1151 #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ 1152 1153 /* Anti-Pop WAIT Stage Timing Control Register */ 1154 #define ICDC_APWAIT_WAITSN_BIT 0 1155 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) 1156 1157 /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1158 #define ICDC_APPRE_PRESN_BIT 0 1159 #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) 1160 1161 /* Anti-Pop HPEN Stage Timing Control Register */ 1162 #define ICDC_APHPEN_HPENSN_BIT 0 1163 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) 1164 1165 /* Anti-Pop Status Register */ 1166 #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ 1167 #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) 1168 #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ 1169 #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ 1170 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ 1171 #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ 1172 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ 1173 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ 1174 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ 1175 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ 1176 #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ 1177 #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) 1178 1179 1180 /************************************************************************* 1181 * I2C 1182 *************************************************************************/ 1183 #define I2C_DR (I2C_BASE + 0x000) 1184 #define I2C_CR (I2C_BASE + 0x004) 1185 #define I2C_SR (I2C_BASE + 0x008) 1186 #define I2C_GR (I2C_BASE + 0x00C) 1187 1188 #define REG_I2C_DR REG8(I2C_DR) 1189 #define REG_I2C_CR REG8(I2C_CR) 1190 #define REG_I2C_SR REG8(I2C_SR) 1191 #define REG_I2C_GR REG16(I2C_GR) 1192 1193 /* I2C Control Register (I2C_CR) */ 1194 1195 #define I2C_CR_IEN (1 << 4) 1196 #define I2C_CR_STA (1 << 3) 1197 #define I2C_CR_STO (1 << 2) 1198 #define I2C_CR_AC (1 << 1) 1199 #define I2C_CR_I2CE (1 << 0) 1200 1201 /* I2C Status Register (I2C_SR) */ 1202 1203 #define I2C_SR_STX (1 << 4) 1204 #define I2C_SR_BUSY (1 << 3) 1205 #define I2C_SR_TEND (1 << 2) 1206 #define I2C_SR_DRF (1 << 1) 1207 #define I2C_SR_ACKF (1 << 0) 1208 1209 1210 /************************************************************************* 1211 * SSI 1212 *************************************************************************/ 1213 #define SSI_DR (SSI_BASE + 0x000) 1214 #define SSI_CR0 (SSI_BASE + 0x004) 1215 #define SSI_CR1 (SSI_BASE + 0x008) 1216 #define SSI_SR (SSI_BASE + 0x00C) 1217 #define SSI_ITR (SSI_BASE + 0x010) 1218 #define SSI_ICR (SSI_BASE + 0x014) 1219 #define SSI_GR (SSI_BASE + 0x018) 1220 1221 #define REG_SSI_DR REG32(SSI_DR) 1222 #define REG_SSI_CR0 REG16(SSI_CR0) 1223 #define REG_SSI_CR1 REG32(SSI_CR1) 1224 #define REG_SSI_SR REG32(SSI_SR) 1225 #define REG_SSI_ITR REG16(SSI_ITR) 1226 #define REG_SSI_ICR REG8(SSI_ICR) 1227 #define REG_SSI_GR REG16(SSI_GR) 1228 1229 /* SSI Data Register (SSI_DR) */ 1230 1231 #define SSI_DR_GPC_BIT 0 1232 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) 1233 1234 /* SSI Control Register 0 (SSI_CR0) */ 1235 1236 #define SSI_CR0_SSIE (1 << 15) 1237 #define SSI_CR0_TIE (1 << 14) 1238 #define SSI_CR0_RIE (1 << 13) 1239 #define SSI_CR0_TEIE (1 << 12) 1240 #define SSI_CR0_REIE (1 << 11) 1241 #define SSI_CR0_LOOP (1 << 10) 1242 #define SSI_CR0_RFINE (1 << 9) 1243 #define SSI_CR0_RFINC (1 << 8) 1244 #define SSI_CR0_FSEL (1 << 6) 1245 #define SSI_CR0_TFLUSH (1 << 2) 1246 #define SSI_CR0_RFLUSH (1 << 1) 1247 #define SSI_CR0_DISREV (1 << 0) 1248 1249 /* SSI Control Register 1 (SSI_CR1) */ 1250 1251 #define SSI_CR1_FRMHL_BIT 30 1252 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) 1253 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ 1254 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ 1255 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ 1256 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ 1257 #define SSI_CR1_TFVCK_BIT 28 1258 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) 1259 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) 1260 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) 1261 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) 1262 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) 1263 #define SSI_CR1_TCKFI_BIT 26 1264 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) 1265 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) 1266 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) 1267 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) 1268 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) 1269 #define SSI_CR1_LFST (1 << 25) 1270 #define SSI_CR1_ITFRM (1 << 24) 1271 #define SSI_CR1_UNFIN (1 << 23) 1272 #define SSI_CR1_MULTS (1 << 22) 1273 #define SSI_CR1_FMAT_BIT 20 1274 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) 1275 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ 1276 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ 1277 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ 1278 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ 1279 #define SSI_CR1_TTRG_BIT 16 1280 #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) 1281 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) 1282 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) 1283 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) 1284 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) 1285 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) 1286 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) 1287 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) 1288 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) 1289 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) 1290 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) 1291 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) 1292 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) 1293 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) 1294 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) 1295 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) 1296 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) 1297 #define SSI_CR1_MCOM_BIT 12 1298 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) 1299 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ 1300 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ 1301 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ 1302 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ 1303 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ 1304 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ 1305 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ 1306 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ 1307 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ 1308 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ 1309 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ 1310 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ 1311 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ 1312 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ 1313 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ 1314 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ 1315 #define SSI_CR1_RTRG_BIT 8 1316 #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) 1317 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) 1318 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) 1319 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) 1320 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) 1321 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) 1322 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) 1323 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) 1324 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) 1325 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) 1326 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) 1327 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) 1328 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) 1329 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) 1330 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) 1331 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) 1332 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) 1333 #define SSI_CR1_FLEN_BIT 4 1334 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) 1335 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) 1336 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) 1337 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) 1338 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) 1339 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) 1340 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) 1341 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) 1342 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) 1343 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) 1344 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) 1345 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) 1346 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) 1347 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) 1348 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) 1349 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) 1350 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) 1351 #define SSI_CR1_PHA (1 << 1) 1352 #define SSI_CR1_POL (1 << 0) 1353 1354 /* SSI Status Register (SSI_SR) */ 1355 1356 #define SSI_SR_TFIFONUM_BIT 16 1357 #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) 1358 #define SSI_SR_RFIFONUM_BIT 8 1359 #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) 1360 #define SSI_SR_END (1 << 7) 1361 #define SSI_SR_BUSY (1 << 6) 1362 #define SSI_SR_TFF (1 << 5) 1363 #define SSI_SR_RFE (1 << 4) 1364 #define SSI_SR_TFHE (1 << 3) 1365 #define SSI_SR_RFHF (1 << 2) 1366 #define SSI_SR_UNDR (1 << 1) 1367 #define SSI_SR_OVER (1 << 0) 1368 1369 /* SSI Interval Time Control Register (SSI_ITR) */ 1370 1371 #define SSI_ITR_CNTCLK (1 << 15) 1372 #define SSI_ITR_IVLTM_BIT 0 1373 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) 1374 1375 1376 /************************************************************************* 1377 * MSC 1378 *************************************************************************/ 1379 #define MSC_STRPCL (MSC_BASE + 0x000) 1380 #define MSC_STAT (MSC_BASE + 0x004) 1381 #define MSC_CLKRT (MSC_BASE + 0x008) 1382 #define MSC_CMDAT (MSC_BASE + 0x00C) 1383 #define MSC_RESTO (MSC_BASE + 0x010) 1384 #define MSC_RDTO (MSC_BASE + 0x014) 1385 #define MSC_BLKLEN (MSC_BASE + 0x018) 1386 #define MSC_NOB (MSC_BASE + 0x01C) 1387 #define MSC_SNOB (MSC_BASE + 0x020) 1388 #define MSC_IMASK (MSC_BASE + 0x024) 1389 #define MSC_IREG (MSC_BASE + 0x028) 1390 #define MSC_CMD (MSC_BASE + 0x02C) 1391 #define MSC_ARG (MSC_BASE + 0x030) 1392 #define MSC_RES (MSC_BASE + 0x034) 1393 #define MSC_RXFIFO (MSC_BASE + 0x038) 1394 #define MSC_TXFIFO (MSC_BASE + 0x03C) 1395 1396 #define REG_MSC_STRPCL REG16(MSC_STRPCL) 1397 #define REG_MSC_STAT REG32(MSC_STAT) 1398 #define REG_MSC_CLKRT REG16(MSC_CLKRT) 1399 #define REG_MSC_CMDAT REG32(MSC_CMDAT) 1400 #define REG_MSC_RESTO REG16(MSC_RESTO) 1401 #define REG_MSC_RDTO REG16(MSC_RDTO) 1402 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) 1403 #define REG_MSC_NOB REG16(MSC_NOB) 1404 #define REG_MSC_SNOB REG16(MSC_SNOB) 1405 #define REG_MSC_IMASK REG16(MSC_IMASK) 1406 #define REG_MSC_IREG REG16(MSC_IREG) 1407 #define REG_MSC_CMD REG8(MSC_CMD) 1408 #define REG_MSC_ARG REG32(MSC_ARG) 1409 #define REG_MSC_RES REG16(MSC_RES) 1410 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) 1411 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) 1412 1413 /* MSC Clock and Control Register (MSC_STRPCL) */ 1414 1415 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) 1416 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) 1417 #define MSC_STRPCL_START_READWAIT (1 << 5) 1418 #define MSC_STRPCL_STOP_READWAIT (1 << 4) 1419 #define MSC_STRPCL_RESET (1 << 3) 1420 #define MSC_STRPCL_START_OP (1 << 2) 1421 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 1422 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) 1423 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ 1424 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ 1425 1426 /* MSC Status Register (MSC_STAT) */ 1427 1428 #define MSC_STAT_IS_RESETTING (1 << 15) 1429 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) 1430 #define MSC_STAT_PRG_DONE (1 << 13) 1431 #define MSC_STAT_DATA_TRAN_DONE (1 << 12) 1432 #define MSC_STAT_END_CMD_RES (1 << 11) 1433 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) 1434 #define MSC_STAT_IS_READWAIT (1 << 9) 1435 #define MSC_STAT_CLK_EN (1 << 8) 1436 #define MSC_STAT_DATA_FIFO_FULL (1 << 7) 1437 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) 1438 #define MSC_STAT_CRC_RES_ERR (1 << 5) 1439 #define MSC_STAT_CRC_READ_ERROR (1 << 4) 1440 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 1441 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) 1442 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ 1443 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ 1444 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ 1445 #define MSC_STAT_TIME_OUT_RES (1 << 1) 1446 #define MSC_STAT_TIME_OUT_READ (1 << 0) 1447 1448 /* MSC Bus Clock Control Register (MSC_CLKRT) */ 1449 1450 #define MSC_CLKRT_CLK_RATE_BIT 0 1451 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) 1452 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ 1453 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ 1454 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ 1455 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ 1456 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ 1457 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ 1458 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ 1459 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ 1460 1461 /* MSC Command Sequence Control Register (MSC_CMDAT) */ 1462 1463 #define MSC_CMDAT_IO_ABORT (1 << 11) 1464 #define MSC_CMDAT_BUS_WIDTH_BIT 9 1465 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) 1466 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) 1467 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) 1468 #define MSC_CMDAT_DMA_EN (1 << 8) 1469 #define MSC_CMDAT_INIT (1 << 7) 1470 #define MSC_CMDAT_BUSY (1 << 6) 1471 #define MSC_CMDAT_STREAM_BLOCK (1 << 5) 1472 #define MSC_CMDAT_WRITE (1 << 4) 1473 #define MSC_CMDAT_READ (0 << 4) 1474 #define MSC_CMDAT_DATA_EN (1 << 3) 1475 #define MSC_CMDAT_RESPONSE_BIT 0 1476 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) 1477 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) 1478 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) 1479 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) 1480 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) 1481 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) 1482 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) 1483 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) 1484 1485 /* MSC Interrupts Mask Register (MSC_IMASK) */ 1486 #define MSC_IMASK_SDIO (1 << 7) 1487 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) 1488 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) 1489 #define MSC_IMASK_END_CMD_RES (1 << 2) 1490 #define MSC_IMASK_PRG_DONE (1 << 1) 1491 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) 1492 1493 1494 /* MSC Interrupts Status Register (MSC_IREG) */ 1495 #define MSC_IREG_SDIO (1 << 7) 1496 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) 1497 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) 1498 #define MSC_IREG_END_CMD_RES (1 << 2) 1499 #define MSC_IREG_PRG_DONE (1 << 1) 1500 #define MSC_IREG_DATA_TRAN_DONE (1 << 0) 1501 1502 1503 /* 1504 * EMC (External Memory Controller) 1505 */ 1506 #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ 1507 1508 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ 1509 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ 1510 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ 1511 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ 1512 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ 1513 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ 1514 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ 1515 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ 1516 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ 1517 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ 1518 1519 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ 1520 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ 1521 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ 1522 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ 1523 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ 1524 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ 1525 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ 1526 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ 1527 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ 1528 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ 1529 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ 1530 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ 1531 1532 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ 1533 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ 1534 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ 1535 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ 1536 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ 1537 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ 1538 1539 #define REG_EMC_BCR REG32(EMC_BCR) 1540 1541 #define REG_EMC_SMCR0 REG32(EMC_SMCR0) 1542 #define REG_EMC_SMCR1 REG32(EMC_SMCR1) 1543 #define REG_EMC_SMCR2 REG32(EMC_SMCR2) 1544 #define REG_EMC_SMCR3 REG32(EMC_SMCR3) 1545 #define REG_EMC_SMCR4 REG32(EMC_SMCR4) 1546 #define REG_EMC_SACR0 REG32(EMC_SACR0) 1547 #define REG_EMC_SACR1 REG32(EMC_SACR1) 1548 #define REG_EMC_SACR2 REG32(EMC_SACR2) 1549 #define REG_EMC_SACR3 REG32(EMC_SACR3) 1550 #define REG_EMC_SACR4 REG32(EMC_SACR4) 1551 1552 #define REG_EMC_NFCSR REG32(EMC_NFCSR) 1553 #define REG_EMC_NFECR REG32(EMC_NFECR) 1554 #define REG_EMC_NFECC REG32(EMC_NFECC) 1555 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) 1556 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) 1557 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) 1558 #define REG_EMC_NFINTS REG32(EMC_NFINTS) 1559 #define REG_EMC_NFINTE REG32(EMC_NFINTE) 1560 #define REG_EMC_NFERR0 REG32(EMC_NFERR0) 1561 #define REG_EMC_NFERR1 REG32(EMC_NFERR1) 1562 #define REG_EMC_NFERR2 REG32(EMC_NFERR2) 1563 #define REG_EMC_NFERR3 REG32(EMC_NFERR3) 1564 1565 #define REG_EMC_DMCR REG32(EMC_DMCR) 1566 #define REG_EMC_RTCSR REG16(EMC_RTCSR) 1567 #define REG_EMC_RTCNT REG16(EMC_RTCNT) 1568 #define REG_EMC_RTCOR REG16(EMC_RTCOR) 1569 #define REG_EMC_DMAR0 REG32(EMC_DMAR0) 1570 1571 /* Static Memory Control Register */ 1572 #define EMC_SMCR_STRV_BIT 24 1573 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) 1574 #define EMC_SMCR_TAW_BIT 20 1575 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) 1576 #define EMC_SMCR_TBP_BIT 16 1577 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) 1578 #define EMC_SMCR_TAH_BIT 12 1579 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) 1580 #define EMC_SMCR_TAS_BIT 8 1581 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) 1582 #define EMC_SMCR_BW_BIT 6 1583 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) 1584 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) 1585 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) 1586 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) 1587 #define EMC_SMCR_BCM (1 << 3) 1588 #define EMC_SMCR_BL_BIT 1 1589 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) 1590 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) 1591 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) 1592 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) 1593 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) 1594 #define EMC_SMCR_SMT (1 << 0) 1595 1596 /* Static Memory Bank Addr Config Reg */ 1597 #define EMC_SACR_BASE_BIT 8 1598 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) 1599 #define EMC_SACR_MASK_BIT 0 1600 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) 1601 1602 /* NAND Flash Control/Status Register */ 1603 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ 1604 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ 1605 #define EMC_NFCSR_NFCE3 (1 << 5) 1606 #define EMC_NFCSR_NFE3 (1 << 4) 1607 #define EMC_NFCSR_NFCE2 (1 << 3) 1608 #define EMC_NFCSR_NFE2 (1 << 2) 1609 #define EMC_NFCSR_NFCE1 (1 << 1) 1610 #define EMC_NFCSR_NFE1 (1 << 0) 1611 1612 /* NAND Flash ECC Control Register */ 1613 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ 1614 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ 1615 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ 1616 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ 1617 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ 1618 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ 1619 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ 1620 1621 /* NAND Flash ECC Data Register */ 1622 #define EMC_NFECC_ECC2_BIT 16 1623 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) 1624 #define EMC_NFECC_ECC1_BIT 8 1625 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) 1626 #define EMC_NFECC_ECC0_BIT 0 1627 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) 1628 1629 /* NAND Flash Interrupt Status Register */ 1630 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ 1631 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) 1632 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ 1633 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ 1634 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ 1635 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ 1636 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ 1637 1638 /* NAND Flash Interrupt Enable Register */ 1639 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ 1640 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ 1641 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ 1642 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ 1643 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ 1644 1645 /* NAND Flash RS Error Report Register */ 1646 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ 1647 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) 1648 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ 1649 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) 1650 1651 1652 /* DRAM Control Register */ 1653 #define EMC_DMCR_BW_BIT 31 1654 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) 1655 #define EMC_DMCR_CA_BIT 26 1656 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) 1657 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) 1658 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) 1659 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) 1660 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) 1661 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) 1662 #define EMC_DMCR_RMODE (1 << 25) 1663 #define EMC_DMCR_RFSH (1 << 24) 1664 #define EMC_DMCR_MRSET (1 << 23) 1665 #define EMC_DMCR_RA_BIT 20 1666 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) 1667 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) 1668 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) 1669 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) 1670 #define EMC_DMCR_BA_BIT 19 1671 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) 1672 #define EMC_DMCR_PDM (1 << 18) 1673 #define EMC_DMCR_EPIN (1 << 17) 1674 #define EMC_DMCR_TRAS_BIT 13 1675 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) 1676 #define EMC_DMCR_RCD_BIT 11 1677 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) 1678 #define EMC_DMCR_TPC_BIT 8 1679 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) 1680 #define EMC_DMCR_TRWL_BIT 5 1681 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) 1682 #define EMC_DMCR_TRC_BIT 2 1683 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) 1684 #define EMC_DMCR_TCL_BIT 0 1685 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) 1686 1687 /* Refresh Time Control/Status Register */ 1688 #define EMC_RTCSR_CMF (1 << 7) 1689 #define EMC_RTCSR_CKS_BIT 0 1690 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) 1691 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) 1692 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) 1693 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) 1694 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) 1695 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) 1696 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) 1697 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) 1698 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) 1699 1700 /* SDRAM Bank Address Configuration Register */ 1701 #define EMC_DMAR_BASE_BIT 8 1702 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) 1703 #define EMC_DMAR_MASK_BIT 0 1704 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) 1705 1706 /* Mode Register of SDRAM bank 0 */ 1707 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ 1708 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ 1709 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) 1710 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) 1711 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ 1712 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) 1713 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) 1714 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) 1715 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) 1716 #define EMC_SDMR_BT_BIT 3 /* Burst Type */ 1717 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) 1718 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ 1719 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ 1720 #define EMC_SDMR_BL_BIT 0 /* Burst Length */ 1721 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) 1722 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) 1723 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) 1724 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) 1725 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) 1726 1727 #define EMC_SDMR_CAS2_16BIT \ 1728 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1729 #define EMC_SDMR_CAS2_32BIT \ 1730 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1731 #define EMC_SDMR_CAS3_16BIT \ 1732 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1733 #define EMC_SDMR_CAS3_32BIT \ 1734 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1735 1736 /************************************************************************* 1737 * CIM 1738 *************************************************************************/ 1739 #define CIM_CFG (CIM_BASE + 0x0000) 1740 #define CIM_CTRL (CIM_BASE + 0x0004) 1741 #define CIM_STATE (CIM_BASE + 0x0008) 1742 #define CIM_IID (CIM_BASE + 0x000C) 1743 #define CIM_RXFIFO (CIM_BASE + 0x0010) 1744 #define CIM_DA (CIM_BASE + 0x0020) 1745 #define CIM_FA (CIM_BASE + 0x0024) 1746 #define CIM_FID (CIM_BASE + 0x0028) 1747 #define CIM_CMD (CIM_BASE + 0x002C) 1748 1749 #define REG_CIM_CFG REG32(CIM_CFG) 1750 #define REG_CIM_CTRL REG32(CIM_CTRL) 1751 #define REG_CIM_STATE REG32(CIM_STATE) 1752 #define REG_CIM_IID REG32(CIM_IID) 1753 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) 1754 #define REG_CIM_DA REG32(CIM_DA) 1755 #define REG_CIM_FA REG32(CIM_FA) 1756 #define REG_CIM_FID REG32(CIM_FID) 1757 #define REG_CIM_CMD REG32(CIM_CMD) 1758 1759 /* CIM Configuration Register (CIM_CFG) */ 1760 1761 #define CIM_CFG_INV_DAT (1 << 15) 1762 #define CIM_CFG_VSP (1 << 14) 1763 #define CIM_CFG_HSP (1 << 13) 1764 #define CIM_CFG_PCP (1 << 12) 1765 #define CIM_CFG_DUMMY_ZERO (1 << 9) 1766 #define CIM_CFG_EXT_VSYNC (1 << 8) 1767 #define CIM_CFG_PACK_BIT 4 1768 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) 1769 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) 1770 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) 1771 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) 1772 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) 1773 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) 1774 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) 1775 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) 1776 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) 1777 #define CIM_CFG_DSM_BIT 0 1778 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) 1779 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ 1780 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ 1781 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ 1782 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ 1783 1784 /* CIM Control Register (CIM_CTRL) */ 1785 1786 #define CIM_CTRL_MCLKDIV_BIT 24 1787 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) 1788 #define CIM_CTRL_FRC_BIT 16 1789 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) 1790 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ 1791 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ 1792 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ 1793 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ 1794 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ 1795 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ 1796 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ 1797 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ 1798 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ 1799 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ 1800 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ 1801 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ 1802 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ 1803 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ 1804 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ 1805 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ 1806 #define CIM_CTRL_VDDM (1 << 13) 1807 #define CIM_CTRL_DMA_SOFM (1 << 12) 1808 #define CIM_CTRL_DMA_EOFM (1 << 11) 1809 #define CIM_CTRL_DMA_STOPM (1 << 10) 1810 #define CIM_CTRL_RXF_TRIGM (1 << 9) 1811 #define CIM_CTRL_RXF_OFM (1 << 8) 1812 #define CIM_CTRL_RXF_TRIG_BIT 4 1813 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) 1814 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ 1815 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ 1816 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ 1817 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ 1818 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ 1819 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ 1820 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ 1821 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ 1822 #define CIM_CTRL_DMA_EN (1 << 2) 1823 #define CIM_CTRL_RXF_RST (1 << 1) 1824 #define CIM_CTRL_ENA (1 << 0) 1825 1826 /* CIM State Register (CIM_STATE) */ 1827 1828 #define CIM_STATE_DMA_SOF (1 << 6) 1829 #define CIM_STATE_DMA_EOF (1 << 5) 1830 #define CIM_STATE_DMA_STOP (1 << 4) 1831 #define CIM_STATE_RXF_OF (1 << 3) 1832 #define CIM_STATE_RXF_TRIG (1 << 2) 1833 #define CIM_STATE_RXF_EMPTY (1 << 1) 1834 #define CIM_STATE_VDD (1 << 0) 1835 1836 /* CIM DMA Command Register (CIM_CMD) */ 1837 1838 #define CIM_CMD_SOFINT (1 << 31) 1839 #define CIM_CMD_EOFINT (1 << 30) 1840 #define CIM_CMD_STOP (1 << 28) 1841 #define CIM_CMD_LEN_BIT 0 1842 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) 1843 1844 1845 /************************************************************************* 1846 * SADC (Smart A/D Controller) 1847 *************************************************************************/ 1848 1849 #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ 1850 #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ 1851 #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ 1852 #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ 1853 #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ 1854 #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ 1855 #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ 1856 #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ 1857 #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ 1858 1859 #define REG_SADC_ENA REG8(SADC_ENA) 1860 #define REG_SADC_CFG REG32(SADC_CFG) 1861 #define REG_SADC_CTRL REG8(SADC_CTRL) 1862 #define REG_SADC_STATE REG8(SADC_STATE) 1863 #define REG_SADC_SAMETIME REG16(SADC_SAMETIME) 1864 #define REG_SADC_WAITTIME REG16(SADC_WAITTIME) 1865 #define REG_SADC_TSDAT REG32(SADC_TSDAT) 1866 #define REG_SADC_BATDAT REG16(SADC_BATDAT) 1867 #define REG_SADC_SADDAT REG16(SADC_SADDAT) 1868 1869 /* ADC Enable Register */ 1870 #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ 1871 #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ 1872 #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ 1873 #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ 1874 1875 /* ADC Configure Register */ 1876 #define SADC_CFG_CLKOUT_NUM_BIT 16 1877 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) 1878 #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ 1879 #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ 1880 #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) 1881 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) 1882 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) 1883 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) 1884 #define SADC_CFG_SNUM_BIT 10 /* Sample Number */ 1885 #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) 1886 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) 1887 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) 1888 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) 1889 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) 1890 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) 1891 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) 1892 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) 1893 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) 1894 #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ 1895 #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) 1896 #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ 1897 #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ 1898 #define SADC_CFG_CMD_BIT 0 /* ADC Command */ 1899 #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) 1900 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ 1901 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ 1902 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ 1903 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ 1904 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ 1905 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ 1906 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ 1907 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ 1908 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ 1909 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ 1910 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ 1911 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ 1912 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ 1913 1914 /* ADC Control Register */ 1915 #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ 1916 #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ 1917 #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ 1918 #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ 1919 #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ 1920 1921 /* ADC Status Register */ 1922 #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ 1923 #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ 1924 #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ 1925 #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ 1926 #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ 1927 #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ 1928 #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ 1929 #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ 1930 1931 /* ADC Touch Screen Data Register */ 1932 #define SADC_TSDAT_DATA0_BIT 0 1933 #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) 1934 #define SADC_TSDAT_TYPE0 (1 << 15) 1935 #define SADC_TSDAT_DATA1_BIT 16 1936 #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) 1937 #define SADC_TSDAT_TYPE1 (1 << 31) 1938 1939 1940 /************************************************************************* 1941 * SLCD (Smart LCD Controller) 1942 *************************************************************************/ 1943 1944 #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ 1945 #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ 1946 #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ 1947 #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ 1948 #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ 1949 1950 #define REG_SLCD_CFG REG32(SLCD_CFG) 1951 #define REG_SLCD_CTRL REG8(SLCD_CTRL) 1952 #define REG_SLCD_STATE REG8(SLCD_STATE) 1953 #define REG_SLCD_DATA REG32(SLCD_DATA) 1954 #define REG_SLCD_FIFO REG32(SLCD_FIFO) 1955 1956 /* SLCD Configure Register */ 1957 #define SLCD_CFG_BURST_BIT 14 1958 #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) 1959 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) 1960 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) 1961 #define SLCD_CFG_DWIDTH_BIT 10 1962 #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) 1963 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) 1964 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) 1965 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) 1966 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) 1967 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) 1968 #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) 1969 #define SLCD_CFG_CWIDTH_16BIT (0 << 8) 1970 #define SLCD_CFG_CWIDTH_8BIT (1 << 8) 1971 #define SLCD_CFG_CWIDTH_18BIT (2 << 8) 1972 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) 1973 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) 1974 #define SLCD_CFG_RS_CMD_LOW (0 << 3) 1975 #define SLCD_CFG_RS_CMD_HIGH (1 << 3) 1976 #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) 1977 #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) 1978 #define SLCD_CFG_TYPE_PARALLEL (0 << 0) 1979 #define SLCD_CFG_TYPE_SERIAL (1 << 0) 1980 1981 /* SLCD Control Register */ 1982 #define SLCD_CTRL_DMA_EN (1 << 0) 1983 1984 /* SLCD Status Register */ 1985 #define SLCD_STATE_BUSY (1 << 0) 1986 1987 /* SLCD Data Register */ 1988 #define SLCD_DATA_RS_DATA (0 << 31) 1989 #define SLCD_DATA_RS_COMMAND (1 << 31) 1990 1991 /* SLCD FIFO Register */ 1992 #define SLCD_FIFO_RS_DATA (0 << 31) 1993 #define SLCD_FIFO_RS_COMMAND (1 << 31) 1994 1995 1996 /************************************************************************* 1997 * LCD (LCD Controller) 1998 *************************************************************************/ 1999 2000 /* Register definitions with absolute positioning have been removed. */ 2001 2002 /* LCD Configure Register */ 2003 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ 2004 #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) 2005 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) 2006 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) 2007 #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ 2008 #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ 2009 #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ 2010 #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ 2011 #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ 2012 #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ 2013 #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ 2014 #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ 2015 #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ 2016 #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ 2017 #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ 2018 #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ 2019 #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ 2020 #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ 2021 #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ 2022 #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ 2023 #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ 2024 #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) 2025 #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ 2026 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ 2027 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ 2028 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ 2029 #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ 2030 #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) 2031 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ 2032 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) 2033 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) 2034 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) 2035 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) 2036 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) 2037 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) 2038 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) 2039 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) 2040 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) 2041 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) 2042 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) 2043 /* JZ47XX defines */ 2044 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) 2045 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) 2046 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) 2047 2048 2049 2050 /* Vertical Synchronize Register */ 2051 #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ 2052 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2053 #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ 2054 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2055 2056 /* Horizontal Synchronize Register */ 2057 #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ 2058 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) 2059 #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ 2060 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) 2061 2062 /* Virtual Area Setting Register */ 2063 #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ 2064 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) 2065 #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ 2066 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) 2067 2068 /* Display Area Horizontal Start/End Point Register */ 2069 #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ 2070 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) 2071 #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ 2072 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) 2073 2074 /* Display Area Vertical Start/End Point Register */ 2075 #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ 2076 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) 2077 #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ 2078 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) 2079 2080 /* PS Signal Setting */ 2081 #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ 2082 #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) 2083 #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ 2084 #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) 2085 2086 /* CLS Signal Setting */ 2087 #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ 2088 #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) 2089 #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ 2090 #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) 2091 2092 /* SPL Signal Setting */ 2093 #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ 2094 #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) 2095 #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ 2096 #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) 2097 2098 /* REV Signal Setting */ 2099 #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ 2100 #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) 2101 2102 /* LCD Control Register */ 2103 #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ 2104 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) 2105 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ 2106 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ 2107 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ 2108 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ 2109 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ 2110 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ 2111 #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ 2112 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) 2113 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ 2114 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ 2115 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ 2116 #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ 2117 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) 2118 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ 2119 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ 2120 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ 2121 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ 2122 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ 2123 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ 2124 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ 2125 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ 2126 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ 2127 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ 2128 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ 2129 #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ 2130 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) 2131 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ 2132 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ 2133 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ 2134 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ 2135 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ 2136 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ 2137 2138 /* LCD Status Register */ 2139 #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ 2140 #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ 2141 #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ 2142 #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ 2143 #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ 2144 #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ 2145 #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ 2146 2147 /* DMA Command Register */ 2148 #define LCD_CMD_SOFINT (1 << 31) 2149 #define LCD_CMD_EOFINT (1 << 30) 2150 #define LCD_CMD_PAL (1 << 28) 2151 #define LCD_CMD_LEN_BIT 0 2152 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) 2153 2154 2155 /************************************************************************* 2156 * USB Device 2157 *************************************************************************/ 2158 #define USB_BASE UDC_BASE 2159 2160 #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ 2161 #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ 2162 #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ 2163 #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ 2164 #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ 2165 #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ 2166 #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ 2167 #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ 2168 #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ 2169 #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ 2170 #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ 2171 2172 #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ 2173 #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ 2174 #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ 2175 #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ 2176 #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ 2177 #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ 2178 #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ 2179 #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ 2180 2181 #define USB_FIFO_EP0 (USB_BASE + 0x20) 2182 #define USB_FIFO_EP1 (USB_BASE + 0x24) 2183 #define USB_FIFO_EP2 (USB_BASE + 0x28) 2184 2185 #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ 2186 #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ 2187 2188 #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ 2189 #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ 2190 #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ 2191 #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ 2192 #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ 2193 #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ 2194 #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ 2195 2196 2197 /* Power register bit masks */ 2198 #define USB_POWER_SUSPENDM 0x01 2199 #define USB_POWER_RESUME 0x04 2200 #define USB_POWER_HSMODE 0x10 2201 #define USB_POWER_HSENAB 0x20 2202 #define USB_POWER_SOFTCONN 0x40 2203 2204 /* Interrupt register bit masks */ 2205 #define USB_INTR_SUSPEND 0x01 2206 #define USB_INTR_RESUME 0x02 2207 #define USB_INTR_RESET 0x04 2208 2209 #define USB_INTR_EP0 0x0001 2210 #define USB_INTR_INEP1 0x0002 2211 #define USB_INTR_INEP2 0x0004 2212 #define USB_INTR_OUTEP1 0x0002 2213 2214 /* CSR0 bit masks */ 2215 #define USB_CSR0_OUTPKTRDY 0x01 2216 #define USB_CSR0_INPKTRDY 0x02 2217 #define USB_CSR0_SENTSTALL 0x04 2218 #define USB_CSR0_DATAEND 0x08 2219 #define USB_CSR0_SETUPEND 0x10 2220 #define USB_CSR0_SENDSTALL 0x20 2221 #define USB_CSR0_SVDOUTPKTRDY 0x40 2222 #define USB_CSR0_SVDSETUPEND 0x80 2223 2224 /* Endpoint CSR register bits */ 2225 #define USB_INCSRH_AUTOSET 0x80 2226 #define USB_INCSRH_ISO 0x40 2227 #define USB_INCSRH_MODE 0x20 2228 #define USB_INCSRH_DMAREQENAB 0x10 2229 #define USB_INCSRH_DMAREQMODE 0x04 2230 #define USB_INCSR_CDT 0x40 2231 #define USB_INCSR_SENTSTALL 0x20 2232 #define USB_INCSR_SENDSTALL 0x10 2233 #define USB_INCSR_FF 0x08 2234 #define USB_INCSR_UNDERRUN 0x04 2235 #define USB_INCSR_FFNOTEMPT 0x02 2236 #define USB_INCSR_INPKTRDY 0x01 2237 #define USB_OUTCSRH_AUTOCLR 0x80 2238 #define USB_OUTCSRH_ISO 0x40 2239 #define USB_OUTCSRH_DMAREQENAB 0x20 2240 #define USB_OUTCSRH_DNYT 0x10 2241 #define USB_OUTCSRH_DMAREQMODE 0x08 2242 #define USB_OUTCSR_CDT 0x80 2243 #define USB_OUTCSR_SENTSTALL 0x40 2244 #define USB_OUTCSR_SENDSTALL 0x20 2245 #define USB_OUTCSR_FF 0x10 2246 #define USB_OUTCSR_DATAERR 0x08 2247 #define USB_OUTCSR_OVERRUN 0x04 2248 #define USB_OUTCSR_FFFULL 0x02 2249 #define USB_OUTCSR_OUTPKTRDY 0x01 2250 2251 /* Testmode register bits */ 2252 #define USB_TEST_SE0NAK 0x01 2253 #define USB_TEST_J 0x02 2254 #define USB_TEST_K 0x04 2255 #define USB_TEST_PACKET 0x08 2256 2257 /* DMA control bits */ 2258 #define USB_CNTL_ENA 0x01 2259 #define USB_CNTL_DIR_IN 0x02 2260 #define USB_CNTL_MODE_1 0x04 2261 #define USB_CNTL_INTR_EN 0x08 2262 #define USB_CNTL_EP(n) ((n) << 4) 2263 #define USB_CNTL_BURST_0 (0 << 9) 2264 #define USB_CNTL_BURST_4 (1 << 9) 2265 #define USB_CNTL_BURST_8 (2 << 9) 2266 #define USB_CNTL_BURST_16 (3 << 9) 2267 2268 2269 2270 /* Module Operation Definitions */ 2271 2272 #ifndef __ASSEMBLY__ 2273 2274 /* Register operations using absolute positioning have been removed. */ 2275 2276 /*************************************************************************** 2277 * CPM 2278 ***************************************************************************/ 2279 2280 /* Register operations using absolute positioning have been removed. */ 2281 2282 /* 2283 * TCU 2284 */ 2285 /* where 'n' is the TCU channel */ 2286 #define __tcu_select_extalclk(n) \ 2287 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) 2288 #define __tcu_select_rtcclk(n) \ 2289 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) 2290 #define __tcu_select_pclk(n) \ 2291 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) 2292 2293 #define __tcu_select_clk_div1(n) \ 2294 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) 2295 #define __tcu_select_clk_div4(n) \ 2296 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) 2297 #define __tcu_select_clk_div16(n) \ 2298 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) 2299 #define __tcu_select_clk_div64(n) \ 2300 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) 2301 #define __tcu_select_clk_div256(n) \ 2302 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) 2303 #define __tcu_select_clk_div1024(n) \ 2304 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) 2305 2306 #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) 2307 #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) 2308 2309 #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) 2310 #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) 2311 2312 #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) 2313 #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) 2314 2315 #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) 2316 #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) 2317 2318 #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) 2319 #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) 2320 #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) 2321 #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) 2322 #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) 2323 #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) 2324 #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) 2325 #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) 2326 #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) 2327 #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) 2328 2329 #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) 2330 #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) 2331 2332 #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) 2333 #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) 2334 2335 #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) 2336 #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) 2337 2338 #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) 2339 #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) 2340 #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) 2341 #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) 2342 2343 2344 /*************************************************************************** 2345 * WDT 2346 ***************************************************************************/ 2347 #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) 2348 #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) 2349 #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) 2350 #define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) 2351 2352 #define __wdt_select_extalclk() \ 2353 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) 2354 #define __wdt_select_rtcclk() \ 2355 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) 2356 #define __wdt_select_pclk() \ 2357 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) 2358 2359 #define __wdt_select_clk_div1() \ 2360 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) 2361 #define __wdt_select_clk_div4() \ 2362 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) 2363 #define __wdt_select_clk_div16() \ 2364 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) 2365 #define __wdt_select_clk_div64() \ 2366 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) 2367 #define __wdt_select_clk_div256() \ 2368 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) 2369 #define __wdt_select_clk_div1024() \ 2370 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) 2371 2372 2373 /*************************************************************************** 2374 * UART 2375 ***************************************************************************/ 2376 2377 #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) 2378 #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) 2379 2380 #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) 2381 #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) 2382 2383 #define __uart_enable_receive_irq() \ 2384 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) 2385 #define __uart_disable_receive_irq() \ 2386 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) 2387 2388 #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) 2389 #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) 2390 2391 #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) 2392 2393 #define __uart_set_baud(devclk, baud) \ 2394 do { \ 2395 REG8(UART0_LCR) |= UARTLCR_DLAB; \ 2396 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ 2397 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ 2398 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ 2399 } while (0) 2400 2401 #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) 2402 #define __uart_clear_errors() \ 2403 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) 2404 2405 #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) 2406 #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) 2407 #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) 2408 #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 2409 #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 2410 #define __uart_receive_char() REG8(UART0_RDR) 2411 #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) 2412 #define __uart_enable_irda() \ 2413 /* Tx high pulse as 0, Rx low pulse as 0 */ \ 2414 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) 2415 2416 2417 /*************************************************************************** 2418 * DMAC 2419 ***************************************************************************/ 2420 2421 /* n is the DMA channel (0 - 5) */ 2422 2423 #define __dmac_enable_module() \ 2424 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) 2425 #define __dmac_disable_module() \ 2426 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) 2427 2428 /* p=0,1,2,3 */ 2429 #define __dmac_set_priority(p) \ 2430 do { \ 2431 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ 2432 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ 2433 } while (0) 2434 2435 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) 2436 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) 2437 2438 #define __dmac_enable_descriptor(n) \ 2439 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) 2440 #define __dmac_disable_descriptor(n) \ 2441 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) 2442 2443 #define __dmac_enable_channel(n) \ 2444 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) 2445 #define __dmac_disable_channel(n) \ 2446 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) 2447 #define __dmac_channel_enabled(n) \ 2448 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) 2449 2450 #define __dmac_channel_enable_irq(n) \ 2451 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) 2452 #define __dmac_channel_disable_irq(n) \ 2453 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) 2454 2455 #define __dmac_channel_transmit_halt_detected(n) \ 2456 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) 2457 #define __dmac_channel_transmit_end_detected(n) \ 2458 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) 2459 #define __dmac_channel_address_error_detected(n) \ 2460 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) 2461 #define __dmac_channel_count_terminated_detected(n) \ 2462 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) 2463 #define __dmac_channel_descriptor_invalid_detected(n) \ 2464 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) 2465 2466 #define __dmac_channel_clear_transmit_halt(n) \ 2467 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) 2468 #define __dmac_channel_clear_transmit_end(n) \ 2469 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) 2470 #define __dmac_channel_clear_address_error(n) \ 2471 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) 2472 #define __dmac_channel_clear_count_terminated(n) \ 2473 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) 2474 #define __dmac_channel_clear_descriptor_invalid(n) \ 2475 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) 2476 2477 #define __dmac_channel_set_single_mode(n) \ 2478 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) 2479 #define __dmac_channel_set_block_mode(n) \ 2480 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) 2481 2482 #define __dmac_channel_set_transfer_unit_32bit(n) \ 2483 do { \ 2484 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 2485 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ 2486 } while (0) 2487 2488 #define __dmac_channel_set_transfer_unit_16bit(n) \ 2489 do { \ 2490 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 2491 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ 2492 } while (0) 2493 2494 #define __dmac_channel_set_transfer_unit_8bit(n) \ 2495 do { \ 2496 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 2497 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ 2498 } while (0) 2499 2500 #define __dmac_channel_set_transfer_unit_16byte(n) \ 2501 do { \ 2502 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 2503 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ 2504 } while (0) 2505 2506 #define __dmac_channel_set_transfer_unit_32byte(n) \ 2507 do { \ 2508 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 2509 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ 2510 } while (0) 2511 2512 /* w=8,16,32 */ 2513 #define __dmac_channel_set_dest_port_width(n,w) \ 2514 do { \ 2515 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ 2516 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ 2517 } while (0) 2518 2519 /* w=8,16,32 */ 2520 #define __dmac_channel_set_src_port_width(n,w) \ 2521 do { \ 2522 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ 2523 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ 2524 } while (0) 2525 2526 /* v=0-15 */ 2527 #define __dmac_channel_set_rdil(n,v) \ 2528 do { \ 2529 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ 2530 REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ 2531 } while (0) 2532 2533 #define __dmac_channel_dest_addr_fixed(n) \ 2534 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) 2535 #define __dmac_channel_dest_addr_increment(n) \ 2536 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) 2537 2538 #define __dmac_channel_src_addr_fixed(n) \ 2539 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) 2540 #define __dmac_channel_src_addr_increment(n) \ 2541 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) 2542 2543 #define __dmac_channel_set_doorbell(n) \ 2544 ( REG_DMAC_DMADBSR = (1 << (n)) ) 2545 2546 #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) 2547 #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) 2548 2549 static __inline__ int __dmac_get_irq(void) 2550 { 2551 int i; 2552 for (i = 0; i < MAX_DMA_NUM; i++) 2553 if (__dmac_channel_irq_detected(i)) 2554 return i; 2555 return -1; 2556 } 2557 2558 2559 /*************************************************************************** 2560 * AIC (AC'97 & I2S Controller) 2561 ***************************************************************************/ 2562 2563 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 2564 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 2565 2566 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 2567 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 2568 2569 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 2570 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 2571 #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) 2572 2573 #define __aic_reset() \ 2574 do { \ 2575 REG_AIC_FR |= AIC_FR_RST; \ 2576 } while(0) 2577 2578 2579 #define __aic_set_transmit_trigger(n) \ 2580 do { \ 2581 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 2582 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ 2583 } while(0) 2584 2585 #define __aic_set_receive_trigger(n) \ 2586 do { \ 2587 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 2588 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ 2589 } while(0) 2590 2591 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 2592 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 2593 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 2594 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 2595 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 2596 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 2597 2598 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) 2599 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) 2600 2601 #define __aic_enable_transmit_intr() \ 2602 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 2603 #define __aic_disable_transmit_intr() \ 2604 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 2605 #define __aic_enable_receive_intr() \ 2606 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 2607 #define __aic_disable_receive_intr() \ 2608 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 2609 2610 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 2611 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 2612 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 2613 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 2614 2615 #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) 2616 #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) 2617 #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) 2618 #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) 2619 #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) 2620 #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) 2621 2622 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 2623 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 2624 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 2625 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 2626 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 2627 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 2628 2629 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 2630 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 2631 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 2632 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 2633 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 2634 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 2635 2636 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 2637 #define __ac97_set_xs_mono() \ 2638 do { \ 2639 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 2640 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 2641 } while(0) 2642 #define __ac97_set_xs_stereo() \ 2643 do { \ 2644 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 2645 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 2646 } while(0) 2647 2648 /* In fact, only stereo is support now. */ 2649 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 2650 #define __ac97_set_rs_mono() \ 2651 do { \ 2652 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 2653 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 2654 } while(0) 2655 #define __ac97_set_rs_stereo() \ 2656 do { \ 2657 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 2658 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 2659 } while(0) 2660 2661 #define __ac97_warm_reset_codec() \ 2662 do { \ 2663 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 2664 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 2665 udelay(2); \ 2666 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 2667 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 2668 } while (0) 2669 2670 #define __ac97_cold_reset_codec() \ 2671 do { \ 2672 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 2673 udelay(2); \ 2674 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 2675 } while (0) 2676 2677 /* n=8,16,18,20 */ 2678 #define __ac97_set_iass(n) \ 2679 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 2680 #define __ac97_set_oass(n) \ 2681 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 2682 2683 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 2684 #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 2685 2686 /* n=8,16,18,20,24 */ 2687 /*#define __i2s_set_sample_size(n) \ 2688 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ 2689 2690 #define __i2s_set_oss_sample_size(n) \ 2691 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) 2692 #define __i2s_set_iss_sample_size(n) \ 2693 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) 2694 2695 #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 2696 #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 2697 2698 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 2699 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 2700 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 2701 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 2702 2703 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 2704 2705 #define __aic_get_transmit_resident() \ 2706 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) 2707 #define __aic_get_receive_count() \ 2708 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) 2709 2710 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 2711 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 2712 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 2713 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 2714 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 2715 #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) 2716 #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) 2717 2718 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 2719 2720 #define CODEC_READ_CMD (1 << 19) 2721 #define CODEC_WRITE_CMD (0 << 19) 2722 #define CODEC_REG_INDEX_BIT 12 2723 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ 2724 #define CODEC_REG_DATA_BIT 4 2725 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ 2726 2727 #define __ac97_out_rcmd_addr(reg) \ 2728 do { \ 2729 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 2730 } while (0) 2731 2732 #define __ac97_out_wcmd_addr(reg) \ 2733 do { \ 2734 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 2735 } while (0) 2736 2737 #define __ac97_out_data(value) \ 2738 do { \ 2739 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ 2740 } while (0) 2741 2742 #define __ac97_in_data() \ 2743 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) 2744 2745 #define __ac97_in_status_addr() \ 2746 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) 2747 2748 #define __i2s_set_sample_rate(i2sclk, sync) \ 2749 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 2750 2751 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 2752 #define __aic_read_rfifo() ( REG_AIC_DR ) 2753 2754 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) 2755 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) 2756 2757 /* Define next ops for AC97 compatible */ 2758 2759 #define AC97_ACSR AIC_ACSR 2760 2761 #define __ac97_enable() __aic_enable(); __aic_select_ac97() 2762 #define __ac97_disable() __aic_disable() 2763 #define __ac97_reset() __aic_reset() 2764 2765 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 2766 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 2767 2768 #define __ac97_enable_record() __aic_enable_record() 2769 #define __ac97_disable_record() __aic_disable_record() 2770 #define __ac97_enable_replay() __aic_enable_replay() 2771 #define __ac97_disable_replay() __aic_disable_replay() 2772 #define __ac97_enable_loopback() __aic_enable_loopback() 2773 #define __ac97_disable_loopback() __aic_disable_loopback() 2774 2775 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 2776 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 2777 #define __ac97_enable_receive_dma() __aic_enable_receive_dma() 2778 #define __ac97_disable_receive_dma() __aic_disable_receive_dma() 2779 2780 #define __ac97_transmit_request() __aic_transmit_request() 2781 #define __ac97_receive_request() __aic_receive_request() 2782 #define __ac97_transmit_underrun() __aic_transmit_underrun() 2783 #define __ac97_receive_overrun() __aic_receive_overrun() 2784 2785 #define __ac97_clear_errors() __aic_clear_errors() 2786 2787 #define __ac97_get_transmit_resident() __aic_get_transmit_resident() 2788 #define __ac97_get_receive_count() __aic_get_receive_count() 2789 2790 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 2791 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 2792 #define __ac97_enable_receive_intr() __aic_enable_receive_intr() 2793 #define __ac97_disable_receive_intr() __aic_disable_receive_intr() 2794 2795 #define __ac97_write_tfifo(v) __aic_write_tfifo(v) 2796 #define __ac97_read_rfifo() __aic_read_rfifo() 2797 2798 /* Define next ops for I2S compatible */ 2799 2800 #define I2S_ACSR AIC_I2SSR 2801 2802 #define __i2s_enable() __aic_enable(); __aic_select_i2s() 2803 #define __i2s_disable() __aic_disable() 2804 #define __i2s_reset() __aic_reset() 2805 2806 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 2807 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 2808 2809 #define __i2s_enable_record() __aic_enable_record() 2810 #define __i2s_disable_record() __aic_disable_record() 2811 #define __i2s_enable_replay() __aic_enable_replay() 2812 #define __i2s_disable_replay() __aic_disable_replay() 2813 #define __i2s_enable_loopback() __aic_enable_loopback() 2814 #define __i2s_disable_loopback() __aic_disable_loopback() 2815 2816 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 2817 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 2818 #define __i2s_enable_receive_dma() __aic_enable_receive_dma() 2819 #define __i2s_disable_receive_dma() __aic_disable_receive_dma() 2820 2821 #define __i2s_transmit_request() __aic_transmit_request() 2822 #define __i2s_receive_request() __aic_receive_request() 2823 #define __i2s_transmit_underrun() __aic_transmit_underrun() 2824 #define __i2s_receive_overrun() __aic_receive_overrun() 2825 2826 #define __i2s_clear_errors() __aic_clear_errors() 2827 2828 #define __i2s_get_transmit_resident() __aic_get_transmit_resident() 2829 #define __i2s_get_receive_count() __aic_get_receive_count() 2830 2831 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 2832 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 2833 #define __i2s_enable_receive_intr() __aic_enable_receive_intr() 2834 #define __i2s_disable_receive_intr() __aic_disable_receive_intr() 2835 2836 #define __i2s_write_tfifo(v) __aic_write_tfifo(v) 2837 #define __i2s_read_rfifo() __aic_read_rfifo() 2838 2839 #define __i2s_reset_codec() \ 2840 do { \ 2841 } while (0) 2842 2843 2844 /*************************************************************************** 2845 * ICDC 2846 ***************************************************************************/ 2847 #define __i2s_internal_codec() __aic_internal_codec() 2848 #define __i2s_external_codec() __aic_external_codec() 2849 2850 /*************************************************************************** 2851 * INTC 2852 ***************************************************************************/ 2853 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) 2854 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) 2855 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) 2856 2857 2858 /*************************************************************************** 2859 * I2C 2860 ***************************************************************************/ 2861 2862 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) 2863 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) 2864 2865 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) 2866 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) 2867 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) 2868 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) 2869 2870 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) 2871 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) 2872 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) 2873 2874 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) 2875 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) 2876 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) 2877 2878 #define __i2c_set_clk(dev_clk, i2c_clk) \ 2879 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) 2880 2881 #define __i2c_read() ( REG_I2C_DR ) 2882 #define __i2c_write(val) ( REG_I2C_DR = (val) ) 2883 2884 2885 /*************************************************************************** 2886 * MSC 2887 ***************************************************************************/ 2888 2889 #define __msc_start_op() \ 2890 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) 2891 2892 #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) 2893 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) 2894 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) 2895 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) 2896 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) 2897 #define __msc_get_nob() ( REG_MSC_NOB ) 2898 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) 2899 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) 2900 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) 2901 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) 2902 2903 #define __msc_set_cmdat_bus_width1() \ 2904 do { \ 2905 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 2906 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ 2907 } while(0) 2908 2909 #define __msc_set_cmdat_bus_width4() \ 2910 do { \ 2911 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 2912 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ 2913 } while(0) 2914 2915 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) 2916 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) 2917 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) 2918 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) 2919 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) 2920 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) 2921 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) 2922 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) 2923 2924 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ 2925 #define __msc_set_cmdat_res_format(r) \ 2926 do { \ 2927 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ 2928 REG_MSC_CMDAT |= (r); \ 2929 } while(0) 2930 2931 #define __msc_clear_cmdat() \ 2932 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ 2933 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ 2934 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) 2935 2936 #define __msc_get_imask() ( REG_MSC_IMASK ) 2937 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) 2938 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) 2939 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) 2940 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) 2941 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) 2942 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) 2943 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) 2944 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) 2945 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) 2946 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) 2947 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) 2948 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) 2949 2950 /* n=0,1,2,3,4,5,6,7 */ 2951 #define __msc_set_clkrt(n) \ 2952 do { \ 2953 REG_MSC_CLKRT = n; \ 2954 } while(0) 2955 2956 #define __msc_get_ireg() ( REG_MSC_IREG ) 2957 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) 2958 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) 2959 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) 2960 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) 2961 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) 2962 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) 2963 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) 2964 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) 2965 2966 #define __msc_get_stat() ( REG_MSC_STAT ) 2967 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) 2968 #define __msc_stat_crc_err() \ 2969 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) 2970 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) 2971 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) 2972 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) 2973 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) 2974 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) 2975 2976 #define __msc_rd_resfifo() ( REG_MSC_RES ) 2977 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 2978 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 2979 2980 #define __msc_reset() \ 2981 do { \ 2982 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 2983 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 2984 } while (0) 2985 2986 #define __msc_start_clk() \ 2987 do { \ 2988 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ 2989 } while (0) 2990 2991 #define __msc_stop_clk() \ 2992 do { \ 2993 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ 2994 } while (0) 2995 2996 #define MMC_CLK 19169200 2997 #define SD_CLK 24576000 2998 2999 /* msc_clk should little than pclk and little than clk retrieve from card */ 3000 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ 3001 do { \ 3002 unsigned int rate, pclk, i; \ 3003 pclk = dev_clk; \ 3004 rate = type?SD_CLK:MMC_CLK; \ 3005 if (msc_clk && msc_clk < pclk) \ 3006 pclk = msc_clk; \ 3007 i = 0; \ 3008 while (pclk < rate) \ 3009 { \ 3010 i ++; \ 3011 rate >>= 1; \ 3012 } \ 3013 lv = i; \ 3014 } while(0) 3015 3016 /* divide rate to little than or equal to 400kHz */ 3017 #define __msc_calc_slow_clk_divisor(type, lv) \ 3018 do { \ 3019 unsigned int rate, i; \ 3020 rate = (type?SD_CLK:MMC_CLK)/1000/400; \ 3021 i = 0; \ 3022 while (rate > 0) \ 3023 { \ 3024 rate >>= 1; \ 3025 i ++; \ 3026 } \ 3027 lv = i; \ 3028 } while(0) 3029 3030 3031 /*************************************************************************** 3032 * SSI 3033 ***************************************************************************/ 3034 3035 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) 3036 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) 3037 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) 3038 3039 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) 3040 3041 #define __ssi_select_ce2() \ 3042 do { \ 3043 REG_SSI_CR0 |= SSI_CR0_FSEL; \ 3044 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ 3045 } while (0) 3046 3047 #define __ssi_select_gpc() \ 3048 do { \ 3049 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ 3050 REG_SSI_CR1 |= SSI_CR1_MULTS; \ 3051 } while (0) 3052 3053 #define __ssi_enable_tx_intr() \ 3054 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) 3055 3056 #define __ssi_disable_tx_intr() \ 3057 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) 3058 3059 #define __ssi_enable_rx_intr() \ 3060 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) 3061 3062 #define __ssi_disable_rx_intr() \ 3063 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) 3064 3065 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) 3066 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) 3067 3068 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) 3069 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) 3070 3071 #define __ssi_finish_receive() \ 3072 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) 3073 3074 #define __ssi_disable_recvfinish() \ 3075 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) 3076 3077 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) 3078 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) 3079 3080 #define __ssi_flush_fifo() \ 3081 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) 3082 3083 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) 3084 3085 #define __ssi_spi_format() \ 3086 do { \ 3087 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 3088 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ 3089 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 3090 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ 3091 } while (0) 3092 3093 /* TI's SSP format, must clear SSI_CR1.UNFIN */ 3094 #define __ssi_ssp_format() \ 3095 do { \ 3096 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ 3097 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ 3098 } while (0) 3099 3100 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ 3101 #define __ssi_microwire_format() \ 3102 do { \ 3103 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 3104 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ 3105 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 3106 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ 3107 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ 3108 } while (0) 3109 3110 /* CE# level (FRMHL), CE# in interval time (ITFRM), 3111 clock phase and polarity (PHA POL), 3112 interval time (SSIITR), interval characters/frame (SSIICR) */ 3113 3114 /* frmhl,endian,mcom,flen,pha,pol MASK */ 3115 #define SSICR1_MISC_MASK \ 3116 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ 3117 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ 3118 3119 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ 3120 do { \ 3121 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ 3122 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ 3123 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ 3124 ((pha) << 1) | (pol); \ 3125 } while(0) 3126 3127 /* Transfer with MSB or LSB first */ 3128 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) 3129 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) 3130 3131 #define __ssi_set_frame_length(n) \ 3132 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) 3133 3134 /* n = 1 - 16 */ 3135 #define __ssi_set_microwire_command_length(n) \ 3136 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) 3137 3138 /* Set the clock phase for SPI */ 3139 #define __ssi_set_spi_clock_phase(n) \ 3140 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) 3141 3142 /* Set the clock polarity for SPI */ 3143 #define __ssi_set_spi_clock_polarity(n) \ 3144 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) 3145 3146 /* n = ix8 */ 3147 #define __ssi_set_tx_trigger(n) \ 3148 do { \ 3149 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ 3150 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ 3151 } while (0) 3152 3153 /* n = ix8 */ 3154 #define __ssi_set_rx_trigger(n) \ 3155 do { \ 3156 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ 3157 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ 3158 } while (0) 3159 3160 #define __ssi_get_txfifo_count() \ 3161 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) 3162 3163 #define __ssi_get_rxfifo_count() \ 3164 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) 3165 3166 #define __ssi_clear_errors() \ 3167 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) 3168 3169 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) 3170 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) 3171 3172 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) 3173 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) 3174 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) 3175 3176 #define __ssi_set_clk(dev_clk, ssi_clk) \ 3177 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) 3178 3179 #define __ssi_receive_data() REG_SSI_DR 3180 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) 3181 3182 3183 /*************************************************************************** 3184 * CIM 3185 ***************************************************************************/ 3186 3187 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) 3188 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) 3189 3190 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) 3191 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) 3192 3193 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) 3194 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) 3195 3196 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) 3197 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) 3198 3199 #define __cim_sample_data_at_pclk_falling_edge() \ 3200 ( REG_CIM_CFG |= CIM_CFG_PCP ) 3201 #define __cim_sample_data_at_pclk_rising_edge() \ 3202 ( REG_CIM_CFG &= ~CIM_CFG_PCP ) 3203 3204 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) 3205 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) 3206 3207 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) 3208 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) 3209 3210 /* n=0-7 */ 3211 #define __cim_set_data_packing_mode(n) \ 3212 do { \ 3213 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ 3214 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ 3215 } while (0) 3216 3217 #define __cim_enable_ccir656_progressive_mode() \ 3218 do { \ 3219 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3220 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ 3221 } while (0) 3222 3223 #define __cim_enable_ccir656_interlace_mode() \ 3224 do { \ 3225 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3226 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ 3227 } while (0) 3228 3229 #define __cim_enable_gated_clock_mode() \ 3230 do { \ 3231 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3232 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ 3233 } while (0) 3234 3235 #define __cim_enable_nongated_clock_mode() \ 3236 do { \ 3237 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3238 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ 3239 } while (0) 3240 3241 /* sclk:system bus clock 3242 * mclk: CIM master clock 3243 */ 3244 #define __cim_set_master_clk(sclk, mclk) \ 3245 do { \ 3246 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ 3247 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ 3248 } while (0) 3249 3250 #define __cim_enable_sof_intr() \ 3251 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) 3252 #define __cim_disable_sof_intr() \ 3253 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) 3254 3255 #define __cim_enable_eof_intr() \ 3256 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) 3257 #define __cim_disable_eof_intr() \ 3258 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) 3259 3260 #define __cim_enable_stop_intr() \ 3261 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) 3262 #define __cim_disable_stop_intr() \ 3263 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) 3264 3265 #define __cim_enable_trig_intr() \ 3266 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) 3267 #define __cim_disable_trig_intr() \ 3268 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) 3269 3270 #define __cim_enable_rxfifo_overflow_intr() \ 3271 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) 3272 #define __cim_disable_rxfifo_overflow_intr() \ 3273 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) 3274 3275 /* n=1-16 */ 3276 #define __cim_set_frame_rate(n) \ 3277 do { \ 3278 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ 3279 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ 3280 } while (0) 3281 3282 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) 3283 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) 3284 3285 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) 3286 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) 3287 3288 /* n=4,8,12,16,20,24,28,32 */ 3289 #define __cim_set_rxfifo_trigger(n) \ 3290 do { \ 3291 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ 3292 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ 3293 } while (0) 3294 3295 #define __cim_clear_state() ( REG_CIM_STATE = 0 ) 3296 3297 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) 3298 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) 3299 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) 3300 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) 3301 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) 3302 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) 3303 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) 3304 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) 3305 3306 #define __cim_get_iid() ( REG_CIM_IID ) 3307 #define __cim_get_image_data() ( REG_CIM_RXFIFO ) 3308 #define __cim_get_dam_cmd() ( REG_CIM_CMD ) 3309 3310 #define __cim_set_da(a) ( REG_CIM_DA = (a) ) 3311 3312 /*************************************************************************** 3313 * LCD 3314 ***************************************************************************/ 3315 3316 /* Register operations using absolute positioning have been removed. */ 3317 3318 /*************************************************************************** 3319 * RTC ops 3320 ***************************************************************************/ 3321 3322 #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) 3323 #define __rtc_enabled() \ 3324 do{ \ 3325 while(!__rtc_write_ready()); \ 3326 REG_RTC_RCR |= RTC_RCR_RTCE ; \ 3327 }while(0) \ 3328 3329 #define __rtc_disabled() \ 3330 do{ \ 3331 while(!__rtc_write_ready()); \ 3332 REG_RTC_RCR &= ~RTC_RCR_RTCE; \ 3333 }while(0) 3334 #define __rtc_enable_alarm() \ 3335 do{ \ 3336 while(!__rtc_write_ready()); \ 3337 REG_RTC_RCR |= RTC_RCR_AE; \ 3338 }while(0) 3339 3340 #define __rtc_disable_alarm() \ 3341 do{ \ 3342 while(!__rtc_write_ready()); \ 3343 REG_RTC_RCR &= ~RTC_RCR_AE; \ 3344 }while(0) 3345 3346 #define __rtc_enable_alarm_irq() \ 3347 do{ \ 3348 while(!__rtc_write_ready()); \ 3349 REG_RTC_RCR |= RTC_RCR_AIE; \ 3350 }while(0) 3351 3352 #define __rtc_disable_alarm_irq() \ 3353 do{ \ 3354 while(!__rtc_write_ready()); \ 3355 REG_RTC_RCR &= ~RTC_RCR_AIE; \ 3356 }while(0) 3357 #define __rtc_enable_Hz_irq() \ 3358 do{ \ 3359 while(!__rtc_write_ready()); \ 3360 REG_RTC_RCR |= RTC_RCR_HZIE; \ 3361 }while(0) 3362 3363 #define __rtc_disable_Hz_irq() \ 3364 do{ \ 3365 while(!__rtc_write_ready()); \ 3366 REG_RTC_RCR &= ~RTC_RCR_HZIE; \ 3367 }while(0) 3368 #define __rtc_get_1Hz_flag() \ 3369 do{ \ 3370 while(!__rtc_write_ready()); \ 3371 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ 3372 }while(0) 3373 #define __rtc_clear_1Hz_flag() \ 3374 do{ \ 3375 while(!__rtc_write_ready()); \ 3376 REG_RTC_RCR &= ~RTC_RCR_HZ; \ 3377 }while(0) 3378 #define __rtc_get_alarm_flag() \ 3379 do{ \ 3380 while(!__rtc_write_ready()); \ 3381 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \ 3382 while(0) 3383 #define __rtc_clear_alarm_flag() \ 3384 do{ \ 3385 while(!__rtc_write_ready()); \ 3386 REG_RTC_RCR &= ~RTC_RCR_AF; \ 3387 }while(0) 3388 #define __rtc_get_second() \ 3389 do{ \ 3390 while(!__rtc_write_ready());\ 3391 REG_RTC_RSR; \ 3392 }while(0) 3393 3394 #define __rtc_set_second(v) \ 3395 do{ \ 3396 while(!__rtc_write_ready()); \ 3397 REG_RTC_RSR = v; \ 3398 }while(0) 3399 3400 #define __rtc_get_alarm_second() \ 3401 do{ \ 3402 while(!__rtc_write_ready()); \ 3403 REG_RTC_RSAR; \ 3404 }while(0) 3405 3406 3407 #define __rtc_set_alarm_second(v) \ 3408 do{ \ 3409 while(!__rtc_write_ready()); \ 3410 REG_RTC_RSAR = v; \ 3411 }while(0) 3412 3413 #define __rtc_RGR_is_locked() \ 3414 do{ \ 3415 while(!__rtc_write_ready()); \ 3416 REG_RTC_RGR >> RTC_RGR_LOCK; \ 3417 }while(0) 3418 #define __rtc_lock_RGR() \ 3419 do{ \ 3420 while(!__rtc_write_ready()); \ 3421 REG_RTC_RGR |= RTC_RGR_LOCK; \ 3422 }while(0) 3423 3424 #define __rtc_unlock_RGR() \ 3425 do{ \ 3426 while(!__rtc_write_ready()); \ 3427 REG_RTC_RGR &= ~RTC_RGR_LOCK; \ 3428 }while(0) 3429 3430 #define __rtc_get_adjc_val() \ 3431 do{ \ 3432 while(!__rtc_write_ready()); \ 3433 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ 3434 }while(0) 3435 #define __rtc_set_adjc_val(v) \ 3436 do{ \ 3437 while(!__rtc_write_ready()); \ 3438 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \ 3439 }while(0) 3440 3441 #define __rtc_get_nc1Hz_val() \ 3442 while(!__rtc_write_ready()); \ 3443 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) 3444 3445 #define __rtc_set_nc1Hz_val(v) \ 3446 do{ \ 3447 while(!__rtc_write_ready()); \ 3448 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \ 3449 }while(0) 3450 #define __rtc_power_down() \ 3451 do{ \ 3452 while(!__rtc_write_ready()); \ 3453 REG_RTC_HCR |= RTC_HCR_PD; \ 3454 }while(0) 3455 3456 #define __rtc_get_hwfcr_val() \ 3457 do{ \ 3458 while(!__rtc_write_ready()); \ 3459 REG_RTC_HWFCR & RTC_HWFCR_MASK; \ 3460 }while(0) 3461 #define __rtc_set_hwfcr_val(v) \ 3462 do{ \ 3463 while(!__rtc_write_ready()); \ 3464 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ 3465 }while(0) 3466 3467 #define __rtc_get_hrcr_val() \ 3468 do{ \ 3469 while(!__rtc_write_ready()); \ 3470 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ 3471 }while(0) 3472 #define __rtc_set_hrcr_val(v) \ 3473 do{ \ 3474 while(!__rtc_write_ready()); \ 3475 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ 3476 }while(0) 3477 3478 #define __rtc_enable_alarm_wakeup() \ 3479 do{ \ 3480 while(!__rtc_write_ready()); \ 3481 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ 3482 }while(0) 3483 3484 #define __rtc_disable_alarm_wakeup() \ 3485 do{ \ 3486 while(!__rtc_write_ready()); \ 3487 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ 3488 }while(0) 3489 3490 #define __rtc_status_hib_reset_occur() \ 3491 do{ \ 3492 while(!__rtc_write_ready()); \ 3493 ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \ 3494 }while(0) 3495 #define __rtc_status_ppr_reset_occur() \ 3496 do{ \ 3497 while(!__rtc_write_ready()); \ 3498 ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \ 3499 }while(0) 3500 #define __rtc_status_wakeup_pin_waken_up() \ 3501 do{ \ 3502 while(!__rtc_write_ready()); \ 3503 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ 3504 }while(0) 3505 #define __rtc_status_alarm_waken_up() \ 3506 do{ \ 3507 while(!__rtc_write_ready()); \ 3508 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ 3509 }while(0) 3510 #define __rtc_clear_hib_stat_all() \ 3511 do{ \ 3512 while(!__rtc_write_ready()); \ 3513 ( REG_RTC_HWRSR = 0 ); \ 3514 }while(0) 3515 3516 #define __rtc_get_scratch_pattern() \ 3517 while(!__rtc_write_ready()); \ 3518 (REG_RTC_HSPR) 3519 #define __rtc_set_scratch_pattern(n) \ 3520 do{ \ 3521 while(!__rtc_write_ready()); \ 3522 (REG_RTC_HSPR = n ); \ 3523 }while(0) 3524 3525 3526 #endif /* !__ASSEMBLY__ */ 3527 3528 #endif /* __JZ4740_H__ */