1 /* 2 * Generic board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 5 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 6 * Copyright (C) 2006 Stefan Roese, DENX Software Engineering, sr@denx.de. 7 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 8 * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> 9 * 10 * This program is free software: you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 3 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program. If not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifdef CONFIG_CPU_JZ4730 25 #include "jz4730.h" 26 #include "jz4730_compat.h" 27 #else 28 #include "jz4740.h" 29 #endif 30 31 #include "memory.h" 32 #include "sdram.h" 33 #include "cpm.h" 34 #include "gpio.h" 35 #include "usb_boot_defines.h" 36 37 /* These arguments are initialised by usbboot and are defined in... 38 /etc/xburst-tools/usbboot.cfg. */ 39 40 struct fw_args *fw_args; 41 volatile uint32_t FW_CPU_ID; 42 volatile uint8_t FW_SDRAM_BW16; 43 volatile uint8_t FW_SDRAM_BANK4; 44 volatile uint8_t FW_SDRAM_ROW; 45 volatile uint8_t FW_SDRAM_COL; 46 volatile uint8_t FW_CONFIG_MOBILE_SDRAM; 47 volatile uint8_t FW_IS_SHARE; 48 49 void load_args() 50 { 51 /* Get the fw args from memory. See head1.S for the memory layout. */ 52 53 fw_args = (struct fw_args *) STAGE1_ARGS; 54 FW_CPU_ID = fw_args->cpu_id ; 55 56 /* Where the arguments have not been initialised, use the defaults. */ 57 58 FW_SDRAM_BW16 = FW_CPU_ID ? fw_args->bus_width : SDRAM_BW16; 59 FW_SDRAM_BANK4 = FW_CPU_ID ? fw_args->bank_num : SDRAM_BANK4; 60 FW_SDRAM_ROW = FW_CPU_ID ? fw_args->row_addr : SDRAM_ROW; 61 FW_SDRAM_COL = FW_CPU_ID ? fw_args->col_addr : SDRAM_COL; 62 FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 63 FW_IS_SHARE = fw_args->is_busshare; 64 } 65 66 /* Initialisation functions. */ 67 68 void gpio_init() 69 { 70 void *gpio_port_base; 71 72 #ifdef CONFIG_CPU_JZ4730 73 /* 74 * Initialize SDRAM pins 75 */ 76 77 /* gpio_as_emc */ 78 79 gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, GPIO_PORT_EMC); 80 81 jz4740_gpio_ctrl_update(gpio_port_base, GPIO_GPALR, 0xC0000000, 0x40000000); 82 jz4740_gpio_ctrl_update(gpio_port_base, GPIO_GPAUR, 0x0000FFFF, 0x00005555); 83 #else 84 /* 85 Initialize NAND Flash Pins (gpio_as_nand) 86 CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# 87 */ 88 89 gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 1); 90 91 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x02018000); 92 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x02018000); 93 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x02018000); 94 95 gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 2); 96 97 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x30000000); 98 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x30000000); 99 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x30000000); 100 101 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNC, 0x40000000); 102 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x40000000); 103 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXDIRC, 0x40000000); 104 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x40000000); 105 106 gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 1); 107 108 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x00400000); 109 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x00400000); 110 111 /* 112 Initialize SDRAM pins (gpio_as_sdram_16bit_4720) 113 D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 114 RDWE#, CKO#, WE0#, WE1# 115 */ 116 117 gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 0); 118 119 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x5442bfaa); 120 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x5442bfaa); 121 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x5442bfaa); 122 123 gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 1); 124 125 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x81f9ffff); 126 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x81f9ffff); 127 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x81f9ffff); 128 129 gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, 2); 130 131 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXFUNS, 0x01000000); 132 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXSELC, 0x01000000); 133 jz4740_gpio_ctrl_set(gpio_port_base, GPIO_PXPES, 0x01000000); 134 #endif 135 } 136 137 void pll_init() 138 { 139 register unsigned int cfcr, plcr1; 140 int nf, pllout2; 141 142 /* See CPCCR (Clock Control Register). 143 * 0 == same frequency; 2 == f/3 144 */ 145 146 cfcr = CPM_CPCCR_CLKOEN | 147 CPM_CPCCR_PCS | 148 (0 << CPM_CPCCR_CDIV_BIT) | 149 (2 << CPM_CPCCR_HDIV_BIT) | 150 (2 << CPM_CPCCR_PDIV_BIT) | 151 (2 << CPM_CPCCR_MDIV_BIT) | 152 (2 << CPM_CPCCR_LDIV_BIT); 153 154 /* Init USB Host clock. 155 * Desired frequency == 48MHz 156 */ 157 158 #ifdef CONFIG_CPU_JZ4730 159 cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); 160 #else 161 /* Determine the divider clock output based on the PCS bit. */ 162 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 163 164 /* Divisor == UHCCDR + 1 */ 165 jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_UHCCDR, pllout2 / 48000000 - 1); 166 #endif 167 168 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 169 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 170 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 171 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 172 CPM_CPPCR_PLLEN; /* enable PLL */ 173 174 /* Update PLL and wait. */ 175 176 jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPCCR, cfcr); 177 jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPPCR, plcr1); 178 while (!jz4740_cpm_have_pll((void *) CPM_BASE)); 179 } 180 181 void sdram_init() 182 { 183 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 184 185 unsigned int cas_latency_sdmr[2] = { 186 EMC_SDMR_CAS_2, 187 EMC_SDMR_CAS_3, 188 }; 189 190 unsigned int cas_latency_dmcr[2] = { 191 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 192 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 193 }; 194 195 cpu_clk = jz4740_cpm_get_cpu_frequency((void *) CPM_BASE); 196 mem_clk = jz4740_cpm_get_memory_frequency((void *) CPM_BASE); 197 198 REG_EMC_BCR = 0; /* Disable bus release */ 199 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 200 201 /* Fault DMCR value for mode register setting*/ 202 dmcr0 = (0<<EMC_DMCR_RA_BIT) | 203 (0<<EMC_DMCR_CA_BIT) | 204 (0<<EMC_DMCR_BA_BIT) | 205 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 206 EMC_DMCR_EPIN | 207 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 208 209 /* Basic DMCR value */ 210 dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | 211 ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | 212 ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | 213 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 214 EMC_DMCR_EPIN | 215 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 216 217 /* SDRAM timimg */ 218 ns = 1000000000 / mem_clk; 219 tmp = SDRAM_TRAS/ns; 220 if (tmp < 4) tmp = 4; 221 if (tmp > 11) tmp = 11; 222 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 223 tmp = SDRAM_RCD/ns; 224 if (tmp > 3) tmp = 3; 225 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 226 tmp = SDRAM_TPC/ns; 227 if (tmp > 7) tmp = 7; 228 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 229 tmp = SDRAM_TRWL/ns; 230 if (tmp > 3) tmp = 3; 231 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 232 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 233 if (tmp > 14) tmp = 14; 234 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 235 236 /* SDRAM mode value */ 237 sdmode = EMC_SDMR_BT_SEQ | 238 EMC_SDMR_OM_NORMAL | 239 EMC_SDMR_BL_4 | 240 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 241 242 /* jz4730 additional measures */ 243 #ifdef CONFIG_CPU_JZ4730 244 if (FW_SDRAM_BW16) 245 sdmode <<= 1; 246 else 247 sdmode <<= 2; 248 #endif 249 250 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 251 REG_EMC_DMCR = dmcr; 252 REG8(EMC_SDMR0|sdmode) = 0; 253 254 /* jz4730 additional measures */ 255 #ifdef CONFIG_CPU_JZ4730 256 REG8(EMC_SDMR1|sdmode) = 0; 257 #endif 258 259 /* Wait for precharge, > 200us */ 260 tmp = (cpu_clk / 1000000) * 1000; 261 while (tmp--); 262 263 /* Stage 2. Enable auto-refresh */ 264 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 265 266 tmp = SDRAM_TREF/ns; 267 tmp = tmp/64 + 1; 268 if (tmp > 0xff) tmp = 0xff; 269 REG_EMC_RTCOR = tmp; 270 REG_EMC_RTCNT = 0; 271 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 272 273 /* Wait for number of auto-refresh cycles */ 274 tmp = (cpu_clk / 1000000) * 1000; 275 while (tmp--); 276 277 /* Stage 3. Mode Register Set */ 278 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 279 REG8(EMC_SDMR0|sdmode) = 0; 280 281 /* jz4730 additional measures */ 282 #ifdef CONFIG_CPU_JZ4730 283 REG8(EMC_SDMR1|sdmode) = 0; 284 #endif 285 286 /* Set back to basic DMCR value */ 287 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 288 289 /* everything is ok now */ 290 }