1 /* 2 * JzRISC LCD controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 */ 22 23 #include "sdram.h" 24 #include "jzlcd.h" 25 #include "board.h" 26 27 #define align2(n) (n)=((((n)+1)>>1)<<1) 28 #define align4(n) (n)=((((n)+3)>>2)<<2) 29 #define align8(n) (n)=((((n)+7)>>3)<<3) 30 31 extern struct jzfb_info jzfb; 32 extern vidinfo_t panel_info; 33 34 unsigned long lcd_get_size(void) 35 { 36 int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; 37 return line_length * panel_info.vl_row; 38 } 39 40 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 41 static void jz_lcd_desc_init(vidinfo_t *vid); 42 static int jz_lcd_hw_init(vidinfo_t *vid); 43 44 void lcd_ctrl_init (void *lcdbase) 45 { 46 jz_lcd_init_mem(lcdbase, &panel_info); 47 jz_lcd_desc_init(&panel_info); 48 jz_lcd_hw_init(&panel_info); 49 } 50 51 /* 52 * Before enabled lcd controller, lcd registers should be configured correctly. 53 */ 54 void lcd_enable (void) 55 { 56 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 57 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 58 } 59 60 void lcd_disable (void) 61 { 62 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 63 /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ 64 } 65 66 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 67 { 68 unsigned long palette_mem_size; 69 struct jz_fb_info *fbi = &vid->jz_fb; 70 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; 71 72 fbi->screen = (unsigned long)lcdbase; 73 fbi->palette_size = 256; 74 palette_mem_size = fbi->palette_size * sizeof(u16); 75 76 /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ 77 /* locate palette and descs at end of page following fb */ 78 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 79 80 return 0; 81 } 82 83 static void jz_lcd_desc_init(vidinfo_t *vid) 84 { 85 struct jz_fb_info * fbi; 86 fbi = &vid->jz_fb; 87 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 88 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 89 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 90 91 #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) 92 93 /* populate descriptors */ 94 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 95 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); 96 fbi->dmadesc_fblow->fidr = 0; 97 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; 98 99 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 100 101 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 102 fbi->dmadesc_fbhigh->fidr = 0; 103 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ 104 105 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 106 fbi->dmadesc_palette->fidr = 0; 107 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 108 109 if(NBITS(vid->vl_bpix) < 12) 110 { 111 /* assume any mode with <12 bpp is palette driven */ 112 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 113 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 114 /* flips back and forth between pal and fbhigh */ 115 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 116 } else { 117 /* palette shouldn't be loaded in true-color mode */ 118 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 119 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 120 } 121 122 flush_cache_all(); 123 } 124 125 static int jz_lcd_hw_init(vidinfo_t *vid) 126 { 127 struct jz_fb_info *fbi = &vid->jz_fb; 128 unsigned int val = 0; 129 unsigned int pclk; 130 unsigned int stnH; 131 int pll_div; 132 133 /* Setting Control register */ 134 switch (jzfb.bpp) { 135 case 1: 136 val |= LCD_CTRL_BPP_1; 137 break; 138 case 2: 139 val |= LCD_CTRL_BPP_2; 140 break; 141 case 4: 142 val |= LCD_CTRL_BPP_4; 143 break; 144 case 8: 145 val |= LCD_CTRL_BPP_8; 146 break; 147 case 15: 148 val |= LCD_CTRL_RGB555; 149 case 16: 150 val |= LCD_CTRL_BPP_16; 151 break; 152 case 17 ... 32: 153 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 154 break; 155 156 default: 157 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 158 val |= LCD_CTRL_BPP_16; 159 break; 160 } 161 162 switch (jzfb.cfg & MODE_MASK) { 163 case MODE_STN_MONO_DUAL: 164 case MODE_STN_COLOR_DUAL: 165 case MODE_STN_MONO_SINGLE: 166 case MODE_STN_COLOR_SINGLE: 167 switch (jzfb.bpp) { 168 case 1: 169 /* val |= LCD_CTRL_PEDN; */ 170 case 2: 171 val |= LCD_CTRL_FRC_2; 172 break; 173 case 4: 174 val |= LCD_CTRL_FRC_4; 175 break; 176 case 8: 177 default: 178 val |= LCD_CTRL_FRC_16; 179 break; 180 } 181 break; 182 } 183 184 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 185 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 186 187 switch (jzfb.cfg & MODE_MASK) { 188 case MODE_STN_MONO_DUAL: 189 case MODE_STN_COLOR_DUAL: 190 case MODE_STN_MONO_SINGLE: 191 case MODE_STN_COLOR_SINGLE: 192 switch (jzfb.cfg & STN_DAT_PINMASK) { 193 case STN_DAT_PIN1: 194 /* Do not adjust the hori-param value. */ 195 break; 196 case STN_DAT_PIN2: 197 align2(jzfb.hsw); 198 align2(jzfb.elw); 199 align2(jzfb.blw); 200 break; 201 case STN_DAT_PIN4: 202 align4(jzfb.hsw); 203 align4(jzfb.elw); 204 align4(jzfb.blw); 205 break; 206 case STN_DAT_PIN8: 207 align8(jzfb.hsw); 208 align8(jzfb.elw); 209 align8(jzfb.blw); 210 break; 211 } 212 break; 213 } 214 215 REG_LCD_CTRL = val; 216 217 switch (jzfb.cfg & MODE_MASK) { 218 case MODE_STN_MONO_DUAL: 219 case MODE_STN_COLOR_DUAL: 220 case MODE_STN_MONO_SINGLE: 221 case MODE_STN_COLOR_SINGLE: 222 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 223 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 224 stnH = jzfb.h >> 1; 225 else 226 stnH = jzfb.h; 227 228 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 229 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 230 231 /* Screen setting */ 232 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 233 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 234 REG_LCD_DAV = (0 << 16) | (stnH); 235 236 /* AC BIAs signal */ 237 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 238 239 break; 240 241 case MODE_TFT_GEN: 242 case MODE_TFT_SHARP: 243 case MODE_TFT_CASIO: 244 case MODE_TFT_SAMSUNG: 245 case MODE_8BIT_SERIAL_TFT: 246 case MODE_TFT_18BIT: 247 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 248 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 249 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 250 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 251 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 252 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 253 break; 254 } 255 256 switch (jzfb.cfg & MODE_MASK) { 257 case MODE_TFT_SAMSUNG: 258 { 259 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 260 unsigned int rev_s, rev_e, inv_s, inv_e; 261 262 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 263 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 264 265 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 266 tp_s = jzfb.blw + jzfb.w + 1; 267 tp_e = tp_s + 1; 268 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 269 ckv_s = tp_s - pclk/(1000000000/4100); 270 ckv_e = tp_s + total; 271 rev_s = tp_s - 11; /* -11.5 clk */ 272 rev_e = rev_s + total; 273 inv_s = tp_s; 274 inv_e = inv_s + total; 275 REG_LCD_CLS = (tp_s << 16) | tp_e; 276 REG_LCD_PS = (ckv_s << 16) | ckv_e; 277 REG_LCD_SPL = (rev_s << 16) | rev_e; 278 REG_LCD_REV = (inv_s << 16) | inv_e; 279 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 280 break; 281 } 282 case MODE_TFT_SHARP: 283 { 284 unsigned int total, cls_s, cls_e, ps_s, ps_e; 285 unsigned int spl_s, spl_e, rev_s, rev_e; 286 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 287 spl_s = 1; 288 spl_e = spl_s + 1; 289 cls_s = 0; 290 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 291 ps_s = cls_s; 292 ps_e = cls_e; 293 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 294 rev_e = rev_s + total; 295 jzfb.cfg |= STFT_PSHI; 296 REG_LCD_SPL = (spl_s << 16) | spl_e; 297 REG_LCD_CLS = (cls_s << 16) | cls_e; 298 REG_LCD_PS = (ps_s << 16) | ps_e; 299 REG_LCD_REV = (rev_s << 16) | rev_e; 300 break; 301 } 302 case MODE_TFT_CASIO: 303 break; 304 } 305 306 /* Configure the LCD panel */ 307 REG_LCD_CFG = jzfb.cfg; 308 309 /* Timing setting */ 310 __cpm_stop_lcd(); 311 312 val = jzfb.fclk; /* frame clk */ 313 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 314 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 315 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 316 } else { 317 /* serial mode: Hsync period = 3*Width_Pixel */ 318 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 319 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 320 } 321 322 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 323 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 324 pclk = (pclk * 3); 325 326 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 327 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 328 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 329 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 330 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 331 332 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 333 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 334 pclk >>= 1; 335 336 #ifdef CONFIG_CPU_JZ4730 337 val = __cpm_get_pllout() / pclk; 338 REG_CPM_CFCR2 = val - 1; 339 val = pclk * 4 ; 340 if ( val > 150000000 ) { 341 val = 150000000; 342 } 343 val = __cpm_get_pllout() / val; 344 val--; 345 if ( val > 0xF ) 346 val = 0xF; 347 __cpm_set_lcdclk_div(val); 348 REG_CPM_CFCR |= CPM_CFCR_UPE; 349 #else 350 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 351 pll_div = pll_div ? 1 : 2 ; 352 val = ( __cpm_get_pllout()/pll_div ) / pclk; 353 val--; 354 if ( val > 0x1ff ) { 355 val = 0x1ff; 356 } 357 __cpm_set_pixdiv(val); 358 359 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 360 if ( val > 150000000 ) { 361 val = 150000000; 362 } 363 val = ( __cpm_get_pllout()/pll_div ) / val; 364 val--; 365 if ( val > 0x1f ) { 366 val = 0x1f; 367 } 368 __cpm_set_ldiv( val ); 369 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 370 #endif 371 __cpm_start_lcd(); 372 udelay(1000); 373 374 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 375 376 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 377 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 378 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 379 380 return 0; 381 } 382 383 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 384 { 385 } 386 387 void lcd_initcolregs (void) 388 { 389 }