1 /* 2 * JzRISC lcd controller 3 * 4 * Xiangfu Liu <xiangfu@sharism.cc> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include "lcd.h" 23 24 /* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h 25 via u-boot/arch/mips/include/asm/io.h */ 26 #define virt_to_phys(n) (((int) n) & 0x1fffffff) 27 28 #include "jz4740.h" 29 #include "nanonote_gpm940b0.h" 30 #include "board-nanonote.h" 31 32 #define align2(n) (n)=((((n)+1)>>1)<<1) 33 #define align4(n) (n)=((((n)+3)>>2)<<2) 34 #define align8(n) (n)=((((n)+7)>>3)<<3) 35 36 struct jzfb_info { 37 unsigned int cfg; /* panel mode and pin usage etc. */ 38 unsigned int w; 39 unsigned int h; 40 unsigned int bpp; /* bit per pixel */ 41 unsigned int fclk; /* frame clk */ 42 unsigned int hsw; /* hsync width, in pclk */ 43 unsigned int vsw; /* vsync width, in line count */ 44 unsigned int elw; /* end of line, in pclk */ 45 unsigned int blw; /* begin of line, in pclk */ 46 unsigned int efw; /* end of frame, in line count */ 47 unsigned int bfw; /* begin of frame, in line count */ 48 }; 49 50 static struct jzfb_info jzfb = { 51 MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, 52 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 53 }; 54 55 vidinfo_t panel_info = { 56 320, 240, LCD_BPP, 57 }; 58 59 int lcd_line_length; 60 int lcd_color_fg; 61 int lcd_color_bg; 62 /* 63 * Frame buffer memory information 64 */ 65 void *lcd_base; /* Start of framebuffer memory */ 66 void *lcd_console_address; /* Start of console buffer */ 67 68 short console_col; 69 short console_row; 70 71 void lcd_ctrl_init (void *lcdbase); 72 void lcd_enable (void); 73 void lcd_disable (void); 74 75 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 76 static void jz_lcd_desc_init(vidinfo_t *vid); 77 static int jz_lcd_hw_init(vidinfo_t *vid); 78 /* extern int flush_cache_all(void); */ 79 80 void lcd_ctrl_init (void *lcdbase) 81 { 82 jz_lcd_init_mem(lcdbase, &panel_info); 83 jz_lcd_desc_init(&panel_info); 84 jz_lcd_hw_init(&panel_info); 85 } 86 87 /* 88 * Before enabled lcd controller, lcd registers should be configured correctly. 89 */ 90 void lcd_enable (void) 91 { 92 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 93 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 94 } 95 96 void lcd_disable (void) 97 { 98 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 99 /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ 100 } 101 102 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 103 { 104 unsigned long palette_mem_size; 105 struct jz_fb_info *fbi = &vid->jz_fb; 106 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; 107 108 fbi->screen = (unsigned long)lcdbase; 109 fbi->palette_size = 256; 110 palette_mem_size = fbi->palette_size * sizeof(u16); 111 112 /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ 113 /* locate palette and descs at end of page following fb */ 114 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 115 116 return 0; 117 } 118 119 static void jz_lcd_desc_init(vidinfo_t *vid) 120 { 121 struct jz_fb_info * fbi; 122 fbi = &vid->jz_fb; 123 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 124 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 125 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 126 127 #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) 128 129 /* populate descriptors */ 130 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 131 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); 132 fbi->dmadesc_fblow->fidr = 0; 133 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; 134 135 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 136 137 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 138 fbi->dmadesc_fbhigh->fidr = 0; 139 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ 140 141 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 142 fbi->dmadesc_palette->fidr = 0; 143 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 144 145 if(NBITS(vid->vl_bpix) < 12) 146 { 147 /* assume any mode with <12 bpp is palette driven */ 148 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 149 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 150 /* flips back and forth between pal and fbhigh */ 151 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 152 } else { 153 /* palette shouldn't be loaded in true-color mode */ 154 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 155 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 156 } 157 158 flush_cache_all(); 159 } 160 161 static int jz_lcd_hw_init(vidinfo_t *vid) 162 { 163 struct jz_fb_info *fbi = &vid->jz_fb; 164 unsigned int val = 0; 165 unsigned int pclk; 166 unsigned int stnH; 167 int pll_div; 168 169 /* Setting Control register */ 170 switch (jzfb.bpp) { 171 case 1: 172 val |= LCD_CTRL_BPP_1; 173 break; 174 case 2: 175 val |= LCD_CTRL_BPP_2; 176 break; 177 case 4: 178 val |= LCD_CTRL_BPP_4; 179 break; 180 case 8: 181 val |= LCD_CTRL_BPP_8; 182 break; 183 case 15: 184 val |= LCD_CTRL_RGB555; 185 case 16: 186 val |= LCD_CTRL_BPP_16; 187 break; 188 case 17 ... 32: 189 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 190 break; 191 192 default: 193 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 194 val |= LCD_CTRL_BPP_16; 195 break; 196 } 197 198 switch (jzfb.cfg & MODE_MASK) { 199 case MODE_STN_MONO_DUAL: 200 case MODE_STN_COLOR_DUAL: 201 case MODE_STN_MONO_SINGLE: 202 case MODE_STN_COLOR_SINGLE: 203 switch (jzfb.bpp) { 204 case 1: 205 /* val |= LCD_CTRL_PEDN; */ 206 case 2: 207 val |= LCD_CTRL_FRC_2; 208 break; 209 case 4: 210 val |= LCD_CTRL_FRC_4; 211 break; 212 case 8: 213 default: 214 val |= LCD_CTRL_FRC_16; 215 break; 216 } 217 break; 218 } 219 220 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 221 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 222 223 switch (jzfb.cfg & MODE_MASK) { 224 case MODE_STN_MONO_DUAL: 225 case MODE_STN_COLOR_DUAL: 226 case MODE_STN_MONO_SINGLE: 227 case MODE_STN_COLOR_SINGLE: 228 switch (jzfb.cfg & STN_DAT_PINMASK) { 229 case STN_DAT_PIN1: 230 /* Do not adjust the hori-param value. */ 231 break; 232 case STN_DAT_PIN2: 233 align2(jzfb.hsw); 234 align2(jzfb.elw); 235 align2(jzfb.blw); 236 break; 237 case STN_DAT_PIN4: 238 align4(jzfb.hsw); 239 align4(jzfb.elw); 240 align4(jzfb.blw); 241 break; 242 case STN_DAT_PIN8: 243 align8(jzfb.hsw); 244 align8(jzfb.elw); 245 align8(jzfb.blw); 246 break; 247 } 248 break; 249 } 250 251 REG_LCD_CTRL = val; 252 253 switch (jzfb.cfg & MODE_MASK) { 254 case MODE_STN_MONO_DUAL: 255 case MODE_STN_COLOR_DUAL: 256 case MODE_STN_MONO_SINGLE: 257 case MODE_STN_COLOR_SINGLE: 258 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 259 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 260 stnH = jzfb.h >> 1; 261 else 262 stnH = jzfb.h; 263 264 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 265 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 266 267 /* Screen setting */ 268 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 269 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 270 REG_LCD_DAV = (0 << 16) | (stnH); 271 272 /* AC BIAs signal */ 273 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 274 275 break; 276 277 case MODE_TFT_GEN: 278 case MODE_TFT_SHARP: 279 case MODE_TFT_CASIO: 280 case MODE_TFT_SAMSUNG: 281 case MODE_8BIT_SERIAL_TFT: 282 case MODE_TFT_18BIT: 283 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 284 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 285 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 286 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 287 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 288 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 289 break; 290 } 291 292 switch (jzfb.cfg & MODE_MASK) { 293 case MODE_TFT_SAMSUNG: 294 { 295 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 296 unsigned int rev_s, rev_e, inv_s, inv_e; 297 298 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 299 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 300 301 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 302 tp_s = jzfb.blw + jzfb.w + 1; 303 tp_e = tp_s + 1; 304 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 305 ckv_s = tp_s - pclk/(1000000000/4100); 306 ckv_e = tp_s + total; 307 rev_s = tp_s - 11; /* -11.5 clk */ 308 rev_e = rev_s + total; 309 inv_s = tp_s; 310 inv_e = inv_s + total; 311 REG_LCD_CLS = (tp_s << 16) | tp_e; 312 REG_LCD_PS = (ckv_s << 16) | ckv_e; 313 REG_LCD_SPL = (rev_s << 16) | rev_e; 314 REG_LCD_REV = (inv_s << 16) | inv_e; 315 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 316 break; 317 } 318 case MODE_TFT_SHARP: 319 { 320 unsigned int total, cls_s, cls_e, ps_s, ps_e; 321 unsigned int spl_s, spl_e, rev_s, rev_e; 322 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 323 spl_s = 1; 324 spl_e = spl_s + 1; 325 cls_s = 0; 326 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 327 ps_s = cls_s; 328 ps_e = cls_e; 329 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 330 rev_e = rev_s + total; 331 jzfb.cfg |= STFT_PSHI; 332 REG_LCD_SPL = (spl_s << 16) | spl_e; 333 REG_LCD_CLS = (cls_s << 16) | cls_e; 334 REG_LCD_PS = (ps_s << 16) | ps_e; 335 REG_LCD_REV = (rev_s << 16) | rev_e; 336 break; 337 } 338 case MODE_TFT_CASIO: 339 break; 340 } 341 342 /* Configure the LCD panel */ 343 REG_LCD_CFG = jzfb.cfg; 344 345 /* Timing setting */ 346 __cpm_stop_lcd(); 347 348 val = jzfb.fclk; /* frame clk */ 349 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 350 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 351 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 352 } else { 353 /* serial mode: Hsync period = 3*Width_Pixel */ 354 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 355 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 356 } 357 358 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 359 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 360 pclk = (pclk * 3); 361 362 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 363 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 364 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 365 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 366 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 367 368 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 369 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 370 pclk >>= 1; 371 372 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 373 pll_div = pll_div ? 1 : 2 ; 374 val = ( __cpm_get_pllout()/pll_div ) / pclk; 375 val--; 376 if ( val > 0x1ff ) { 377 /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */ 378 val = 0x1ff; 379 } 380 __cpm_set_pixdiv(val); 381 382 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 383 if ( val > 150000000 ) { 384 /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */ 385 /* printf("Change LCDClock to 150MHz\n"); */ 386 val = 150000000; 387 } 388 val = ( __cpm_get_pllout()/pll_div ) / val; 389 val--; 390 if ( val > 0x1f ) { 391 /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */ 392 val = 0x1f; 393 } 394 __cpm_set_ldiv( val ); 395 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 396 397 __cpm_start_lcd(); 398 udelay(1000); 399 400 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 401 402 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 403 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 404 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 405 406 return 0; 407 } 408 409 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 410 { 411 } 412 413 void lcd_initcolregs (void) 414 { 415 }