1 /* 2 * JzRISC LCD controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 */ 22 23 #include "sdram.h" 24 #include "jzlcd.h" 25 #include "cpu.h" 26 #include "board.h" 27 28 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 29 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 30 31 #define align2(n) (n)=((((n)+1)>>1)<<1) 32 #define align4(n) (n)=((((n)+3)>>2)<<2) 33 #define align8(n) (n)=((((n)+7)>>3)<<3) 34 35 extern struct jzfb_info jzfb; 36 extern vidinfo_t panel_info; 37 38 static unsigned long lcd_get_size(vidinfo_t *vid) 39 { 40 int line_length = (vid->vl_col * NBITS(vid->vl_bpix)) / 8; 41 return line_length * vid->vl_row; 42 } 43 44 static unsigned long lcd_get_total_size(vidinfo_t *vid) 45 { 46 /* Round up to nearest full page, or MMU section if defined */ 47 return ALIGN(lcd_get_size(vid), PAGE_SIZE); 48 } 49 50 static unsigned long lcd_setmem(unsigned long addr) 51 { 52 /* Allocate pages for the frame buffer. */ 53 return ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE) - lcd_get_total_size(&panel_info); 54 } 55 56 static int jz_lcd_init_mem(unsigned long lcdbase, vidinfo_t *vid); 57 static void jz_lcd_desc_init(vidinfo_t *vid); 58 static int jz_lcd_hw_init(vidinfo_t *vid); 59 60 void lcd_ctrl_init(unsigned long *lcdbase) 61 { 62 /* Start from the top of memory and obtain a framebuffer region. */ 63 *lcdbase = lcd_setmem(get_memory_size()); 64 65 jz_lcd_init_mem(*lcdbase, &panel_info); 66 jz_lcd_desc_init(&panel_info); 67 jz_lcd_hw_init(&panel_info); 68 } 69 70 /* 71 * Before enabling the LCD controller, LCD registers should be configured correctly. 72 */ 73 void lcd_enable(void) 74 { 75 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 76 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 77 } 78 79 void lcd_disable(void) 80 { 81 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 82 } 83 84 static int jz_lcd_init_mem(unsigned long lcdbase, vidinfo_t *vid) 85 { 86 unsigned long palette_mem_size; 87 struct jz_fb_info *fbi = &vid->jz_fb; 88 unsigned long fb_size = lcd_get_size(vid); 89 90 fbi->screen = lcdbase; 91 fbi->palette_size = 256; 92 palette_mem_size = fbi->palette_size * sizeof(u16); 93 94 /* locate palette and descs at end of page following fb */ 95 fbi->palette = lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 96 97 return 0; 98 } 99 100 static void jz_lcd_desc_init(vidinfo_t *vid) 101 { 102 struct jz_fb_dma_descriptor *descriptors; 103 struct jz_fb_info * fbi; 104 105 fbi = &vid->jz_fb; 106 descriptors = ((struct jz_fb_dma_descriptor *) fbi->palette) - 3; 107 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *) &descriptors[0]; 108 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *) &descriptors[1]; 109 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *) &descriptors[2]; 110 111 /* populate descriptors */ 112 fbi->dmadesc_fblow->fdadr = fbi->dmadesc_fblow; 113 fbi->dmadesc_fblow->fsadr = fbi->screen + lcd_get_size(vid); 114 fbi->dmadesc_fblow->fidr = 0; 115 fbi->dmadesc_fblow->ldcmd = lcd_get_size(vid) / 4 ; 116 117 fbi->fdadr1 = fbi->dmadesc_fblow; /* only used in dual-panel mode */ 118 119 fbi->dmadesc_fbhigh->fsadr = fbi->screen; 120 fbi->dmadesc_fbhigh->fidr = 0; 121 fbi->dmadesc_fbhigh->ldcmd = lcd_get_size(vid) / 4; /* length in word */ 122 123 fbi->dmadesc_palette->fsadr = fbi->palette; 124 fbi->dmadesc_palette->fidr = 0; 125 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 126 127 if(NBITS(vid->vl_bpix) < 12) 128 { 129 /* assume any mode with <12 bpp is palette driven */ 130 fbi->dmadesc_palette->fdadr = fbi->dmadesc_fbhigh; 131 fbi->dmadesc_fbhigh->fdadr = fbi->dmadesc_palette; 132 /* flips back and forth between pal and fbhigh */ 133 fbi->fdadr0 = fbi->dmadesc_palette; 134 } else { 135 /* palette shouldn't be loaded in true-color mode */ 136 fbi->dmadesc_fbhigh->fdadr = fbi->dmadesc_fbhigh; 137 fbi->fdadr0 = fbi->dmadesc_fbhigh; /* no pal just fbhigh */ 138 } 139 140 flush_cache_all(); 141 } 142 143 static int jz_lcd_hw_init(vidinfo_t *vid) 144 { 145 struct jz_fb_info *fbi = &vid->jz_fb; 146 unsigned int val = 0; 147 unsigned int pclk; 148 unsigned int stnH; 149 #ifndef CONFIG_CPU_JZ4730 150 int pll_div; 151 #endif 152 153 /* Setting Control register */ 154 switch (jzfb.bpp) { 155 case 1: 156 val |= LCD_CTRL_BPP_1; 157 break; 158 case 2: 159 val |= LCD_CTRL_BPP_2; 160 break; 161 case 4: 162 val |= LCD_CTRL_BPP_4; 163 break; 164 case 8: 165 val |= LCD_CTRL_BPP_8; 166 break; 167 case 15: 168 val |= LCD_CTRL_RGB555; 169 case 16: 170 val |= LCD_CTRL_BPP_16; 171 break; 172 #ifndef CONFIG_CPU_JZ4730 173 case 17 ... 32: 174 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 175 break; 176 #endif 177 default: 178 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 179 val |= LCD_CTRL_BPP_16; 180 break; 181 } 182 183 switch (jzfb.cfg & MODE_MASK) { 184 case MODE_STN_MONO_DUAL: 185 case MODE_STN_COLOR_DUAL: 186 case MODE_STN_MONO_SINGLE: 187 case MODE_STN_COLOR_SINGLE: 188 switch (jzfb.bpp) { 189 case 1: 190 /* val |= LCD_CTRL_PEDN; */ 191 case 2: 192 val |= LCD_CTRL_FRC_2; 193 break; 194 case 4: 195 val |= LCD_CTRL_FRC_4; 196 break; 197 case 8: 198 default: 199 val |= LCD_CTRL_FRC_16; 200 break; 201 } 202 break; 203 } 204 205 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 206 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 207 208 switch (jzfb.cfg & MODE_MASK) { 209 case MODE_STN_MONO_DUAL: 210 case MODE_STN_COLOR_DUAL: 211 case MODE_STN_MONO_SINGLE: 212 case MODE_STN_COLOR_SINGLE: 213 switch (jzfb.cfg & STN_DAT_PINMASK) { 214 case STN_DAT_PIN1: 215 /* Do not adjust the hori-param value. */ 216 break; 217 case STN_DAT_PIN2: 218 align2(jzfb.hsw); 219 align2(jzfb.elw); 220 align2(jzfb.blw); 221 break; 222 case STN_DAT_PIN4: 223 align4(jzfb.hsw); 224 align4(jzfb.elw); 225 align4(jzfb.blw); 226 break; 227 case STN_DAT_PIN8: 228 align8(jzfb.hsw); 229 align8(jzfb.elw); 230 align8(jzfb.blw); 231 break; 232 } 233 break; 234 } 235 236 REG_LCD_CTRL = val; 237 238 switch (jzfb.cfg & MODE_MASK) { 239 case MODE_STN_MONO_DUAL: 240 case MODE_STN_COLOR_DUAL: 241 case MODE_STN_MONO_SINGLE: 242 case MODE_STN_COLOR_SINGLE: 243 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 244 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 245 stnH = jzfb.h >> 1; 246 else 247 stnH = jzfb.h; 248 249 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 250 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 251 252 /* Screen setting */ 253 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 254 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 255 REG_LCD_DAV = (0 << 16) | (stnH); 256 257 /* AC BIAs signal */ 258 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 259 260 break; 261 262 case MODE_TFT_GEN: 263 case MODE_TFT_SHARP: 264 case MODE_TFT_CASIO: 265 case MODE_TFT_SAMSUNG: 266 case MODE_8BIT_SERIAL_TFT: 267 case MODE_TFT_18BIT: 268 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 269 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 270 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 271 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 272 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 273 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 274 break; 275 } 276 277 switch (jzfb.cfg & MODE_MASK) { 278 case MODE_TFT_SAMSUNG: 279 { 280 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 281 unsigned int rev_s, rev_e, inv_s, inv_e; 282 283 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 284 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 285 286 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 287 tp_s = jzfb.blw + jzfb.w + 1; 288 tp_e = tp_s + 1; 289 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 290 ckv_s = tp_s - pclk/(1000000000/4100); 291 ckv_e = tp_s + total; 292 rev_s = tp_s - 11; /* -11.5 clk */ 293 rev_e = rev_s + total; 294 inv_s = tp_s; 295 inv_e = inv_s + total; 296 REG_LCD_CLS = (tp_s << 16) | tp_e; 297 REG_LCD_PS = (ckv_s << 16) | ckv_e; 298 REG_LCD_SPL = (rev_s << 16) | rev_e; 299 REG_LCD_REV = (inv_s << 16) | inv_e; 300 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 301 break; 302 } 303 case MODE_TFT_SHARP: 304 { 305 unsigned int total, cls_s, cls_e, ps_s, ps_e; 306 unsigned int spl_s, spl_e, rev_s, rev_e; 307 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 308 spl_s = 1; 309 spl_e = spl_s + 1; 310 cls_s = 0; 311 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 312 ps_s = cls_s; 313 ps_e = cls_e; 314 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 315 rev_e = rev_s + total; 316 jzfb.cfg |= STFT_PSHI; 317 REG_LCD_SPL = (spl_s << 16) | spl_e; 318 REG_LCD_CLS = (cls_s << 16) | cls_e; 319 REG_LCD_PS = (ps_s << 16) | ps_e; 320 REG_LCD_REV = (rev_s << 16) | rev_e; 321 break; 322 } 323 case MODE_TFT_CASIO: 324 break; 325 } 326 327 /* Configure the LCD panel */ 328 REG_LCD_CFG = jzfb.cfg; 329 330 /* Timing setting */ 331 __cpm_stop_lcd(); 332 333 val = jzfb.fclk; /* frame clk */ 334 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 335 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 336 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 337 } else { 338 /* serial mode: Hsync period = 3*Width_Pixel */ 339 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 340 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 341 } 342 343 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 344 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 345 pclk = (pclk * 3); 346 347 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 348 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 349 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 350 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 351 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 352 353 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 354 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 355 pclk >>= 1; 356 357 #ifdef CONFIG_CPU_JZ4730 358 val = __cpm_get_pllout() / pclk; 359 REG_CPM_CFCR2 = val - 1; 360 val = pclk * 4 ; 361 if ( val > 150000000 ) { 362 val = 150000000; 363 } 364 val = __cpm_get_pllout() / val; 365 val--; 366 if ( val > 0xF ) 367 val = 0xF; 368 #else 369 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 370 pll_div = pll_div ? 1 : 2 ; 371 val = ( __cpm_get_pllout()/pll_div ) / pclk; 372 val--; 373 if ( val > 0x1ff ) { 374 val = 0x1ff; 375 } 376 __cpm_set_pixdiv(val); 377 378 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 379 if ( val > 150000000 ) { 380 val = 150000000; 381 } 382 val = ( __cpm_get_pllout()/pll_div ) / val; 383 val--; 384 if ( val > 0x1f ) { 385 val = 0x1f; 386 } 387 #endif 388 __cpm_set_ldiv( val ); 389 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 390 391 __cpm_start_lcd(); 392 udelay(1000); 393 394 REG_LCD_DA0 = (unsigned long) fbi->fdadr0; /* frame descriptor */ 395 396 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 397 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 398 REG_LCD_DA1 = (unsigned long) fbi->fdadr1; /* frame descriptor */ 399 400 return 0; 401 } 402 403 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 404 { 405 } 406 407 void lcd_initcolregs (void) 408 { 409 }