1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * 8 * This program is free software; you can redistribute it and/or modify it under 9 * the terms of the GNU General Public License as published by the Free Software 10 * Foundation; either version 3 of the License, or (at your option) any later 11 * version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 15 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "jz4740.h" 23 #include "configs.h" 24 25 void gpio_init(void) 26 { 27 /* 28 * Initialize NAND Flash Pins 29 */ 30 __gpio_as_nand(); 31 32 /* 33 * Initialize SDRAM pins 34 */ 35 __gpio_as_sdram_32bit(); 36 37 /* 38 * Initialize LCD pins 39 */ 40 __gpio_as_lcd_8bit(); 41 42 /* 43 * Initialize MSC pins 44 */ 45 __gpio_as_msc(); 46 47 /* 48 * Initialize Other pins 49 */ 50 unsigned int i; 51 for (i = 0; i < 7; i++){ 52 __gpio_as_input(GPIO_KEYIN_BASE + i); 53 __gpio_enable_pull(GPIO_KEYIN_BASE + i); 54 } 55 56 for (i = 0; i < 8; i++) { 57 __gpio_as_output(GPIO_KEYOUT_BASE + i); 58 __gpio_clear_pin(GPIO_KEYOUT_BASE + i); 59 } 60 61 /* enable the TP4, TP5 as UART0 */ 62 __gpio_jtag_to_uart0(); 63 64 __gpio_as_input(GPIO_KEYIN_8); 65 __gpio_enable_pull(GPIO_KEYIN_8); 66 67 __gpio_as_output(GPIO_AUDIO_POP); 68 __gpio_set_pin(GPIO_AUDIO_POP); 69 70 __gpio_as_output(GPIO_LCD_CS); 71 __gpio_clear_pin(GPIO_LCD_CS); 72 73 __gpio_as_output(GPIO_AMP_EN); 74 __gpio_clear_pin(GPIO_AMP_EN); 75 76 __gpio_as_output(GPIO_SDPW_EN); 77 __gpio_disable_pull(GPIO_SDPW_EN); 78 __gpio_clear_pin(GPIO_SDPW_EN); 79 80 __gpio_as_input(GPIO_SD_DETECT); 81 __gpio_disable_pull(GPIO_SD_DETECT); 82 83 __gpio_as_input(GPIO_USB_DETECT); 84 __gpio_enable_pull(GPIO_USB_DETECT); 85 } 86 87 void cpm_init(void) 88 { 89 __cpm_stop_ipu(); 90 __cpm_stop_cim(); 91 __cpm_stop_i2c(); 92 __cpm_stop_ssi(); 93 __cpm_stop_uart1(); 94 __cpm_stop_sadc(); 95 __cpm_stop_uhc(); 96 __cpm_stop_udc(); 97 __cpm_stop_aic1(); 98 /* __cpm_stop_aic2();*/ 99 } 100 101 void pll_init(void) 102 { 103 register unsigned int cfcr, plcr1; 104 int n2FR[33] = { 105 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 106 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 107 9 108 }; 109 int nf, pllout2; 110 111 cfcr = CPM_CPCCR_CLKOEN | 112 (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | 113 (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | 114 (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | 115 (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | 116 (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); 117 118 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); 119 120 /* Init USB Host clock, pllout2 must be n*48MHz */ 121 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 122 123 nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; 124 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 125 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 126 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 127 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ 128 CPM_CPPCR_PLLEN; /* enable PLL */ 129 130 /* init PLL */ 131 REG_CPM_CPCCR = cfcr; 132 REG_CPM_CPPCR = plcr1; 133 } 134 135 void sdram_init(void) 136 { 137 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 138 139 unsigned int cas_latency_sdmr[2] = { 140 EMC_SDMR_CAS_2, 141 EMC_SDMR_CAS_3, 142 }; 143 144 unsigned int cas_latency_dmcr[2] = { 145 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 146 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 147 }; 148 149 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 150 151 cpu_clk = CFG_CPU_SPEED; 152 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; 153 154 REG_EMC_BCR = 0; /* Disable bus release */ 155 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 156 157 /* Fault DMCR value for mode register setting*/ 158 #define SDRAM_ROW0 11 159 #define SDRAM_COL0 8 160 #define SDRAM_BANK40 0 161 162 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | 163 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | 164 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | 165 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 166 EMC_DMCR_EPIN | 167 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 168 169 /* Basic DMCR value */ 170 dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | 171 ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | 172 (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | 173 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 174 EMC_DMCR_EPIN | 175 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 176 177 /* SDRAM timimg */ 178 ns = 1000000000 / mem_clk; 179 tmp = SDRAM_TRAS/ns; 180 if (tmp < 4) tmp = 4; 181 if (tmp > 11) tmp = 11; 182 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 183 tmp = SDRAM_RCD/ns; 184 if (tmp > 3) tmp = 3; 185 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 186 tmp = SDRAM_TPC/ns; 187 if (tmp > 7) tmp = 7; 188 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 189 tmp = SDRAM_TRWL/ns; 190 if (tmp > 3) tmp = 3; 191 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 192 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 193 if (tmp > 14) tmp = 14; 194 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 195 196 /* SDRAM mode value */ 197 sdmode = EMC_SDMR_BT_SEQ | 198 EMC_SDMR_OM_NORMAL | 199 EMC_SDMR_BL_4 | 200 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 201 202 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 203 REG_EMC_DMCR = dmcr; 204 REG8(EMC_SDMR0|sdmode) = 0; 205 206 /* Wait for precharge, > 200us */ 207 tmp = (cpu_clk / 1000000) * 1000; 208 while (tmp--); 209 210 /* Stage 2. Enable auto-refresh */ 211 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 212 213 tmp = SDRAM_TREF/ns; 214 tmp = tmp/64 + 1; 215 if (tmp > 0xff) tmp = 0xff; 216 REG_EMC_RTCOR = tmp; 217 REG_EMC_RTCNT = 0; 218 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 219 220 /* Wait for number of auto-refresh cycles */ 221 tmp = (cpu_clk / 1000000) * 1000; 222 while (tmp--); 223 224 /* Stage 3. Mode Register Set */ 225 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 226 REG8(EMC_SDMR0|sdmode) = 0; 227 228 /* Set back to basic DMCR value */ 229 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 230 231 /* everything is ok now */ 232 }