1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "jz4740.h" 24 #include "configs.h" 25 #include "nanonote.h" 26 #include "usb_boot_defines.h" 27 28 /* These arguments are initialised by usbboot and are defined in... 29 /etc/xburst-tools/usbboot.cfg. */ 30 31 struct fw_args *fw_args; 32 volatile u32 CPU_ID; 33 volatile u32 UART_BASE; 34 volatile u32 CONFIG_BAUDRATE; 35 volatile u8 SDRAM_BW16; 36 volatile u8 SDRAM_BANK4; 37 volatile u8 SDRAM_ROW; 38 volatile u8 SDRAM_COL; 39 volatile u8 CONFIG_MOBILE_SDRAM; 40 volatile u32 CFG_CPU_SPEED; 41 volatile u32 CFG_EXTAL; 42 volatile u8 PHM_DIV; 43 volatile u8 IS_SHARE; 44 45 void load_args(void) 46 { 47 /* Get the fw args from memory. See head.S for the memory layout. */ 48 49 fw_args = (struct fw_args *)0x80002008; 50 CPU_ID = fw_args->cpu_id ; 51 CFG_EXTAL = (u32)fw_args->ext_clk * 1000000; 52 CFG_CPU_SPEED = (u32)fw_args->cpu_speed * CFG_EXTAL ; 53 if (CFG_EXTAL == 19000000) { 54 CFG_EXTAL = 19200000; 55 CFG_CPU_SPEED = 192000000; 56 } 57 PHM_DIV = fw_args->phm_div; 58 UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000; 59 CONFIG_BAUDRATE = fw_args->boudrate; 60 SDRAM_BW16 = fw_args->bus_width; 61 SDRAM_BANK4 = fw_args->bank_num; 62 SDRAM_ROW = fw_args->row_addr; 63 SDRAM_COL = fw_args->col_addr; 64 CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 65 IS_SHARE = fw_args->is_busshare; 66 } 67 68 /* Initialisation functions. */ 69 70 void gpio_init(void) 71 { 72 /* 73 * Initialize NAND Flash Pins 74 */ 75 __gpio_as_nand(); 76 77 /* 78 * Initialize SDRAM pins 79 */ 80 __gpio_as_sdram_32bit(); 81 } 82 83 void pll_init(void) 84 { 85 register unsigned int cfcr, plcr1; 86 int n2FR[33] = { 87 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 88 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 89 9 90 }; 91 int nf, pllout2; 92 93 cfcr = CPM_CPCCR_CLKOEN | 94 (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | 95 (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | 96 (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | 97 (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | 98 (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); 99 100 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); 101 102 /* Init USB Host clock, pllout2 must be n*48MHz */ 103 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 104 105 nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; 106 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 107 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 108 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 109 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ 110 CPM_CPPCR_PLLEN; /* enable PLL */ 111 112 /* init PLL */ 113 REG_CPM_CPCCR = cfcr; 114 REG_CPM_CPPCR = plcr1; 115 } 116 117 void sdram_init(void) 118 { 119 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 120 121 unsigned int cas_latency_sdmr[2] = { 122 EMC_SDMR_CAS_2, 123 EMC_SDMR_CAS_3, 124 }; 125 126 unsigned int cas_latency_dmcr[2] = { 127 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 128 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 129 }; 130 131 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 132 133 cpu_clk = CFG_CPU_SPEED; 134 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; 135 136 REG_EMC_BCR = 0; /* Disable bus release */ 137 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 138 139 /* Fault DMCR value for mode register setting*/ 140 #define SDRAM_ROW0 11 141 #define SDRAM_COL0 8 142 #define SDRAM_BANK40 0 143 144 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | 145 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | 146 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | 147 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 148 EMC_DMCR_EPIN | 149 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 150 151 /* Basic DMCR value */ 152 dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | 153 ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | 154 (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | 155 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 156 EMC_DMCR_EPIN | 157 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 158 159 /* SDRAM timimg */ 160 ns = 1000000000 / mem_clk; 161 tmp = SDRAM_TRAS/ns; 162 if (tmp < 4) tmp = 4; 163 if (tmp > 11) tmp = 11; 164 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 165 tmp = SDRAM_RCD/ns; 166 if (tmp > 3) tmp = 3; 167 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 168 tmp = SDRAM_TPC/ns; 169 if (tmp > 7) tmp = 7; 170 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 171 tmp = SDRAM_TRWL/ns; 172 if (tmp > 3) tmp = 3; 173 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 174 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 175 if (tmp > 14) tmp = 14; 176 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 177 178 /* SDRAM mode value */ 179 sdmode = EMC_SDMR_BT_SEQ | 180 EMC_SDMR_OM_NORMAL | 181 EMC_SDMR_BL_4 | 182 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 183 184 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 185 REG_EMC_DMCR = dmcr; 186 REG8(EMC_SDMR0|sdmode) = 0; 187 188 /* Wait for precharge, > 200us */ 189 tmp = (cpu_clk / 1000000) * 1000; 190 while (tmp--); 191 192 /* Stage 2. Enable auto-refresh */ 193 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 194 195 tmp = SDRAM_TREF/ns; 196 tmp = tmp/64 + 1; 197 if (tmp > 0xff) tmp = 0xff; 198 REG_EMC_RTCOR = tmp; 199 REG_EMC_RTCNT = 0; 200 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 201 202 /* Wait for number of auto-refresh cycles */ 203 tmp = (cpu_clk / 1000000) * 1000; 204 while (tmp--); 205 206 /* Stage 3. Mode Register Set */ 207 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 208 REG8(EMC_SDMR0|sdmode) = 0; 209 210 /* Set back to basic DMCR value */ 211 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 212 213 /* everything is ok now */ 214 }