1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * 8 * This program is free software; you can redistribute it and/or modify it under 9 * the terms of the GNU General Public License as published by the Free Software 10 * Foundation; either version 3 of the License, or (at your option) any later 11 * version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 15 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "jz4740.h" 23 #include "configs.h" 24 #include "nanonote.h" 25 26 void gpio_init(void) 27 { 28 /* 29 * Initialize NAND Flash Pins 30 */ 31 __gpio_as_nand(); 32 33 /* 34 * Initialize SDRAM pins 35 */ 36 __gpio_as_sdram_32bit(); 37 38 /* 39 * Initialize LCD pins 40 */ 41 __gpio_as_slcd_8bit(); 42 43 /* 44 * Initialize MSC pins 45 */ 46 __gpio_as_msc(); 47 48 /* 49 * Initialize Other pins 50 */ 51 unsigned int i; 52 for (i = 0; i < 7; i++){ 53 __gpio_as_input(GPIO_KEYIN_BASE + i); 54 __gpio_enable_pull(GPIO_KEYIN_BASE + i); 55 } 56 57 for (i = 0; i < 8; i++) { 58 __gpio_as_output(GPIO_KEYOUT_BASE + i); 59 __gpio_clear_pin(GPIO_KEYOUT_BASE + i); 60 } 61 62 /* enable the TP4, TP5 as UART0 */ 63 __gpio_jtag_to_uart0(); 64 65 __gpio_as_input(GPIO_KEYIN_8); 66 __gpio_enable_pull(GPIO_KEYIN_8); 67 68 __gpio_as_output(GPIO_AUDIO_POP); 69 __gpio_set_pin(GPIO_AUDIO_POP); 70 71 __gpio_as_output(GPIO_LCD_CS); 72 __gpio_clear_pin(GPIO_LCD_CS); 73 74 __gpio_as_output(GPIO_AMP_EN); 75 __gpio_clear_pin(GPIO_AMP_EN); 76 77 __gpio_as_output(GPIO_SDPW_EN); 78 __gpio_disable_pull(GPIO_SDPW_EN); 79 __gpio_clear_pin(GPIO_SDPW_EN); 80 81 __gpio_as_input(GPIO_SD_DETECT); 82 __gpio_disable_pull(GPIO_SD_DETECT); 83 84 __gpio_as_input(GPIO_USB_DETECT); 85 __gpio_enable_pull(GPIO_USB_DETECT); 86 } 87 88 void cpm_init(void) 89 { 90 __cpm_stop_ipu(); 91 __cpm_stop_cim(); 92 __cpm_stop_i2c(); 93 __cpm_stop_ssi(); 94 __cpm_stop_uart1(); 95 __cpm_stop_sadc(); 96 __cpm_stop_uhc(); 97 __cpm_stop_udc(); 98 __cpm_stop_aic1(); 99 /* __cpm_stop_aic2();*/ 100 } 101 102 void pll_init(void) 103 { 104 register unsigned int cfcr, plcr1; 105 int n2FR[33] = { 106 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 107 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 108 9 109 }; 110 int nf, pllout2; 111 112 cfcr = CPM_CPCCR_CLKOEN | 113 (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | 114 (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | 115 (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | 116 (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | 117 (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); 118 119 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); 120 121 /* Init USB Host clock, pllout2 must be n*48MHz */ 122 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 123 124 nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; 125 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 126 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 127 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 128 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ 129 CPM_CPPCR_PLLEN; /* enable PLL */ 130 131 /* init PLL */ 132 REG_CPM_CPCCR = cfcr; 133 REG_CPM_CPPCR = plcr1; 134 } 135 136 void sdram_init(void) 137 { 138 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 139 140 unsigned int cas_latency_sdmr[2] = { 141 EMC_SDMR_CAS_2, 142 EMC_SDMR_CAS_3, 143 }; 144 145 unsigned int cas_latency_dmcr[2] = { 146 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 147 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 148 }; 149 150 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 151 152 cpu_clk = CFG_CPU_SPEED; 153 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; 154 155 REG_EMC_BCR = 0; /* Disable bus release */ 156 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 157 158 /* Fault DMCR value for mode register setting*/ 159 #define SDRAM_ROW0 11 160 #define SDRAM_COL0 8 161 #define SDRAM_BANK40 0 162 163 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | 164 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | 165 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | 166 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 167 EMC_DMCR_EPIN | 168 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 169 170 /* Basic DMCR value */ 171 dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | 172 ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | 173 (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | 174 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 175 EMC_DMCR_EPIN | 176 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 177 178 /* SDRAM timimg */ 179 ns = 1000000000 / mem_clk; 180 tmp = SDRAM_TRAS/ns; 181 if (tmp < 4) tmp = 4; 182 if (tmp > 11) tmp = 11; 183 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 184 tmp = SDRAM_RCD/ns; 185 if (tmp > 3) tmp = 3; 186 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 187 tmp = SDRAM_TPC/ns; 188 if (tmp > 7) tmp = 7; 189 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 190 tmp = SDRAM_TRWL/ns; 191 if (tmp > 3) tmp = 3; 192 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 193 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 194 if (tmp > 14) tmp = 14; 195 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 196 197 /* SDRAM mode value */ 198 sdmode = EMC_SDMR_BT_SEQ | 199 EMC_SDMR_OM_NORMAL | 200 EMC_SDMR_BL_4 | 201 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 202 203 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 204 REG_EMC_DMCR = dmcr; 205 REG8(EMC_SDMR0|sdmode) = 0; 206 207 /* Wait for precharge, > 200us */ 208 tmp = (cpu_clk / 1000000) * 1000; 209 while (tmp--); 210 211 /* Stage 2. Enable auto-refresh */ 212 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 213 214 tmp = SDRAM_TREF/ns; 215 tmp = tmp/64 + 1; 216 if (tmp > 0xff) tmp = 0xff; 217 REG_EMC_RTCOR = tmp; 218 REG_EMC_RTCNT = 0; 219 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 220 221 /* Wait for number of auto-refresh cycles */ 222 tmp = (cpu_clk / 1000000) * 1000; 223 while (tmp--); 224 225 /* Stage 3. Mode Register Set */ 226 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 227 REG8(EMC_SDMR0|sdmode) = 0; 228 229 /* Set back to basic DMCR value */ 230 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 231 232 /* everything is ok now */ 233 }