1 /* 2 * Generic board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 5 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 6 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 7 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifdef CONFIG_CPU_JZ4730 24 #include "jz4730.h" 25 #else 26 #include "jz4740.h" 27 #endif 28 29 #include "sdram.h" 30 #include "usb_boot_defines.h" 31 32 /* These arguments are initialised by usbboot and are defined in... 33 /etc/xburst-tools/usbboot.cfg. */ 34 35 struct fw_args *fw_args; 36 volatile u32 FW_CPU_ID; 37 volatile u8 FW_SDRAM_BW16; 38 volatile u8 FW_SDRAM_BANK4; 39 volatile u8 FW_SDRAM_ROW; 40 volatile u8 FW_SDRAM_COL; 41 volatile u8 FW_CONFIG_MOBILE_SDRAM; 42 volatile u8 FW_IS_SHARE; 43 44 void load_args(void) 45 { 46 /* Get the fw args from memory. See head1.S for the memory layout. */ 47 48 fw_args = (struct fw_args *)0x80002008; 49 FW_CPU_ID = fw_args->cpu_id ; 50 FW_SDRAM_BW16 = fw_args->bus_width; 51 FW_SDRAM_BANK4 = fw_args->bank_num; 52 FW_SDRAM_ROW = fw_args->row_addr; 53 FW_SDRAM_COL = fw_args->col_addr; 54 FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 55 FW_IS_SHARE = fw_args->is_busshare; 56 } 57 58 /* Initialisation functions. */ 59 60 void gpio_init(void) 61 { 62 /* 63 * Initialize NAND Flash Pins 64 */ 65 __gpio_as_nand(); 66 67 /* 68 * Initialize SDRAM pins 69 */ 70 __gpio_as_sdram_16bit_4720(); 71 } 72 73 void pll_init(void) 74 { 75 register unsigned int cfcr, plcr1; 76 int nf, pllout2; 77 78 /* See CPCCR (Clock Control Register). 79 * 0 == same frequency; 2 == f/3 80 */ 81 82 cfcr = CPM_CPCCR_CLKOEN | 83 CPM_CPCCR_PCS | 84 (0 << CPM_CPCCR_CDIV_BIT) | 85 (2 << CPM_CPCCR_HDIV_BIT) | 86 (2 << CPM_CPCCR_PDIV_BIT) | 87 (2 << CPM_CPCCR_MDIV_BIT) | 88 (2 << CPM_CPCCR_LDIV_BIT); 89 90 /* Init USB Host clock. 91 * Desired frequency == 48MHz 92 */ 93 94 #ifdef CONFIG_CPU_JZ4730 95 cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); 96 #else 97 /* Determine the divider clock output based on the PCS bit. */ 98 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 99 100 /* Divisor == UHCCDR + 1 */ 101 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 102 #endif 103 104 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 105 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 106 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 107 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 108 CPM_CPPCR_PLLEN; /* enable PLL */ 109 110 /* Update PLL and wait. */ 111 112 REG_CPM_CPCCR = cfcr; 113 REG_CPM_CPPCR = plcr1; 114 while (!__cpm_pll_is_on()); 115 } 116 117 void sdram_init(void) 118 { 119 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 120 unsigned int pllout = __cpm_get_pllout(); 121 122 unsigned int cas_latency_sdmr[2] = { 123 EMC_SDMR_CAS_2, 124 EMC_SDMR_CAS_3, 125 }; 126 127 unsigned int cas_latency_dmcr[2] = { 128 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 129 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 130 }; 131 132 /* Divisors for CPCCR values. */ 133 134 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 135 136 cpu_clk = pllout / div[__cpm_get_cdiv()]; 137 mem_clk = pllout / div[__cpm_get_mdiv()]; 138 139 REG_EMC_BCR = 0; /* Disable bus release */ 140 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 141 142 /* Fault DMCR value for mode register setting*/ 143 dmcr0 = (0<<EMC_DMCR_RA_BIT) | 144 (0<<EMC_DMCR_CA_BIT) | 145 (0<<EMC_DMCR_BA_BIT) | 146 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 147 EMC_DMCR_EPIN | 148 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 149 150 /* Basic DMCR value */ 151 dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | 152 ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | 153 ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | 154 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 155 EMC_DMCR_EPIN | 156 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 157 158 /* SDRAM timimg */ 159 ns = 1000000000 / mem_clk; 160 tmp = SDRAM_TRAS/ns; 161 if (tmp < 4) tmp = 4; 162 if (tmp > 11) tmp = 11; 163 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 164 tmp = SDRAM_RCD/ns; 165 if (tmp > 3) tmp = 3; 166 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 167 tmp = SDRAM_TPC/ns; 168 if (tmp > 7) tmp = 7; 169 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 170 tmp = SDRAM_TRWL/ns; 171 if (tmp > 3) tmp = 3; 172 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 173 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 174 if (tmp > 14) tmp = 14; 175 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 176 177 /* SDRAM mode value */ 178 sdmode = EMC_SDMR_BT_SEQ | 179 EMC_SDMR_OM_NORMAL | 180 EMC_SDMR_BL_4 | 181 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 182 183 /* jz4730 additional measures */ 184 #ifdef CONFIG_CPU_JZ4730 185 if (FW_SDRAM_BW16) 186 sdmode <<= 1; 187 else 188 sdmode <<= 2; 189 #endif 190 191 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 192 REG_EMC_DMCR = dmcr; 193 REG8(EMC_SDMR0|sdmode) = 0; 194 195 /* jz4730 additional measures */ 196 #ifdef CONFIG_CPU_JZ4730 197 REG8(EMC_SDMR1|sdmode) = 0; 198 #endif 199 200 /* Wait for precharge, > 200us */ 201 tmp = (cpu_clk / 1000000) * 1000; 202 while (tmp--); 203 204 /* Stage 2. Enable auto-refresh */ 205 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 206 207 tmp = SDRAM_TREF/ns; 208 tmp = tmp/64 + 1; 209 if (tmp > 0xff) tmp = 0xff; 210 REG_EMC_RTCOR = tmp; 211 REG_EMC_RTCNT = 0; 212 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 213 214 /* Wait for number of auto-refresh cycles */ 215 tmp = (cpu_clk / 1000000) * 1000; 216 while (tmp--); 217 218 /* Stage 3. Mode Register Set */ 219 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 220 REG8(EMC_SDMR0|sdmode) = 0; 221 222 /* jz4730 additional measures */ 223 #ifdef CONFIG_CPU_JZ4730 224 REG8(EMC_SDMR1|sdmode) = 0; 225 #endif 226 227 /* Set back to basic DMCR value */ 228 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 229 230 /* everything is ok now */ 231 }