1 /* 2 * Generic board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 5 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 6 * Copyright (C) 2006 Stefan Roese, DENX Software Engineering, sr@denx.de. 7 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 8 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 9 * 10 * This program is free software: you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 3 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program. If not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifdef CONFIG_CPU_JZ4730 25 #include "jz4730.h" 26 #include "jz4730_compat.h" 27 #else 28 #include "jz4740.h" 29 #endif 30 31 #include "memory.h" 32 #include "sdram.h" 33 #include "usb_boot_defines.h" 34 35 /* These arguments are initialised by usbboot and are defined in... 36 /etc/xburst-tools/usbboot.cfg. */ 37 38 struct fw_args *fw_args; 39 volatile u32 FW_CPU_ID; 40 volatile u8 FW_SDRAM_BW16; 41 volatile u8 FW_SDRAM_BANK4; 42 volatile u8 FW_SDRAM_ROW; 43 volatile u8 FW_SDRAM_COL; 44 volatile u8 FW_CONFIG_MOBILE_SDRAM; 45 volatile u8 FW_IS_SHARE; 46 47 void load_args() 48 { 49 /* Get the fw args from memory. See head1.S for the memory layout. */ 50 51 fw_args = (struct fw_args *) STAGE1_ARGS; 52 FW_CPU_ID = fw_args->cpu_id ; 53 54 /* Where the arguments have not been initialised, use the defaults. */ 55 56 FW_SDRAM_BW16 = FW_CPU_ID ? fw_args->bus_width : SDRAM_BW16; 57 FW_SDRAM_BANK4 = FW_CPU_ID ? fw_args->bank_num : SDRAM_BANK4; 58 FW_SDRAM_ROW = FW_CPU_ID ? fw_args->row_addr : SDRAM_ROW; 59 FW_SDRAM_COL = FW_CPU_ID ? fw_args->col_addr : SDRAM_COL; 60 FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 61 FW_IS_SHARE = fw_args->is_busshare; 62 } 63 64 /* Initialisation functions. */ 65 66 void gpio_init() 67 { 68 #ifdef CONFIG_CPU_JZ4730 69 /* 70 * Initialize SDRAM pins 71 */ 72 __gpio_as_emc(); 73 #else 74 /* 75 * Initialize NAND Flash Pins 76 */ 77 __gpio_as_nand(); 78 79 /* 80 * Initialize SDRAM pins 81 */ 82 __gpio_as_sdram_16bit_4720(); 83 #endif 84 } 85 86 void pll_init() 87 { 88 register unsigned int cfcr, plcr1; 89 int nf, pllout2; 90 91 /* See CPCCR (Clock Control Register). 92 * 0 == same frequency; 2 == f/3 93 */ 94 95 cfcr = CPM_CPCCR_CLKOEN | 96 CPM_CPCCR_PCS | 97 (0 << CPM_CPCCR_CDIV_BIT) | 98 (2 << CPM_CPCCR_HDIV_BIT) | 99 (2 << CPM_CPCCR_PDIV_BIT) | 100 (2 << CPM_CPCCR_MDIV_BIT) | 101 (2 << CPM_CPCCR_LDIV_BIT); 102 103 /* Init USB Host clock. 104 * Desired frequency == 48MHz 105 */ 106 107 #ifdef CONFIG_CPU_JZ4730 108 cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); 109 #else 110 /* Determine the divider clock output based on the PCS bit. */ 111 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 112 113 /* Divisor == UHCCDR + 1 */ 114 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 115 #endif 116 117 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 118 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 119 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 120 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 121 CPM_CPPCR_PLLEN; /* enable PLL */ 122 123 /* Update PLL and wait. */ 124 125 REG_CPM_CPCCR = cfcr; 126 REG_CPM_CPPCR = plcr1; 127 while (!__cpm_pll_is_on()); 128 } 129 130 void sdram_init() 131 { 132 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 133 unsigned int pllout = __cpm_get_pllout(); 134 135 unsigned int cas_latency_sdmr[2] = { 136 EMC_SDMR_CAS_2, 137 EMC_SDMR_CAS_3, 138 }; 139 140 unsigned int cas_latency_dmcr[2] = { 141 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 142 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 143 }; 144 145 /* Divisors for CPCCR values. */ 146 147 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 148 149 cpu_clk = pllout / div[__cpm_get_cdiv()]; 150 mem_clk = pllout / div[__cpm_get_mdiv()]; 151 152 REG_EMC_BCR = 0; /* Disable bus release */ 153 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 154 155 /* Fault DMCR value for mode register setting*/ 156 dmcr0 = (0<<EMC_DMCR_RA_BIT) | 157 (0<<EMC_DMCR_CA_BIT) | 158 (0<<EMC_DMCR_BA_BIT) | 159 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 160 EMC_DMCR_EPIN | 161 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 162 163 /* Basic DMCR value */ 164 dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | 165 ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | 166 ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | 167 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 168 EMC_DMCR_EPIN | 169 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 170 171 /* SDRAM timimg */ 172 ns = 1000000000 / mem_clk; 173 tmp = SDRAM_TRAS/ns; 174 if (tmp < 4) tmp = 4; 175 if (tmp > 11) tmp = 11; 176 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 177 tmp = SDRAM_RCD/ns; 178 if (tmp > 3) tmp = 3; 179 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 180 tmp = SDRAM_TPC/ns; 181 if (tmp > 7) tmp = 7; 182 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 183 tmp = SDRAM_TRWL/ns; 184 if (tmp > 3) tmp = 3; 185 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 186 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 187 if (tmp > 14) tmp = 14; 188 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 189 190 /* SDRAM mode value */ 191 sdmode = EMC_SDMR_BT_SEQ | 192 EMC_SDMR_OM_NORMAL | 193 EMC_SDMR_BL_4 | 194 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 195 196 /* jz4730 additional measures */ 197 #ifdef CONFIG_CPU_JZ4730 198 if (FW_SDRAM_BW16) 199 sdmode <<= 1; 200 else 201 sdmode <<= 2; 202 #endif 203 204 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 205 REG_EMC_DMCR = dmcr; 206 REG8(EMC_SDMR0|sdmode) = 0; 207 208 /* jz4730 additional measures */ 209 #ifdef CONFIG_CPU_JZ4730 210 REG8(EMC_SDMR1|sdmode) = 0; 211 #endif 212 213 /* Wait for precharge, > 200us */ 214 tmp = (cpu_clk / 1000000) * 1000; 215 while (tmp--); 216 217 /* Stage 2. Enable auto-refresh */ 218 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 219 220 tmp = SDRAM_TREF/ns; 221 tmp = tmp/64 + 1; 222 if (tmp > 0xff) tmp = 0xff; 223 REG_EMC_RTCOR = tmp; 224 REG_EMC_RTCNT = 0; 225 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 226 227 /* Wait for number of auto-refresh cycles */ 228 tmp = (cpu_clk / 1000000) * 1000; 229 while (tmp--); 230 231 /* Stage 3. Mode Register Set */ 232 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 233 REG8(EMC_SDMR0|sdmode) = 0; 234 235 /* jz4730 additional measures */ 236 #ifdef CONFIG_CPU_JZ4730 237 REG8(EMC_SDMR1|sdmode) = 0; 238 #endif 239 240 /* Set back to basic DMCR value */ 241 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 242 243 /* everything is ok now */ 244 }