1 /* 2 * CPU-specific routines originally from U-Boot. 3 * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c 4 * See: u-boot/arch/mips/include/asm/cacheops.h 5 * 6 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 7 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #include "cpu.h" 26 #include "sdram.h" 27 28 void flush_icache_all(void) 29 { 30 u32 addr, t = 0; 31 32 asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ 33 asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ 34 35 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; 36 addr += CONFIG_SYS_CACHELINE_SIZE) { 37 asm volatile ( 38 ".set mips3\n\t" 39 " cache %0, 0(%1)\n\t" 40 ".set mips2\n\t" 41 : 42 : "I" (Index_Store_Tag_I), "r"(addr)); 43 } 44 45 /* invalicate btb */ 46 asm volatile ( 47 ".set mips32\n\t" 48 "mfc0 %0, $16, 7\n\t" 49 "nop\n\t" 50 "ori %0,2\n\t" 51 "mtc0 %0, $16, 7\n\t" 52 ".set mips2\n\t" 53 : 54 : "r" (t)); 55 } 56 57 void flush_dcache_all(void) 58 { 59 u32 addr; 60 61 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; 62 addr += CONFIG_SYS_CACHELINE_SIZE) { 63 asm volatile ( 64 ".set mips3\n\t" 65 " cache %0, 0(%1)\n\t" 66 ".set mips2\n\t" 67 : 68 : "I" (Index_Writeback_Inv_D), "r"(addr)); 69 } 70 71 asm volatile ("sync"); 72 } 73 74 void flush_cache_all(void) 75 { 76 flush_dcache_all(); 77 flush_icache_all(); 78 } 79 80 void handle_error_level(void) 81 { 82 asm volatile( 83 "mfc0 $t3, $12\n" /* CP0_STATUS */ 84 "li $t4, 0xfffffffb\n" /* ERL = 0 */ 85 "and $t3, $t3, $t4\n" 86 "mtc0 $t3, $12\n" 87 "nop\n"); 88 } 89 90 void enable_interrupts(void) 91 { 92 asm volatile( 93 "mfc0 $t3, $12\n" /* CP0_STATUS */ 94 "li $t4, 0x0000fc01\n" /* IE = enable interrupts */ 95 "or $t3, $t3, $t4\n" 96 "mtc0 $t3, $12\n" 97 "nop\n"); 98 } 99 100 void init_interrupts(void) 101 { 102 /* Set exception registers. */ 103 104 asm volatile( 105 "mtc0 $zero, $18\n" /* CP0_WATCHLO */ 106 "li $t3, 0x00800000\n" /* IV = 1 (use 0x80000200 for interrupts) */ 107 "mtc0 $t3, $13\n" /* CP0_CAUSE */ 108 "mfc0 $t4, $12\n" /* CP0_STATUS */ 109 "li $t3, 0xffbfffff\n" /* BEV=0 */ 110 "and $t3, $t3, $t4\n" 111 "mtc0 $t3, $12\n" 112 "nop\n"); 113 } 114 115 void set_task(u8 asid) 116 { 117 asm volatile( 118 119 /* Set the ASID. */ 120 121 "mtc0 %0, $10\n" /* CP0_ENTRYHI */ 122 "nop" 123 : 124 : "r" (asid) 125 ); 126 } 127 128 void init_registers(u32 *base, u32 got, void (*function)(), u32 args[], u8 nargs) 129 { 130 u8 i; 131 132 /* Provide arguments to the function. */ 133 134 for (i = 0; i < nargs; i++) 135 { 136 base[i+4] = args[i]; 137 } 138 139 /* Store essential data for the function environment. */ 140 141 base[25] = (u32) function - 0x80000000; /* store the function address as t9 */ 142 base[26] = got - 0x80000000; /* store the global pointer */ 143 base[29] = (u32) function - 0x80000000; /* store the function address as EPC (for the handler) */ 144 } 145 146 void enter_user_mode(void) 147 { 148 asm volatile( 149 "mfc0 $t3, $12\n" /* CP0_STATUS */ 150 "li $t4, 0x00000010\n" /* KSU = 2 (UM = 1) */ 151 "or $t3, $t3, $t4\n" 152 "mtc0 $t3, $12\n" 153 "nop\n"); 154 } 155 156 void init_tlb(void) 157 { 158 unsigned short first_random = 0; 159 160 asm volatile( 161 "mtc0 $zero, $4\n" /* CP0_CONTEXT */ 162 "mtc0 $zero, $10\n" /* CP0_ENTRYHI */ 163 "mtc0 $zero, $2\n" /* CP0_ENTRYLO0 */ 164 "mtc0 $zero, $3\n" /* CP0_ENTRYLO1 */ 165 "mtc0 %0, $6\n" /* CP0_WIRED */ 166 "nop" 167 : 168 : "r" (first_random) 169 ); 170 } 171 172 void map_page_index(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid, u32 index) 173 { 174 u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ 175 u32 lower = ((physical & 0xfffff000) >> 6) | flags; 176 u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; 177 u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; 178 179 asm volatile( 180 "mtc0 %3, $5\n" /* CP0_PAGEMASK */ 181 182 /* Set the index. */ 183 184 "mtc0 %4, $0\n" /* CP0_INDEX */ 185 186 /* Set physical address. */ 187 188 "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ 189 "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ 190 191 /* Set virtual address. */ 192 193 "mtc0 %2, $10\n" /* CP0_ENTRYHI */ 194 "nop\n" 195 196 "tlbwi\n" 197 "nop" 198 : 199 : "r" (lower), "r" (upper), "r" (start), "r" (pagemask), "r" (index) 200 ); 201 } 202 203 void init_page_table(u32 page_table, u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) 204 { 205 u32 lower = ((physical & 0xfffff000) >> 6) | flags; 206 u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; 207 208 /* 209 With a complete address space mapping involving pairs of 4KB pages 210 described by two values for each entry, there would be... 211 212 an address space of 0x100000000 requiring... 213 214 0x100000000 / (8 * 1024) == 0x100000000 >> 13 215 == 524288 entries 216 == 0x80000 entries 217 218 Thus, each task's entries would require... 219 220 0x80000 * 8 == 0x400000 bytes 221 222 The kseg2 region thus permits 256 tasks occupying 0x40000000 bytes. 223 224 However, for more modest address spaces occupying as much as 32MB there 225 would be... 226 227 an address space of 0x02000000 requiring... 228 229 0x02000000 / (8 * 1024) == 0x02000000 >> 13 230 == 4096 entries 231 == 0x1000 entries 232 233 Thus, each task's entries would only require... 234 235 0x1000 * 8 == 0x8000 bytes 236 */ 237 238 u32 base = page_table + page_table_task_size * asid; 239 240 /* Each page table entry corresponds to a pair of 4KB pages and holds two values. */ 241 242 u32 entry = ((virtual & 0xffffe000) >> 13) * 8; 243 u32 address = base + entry; 244 245 /* The page tables should be permanently mapped to avoid hierarchical TLB miss handling. */ 246 247 asm volatile( 248 "sw %1, 0(%0)\n" 249 "sw %2, 4(%0)\n" 250 : 251 : "r" (address), "r" (lower), "r" (upper) 252 ); 253 } 254 255 void map_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) 256 { 257 u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ 258 u32 lower = ((physical & 0xfffff000) >> 6) | flags; 259 u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; 260 u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; 261 262 asm volatile( 263 "mtc0 %3, $5\n" /* CP0_PAGEMASK */ 264 265 /* Set physical address. */ 266 267 "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ 268 "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ 269 270 /* Set virtual address. */ 271 272 "mtc0 %2, $10\n" /* CP0_ENTRYHI */ 273 "nop\n" 274 275 "tlbwr\n" 276 "nop" 277 : 278 : "r" (lower), "r" (upper), "r" (start), "r" (pagemask) 279 ); 280 } 281 282 void map_page_miss(u32 physical, u32 pagesize, u8 flags) 283 { 284 u32 lower = ((physical & 0xfffff000) >> 6) | flags; 285 u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; 286 u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; 287 288 asm volatile( 289 "mtc0 %2, $5\n" /* CP0_PAGEMASK */ 290 291 /* Set physical address. */ 292 293 "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ 294 "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ 295 "nop\n" 296 297 "tlbwr\n" 298 "nop" 299 : 300 : "r" (lower), "r" (upper), "r" (pagemask) 301 ); 302 } 303 304 void unmap_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) 305 { 306 u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ 307 u32 lower = ((physical & 0xfffff000) >> 6) | flags; 308 u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; 309 u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; 310 u32 index = 0; 311 312 asm volatile( 313 "mtc0 %4, $5\n" /* CP0_PAGEMASK */ 314 315 /* Set physical address. */ 316 317 "mtc0 %1, $2\n" /* CP0_ENTRYLO0 */ 318 "mtc0 %2, $3\n" /* CP0_ENTRYLO1 */ 319 320 /* Set virtual address. */ 321 322 "mtc0 %3, $10\n" /* CP0_ENTRYHI */ 323 "nop\n" 324 325 /* Find an existing mapping. */ 326 327 "tlbp\n" 328 "nop\n" 329 330 /* Read the index register to see if a match was found. */ 331 332 "mfc0 %0, $0\n" /* CP0_INDEX */ 333 "nop" 334 : "=r" (index) 335 : "r" (lower), "r" (upper), "r" (start), "r" (pagemask) 336 ); 337 338 /* Return if the page is not mapped. */ 339 340 if (index & 0x80000000) 341 return; 342 343 /* Otherwise, invalidate the mapping. */ 344 345 map_page_index(virtual, physical, pagesize, flags & 0xfd, asid, index); 346 }