1 /* 2 * JzRISC LCD controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 */ 22 23 #include "sdram.h" 24 #include "jzlcd.h" 25 #include "cpu.h" 26 #include "board.h" 27 28 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 29 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 30 31 #define align2(n) (n)=((((n)+1)>>1)<<1) 32 #define align4(n) (n)=((((n)+3)>>2)<<2) 33 #define align8(n) (n)=((((n)+7)>>3)<<3) 34 35 extern struct jzfb_info jzfb; 36 extern vidinfo_t panel_info; 37 38 static unsigned long lcd_get_size(vidinfo_t *vid) 39 { 40 int line_length = (vid->vl_col * NBITS(vid->vl_bpix)) / 8; 41 return line_length * vid->vl_row; 42 } 43 44 static unsigned long lcd_get_total_size(vidinfo_t *vid) 45 { 46 /* Round up to nearest full page, or MMU section if defined */ 47 return ALIGN(lcd_get_size(vid), PAGE_SIZE); 48 } 49 50 static unsigned long lcd_setmem(unsigned long addr) 51 { 52 /* Allocate pages for the frame buffer. */ 53 return ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE) - lcd_get_total_size(&panel_info); 54 } 55 56 static int jz_lcd_init_mem(unsigned long lcdbase, vidinfo_t *vid); 57 static void jz_lcd_desc_init(vidinfo_t *vid); 58 static int jz_lcd_hw_init(vidinfo_t *vid); 59 60 void lcd_ctrl_init(unsigned long *lcdbase) 61 { 62 /* Start from the top of memory and obtain a framebuffer region. */ 63 *lcdbase = lcd_setmem(get_memory_size()); 64 65 jz_lcd_init_mem(*lcdbase, &panel_info); 66 jz_lcd_desc_init(&panel_info); 67 jz_lcd_hw_init(&panel_info); 68 } 69 70 /* 71 * Before enabling the LCD controller, LCD registers should be configured correctly. 72 */ 73 void lcd_enable(void) 74 { 75 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 76 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 77 } 78 79 void lcd_disable(void) 80 { 81 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 82 } 83 84 static int jz_lcd_init_mem(unsigned long lcdbase, vidinfo_t *vid) 85 { 86 unsigned long palette_mem_size; 87 struct jz_fb_info *fbi = &vid->jz_fb; 88 unsigned long fb_size = lcd_get_size(vid); 89 90 fbi->screen = lcdbase; 91 fbi->palette_size = 256; 92 palette_mem_size = fbi->palette_size * sizeof(u16); 93 94 /* locate palette and descs at end of page following fb */ 95 fbi->palette = lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 96 97 return 0; 98 } 99 100 static void jz_lcd_desc_init(vidinfo_t *vid) 101 { 102 struct jz_fb_dma_descriptor *descriptors; 103 struct jz_fb_info * fbi; 104 105 fbi = &vid->jz_fb; 106 107 /* Allocate space for descriptors before the palette entries. */ 108 109 descriptors = ((struct jz_fb_dma_descriptor *) fbi->palette) - 3; 110 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *) &descriptors[0]; 111 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *) &descriptors[1]; 112 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *) &descriptors[2]; 113 114 /* Populate descriptors. */ 115 116 fbi->dmadesc_fblow->fdadr = fbi->dmadesc_fblow; 117 fbi->dmadesc_fblow->fsadr = fbi->screen + lcd_get_size(vid); 118 fbi->dmadesc_fblow->fidr = 0; 119 fbi->dmadesc_fblow->ldcmd = lcd_get_size(vid) / 4 ; 120 121 fbi->fdadr1 = fbi->dmadesc_fblow; /* only used in dual-panel mode */ 122 123 fbi->dmadesc_fbhigh->fsadr = fbi->screen; 124 fbi->dmadesc_fbhigh->fidr = 0; 125 fbi->dmadesc_fbhigh->ldcmd = lcd_get_size(vid) / 4; /* length in word */ 126 127 fbi->dmadesc_palette->fsadr = fbi->palette; 128 fbi->dmadesc_palette->fidr = 0; 129 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 130 131 if(NBITS(vid->vl_bpix) < 12) 132 { 133 /* assume any mode with <12 bpp is palette driven */ 134 fbi->dmadesc_palette->fdadr = fbi->dmadesc_fbhigh; 135 fbi->dmadesc_fbhigh->fdadr = fbi->dmadesc_palette; 136 /* flips back and forth between pal and fbhigh */ 137 fbi->fdadr0 = fbi->dmadesc_palette; 138 } else { 139 /* palette shouldn't be loaded in true-color mode */ 140 fbi->dmadesc_fbhigh->fdadr = fbi->dmadesc_fbhigh; 141 fbi->fdadr0 = fbi->dmadesc_fbhigh; /* no pal just fbhigh */ 142 } 143 144 flush_cache_all(); 145 } 146 147 static unsigned int jz_lcd_stn_init(unsigned int stnH) 148 { 149 unsigned int val = 0; 150 151 switch (jzfb.bpp) { 152 case 1: 153 /* val |= LCD_CTRL_PEDN; */ 154 case 2: 155 val |= LCD_CTRL_FRC_2; 156 break; 157 case 4: 158 val |= LCD_CTRL_FRC_4; 159 break; 160 case 8: 161 default: 162 val |= LCD_CTRL_FRC_16; 163 break; 164 } 165 166 switch (jzfb.cfg & STN_DAT_PINMASK) { 167 case STN_DAT_PIN1: 168 /* Do not adjust the hori-param value. */ 169 break; 170 case STN_DAT_PIN2: 171 align2(jzfb.hsw); 172 align2(jzfb.elw); 173 align2(jzfb.blw); 174 break; 175 case STN_DAT_PIN4: 176 align4(jzfb.hsw); 177 align4(jzfb.elw); 178 align4(jzfb.blw); 179 break; 180 case STN_DAT_PIN8: 181 align8(jzfb.hsw); 182 align8(jzfb.elw); 183 align8(jzfb.blw); 184 break; 185 } 186 187 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 188 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 189 190 /* Screen setting */ 191 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 192 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 193 REG_LCD_DAV = (0 << 16) | (stnH); 194 195 /* AC BIAs signal */ 196 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 197 198 return val; 199 } 200 201 static void jz_lcd_tft_init() 202 { 203 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 204 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 205 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 206 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 207 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 208 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 209 } 210 211 static int jz_lcd_hw_init(vidinfo_t *vid) 212 { 213 struct jz_fb_info *fbi = &vid->jz_fb; 214 unsigned int val = 0; 215 unsigned int pclk; 216 #ifndef CONFIG_CPU_JZ4730 217 int pll_div; 218 #endif 219 220 /* Setting Control register */ 221 switch (jzfb.bpp) { 222 case 1: 223 val |= LCD_CTRL_BPP_1; 224 break; 225 case 2: 226 val |= LCD_CTRL_BPP_2; 227 break; 228 case 4: 229 val |= LCD_CTRL_BPP_4; 230 break; 231 case 8: 232 val |= LCD_CTRL_BPP_8; 233 break; 234 case 15: 235 val |= LCD_CTRL_RGB555; 236 case 16: 237 val |= LCD_CTRL_BPP_16; 238 break; 239 #ifndef CONFIG_CPU_JZ4730 240 case 17 ... 32: 241 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 242 break; 243 #endif 244 default: 245 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 246 val |= LCD_CTRL_BPP_16; 247 break; 248 } 249 250 switch (jzfb.cfg & MODE_MASK) { 251 case MODE_STN_MONO_DUAL: 252 case MODE_STN_COLOR_DUAL: 253 val |= jz_lcd_stn_init(jzfb.h >> 1); 254 break; 255 256 case MODE_STN_MONO_SINGLE: 257 case MODE_STN_COLOR_SINGLE: 258 val |= jz_lcd_stn_init(jzfb.h); 259 break; 260 261 case MODE_TFT_GEN: 262 case MODE_TFT_CASIO: 263 case MODE_8BIT_SERIAL_TFT: 264 case MODE_TFT_18BIT: 265 jz_lcd_tft_init(); 266 break; 267 268 case MODE_TFT_SAMSUNG: 269 { 270 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 271 unsigned int rev_s, rev_e, inv_s, inv_e; 272 273 jz_lcd_tft_init(); 274 275 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 276 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 277 278 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 279 tp_s = jzfb.blw + jzfb.w + 1; 280 tp_e = tp_s + 1; 281 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 282 ckv_s = tp_s - pclk/(1000000000/4100); 283 ckv_e = tp_s + total; 284 rev_s = tp_s - 11; /* -11.5 clk */ 285 rev_e = rev_s + total; 286 inv_s = tp_s; 287 inv_e = inv_s + total; 288 REG_LCD_CLS = (tp_s << 16) | tp_e; 289 REG_LCD_PS = (ckv_s << 16) | ckv_e; 290 REG_LCD_SPL = (rev_s << 16) | rev_e; 291 REG_LCD_REV = (inv_s << 16) | inv_e; 292 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 293 break; 294 } 295 296 case MODE_TFT_SHARP: 297 { 298 unsigned int total, cls_s, cls_e, ps_s, ps_e; 299 unsigned int spl_s, spl_e, rev_s, rev_e; 300 301 jz_lcd_tft_init(); 302 303 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 304 spl_s = 1; 305 spl_e = spl_s + 1; 306 cls_s = 0; 307 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 308 ps_s = cls_s; 309 ps_e = cls_e; 310 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 311 rev_e = rev_s + total; 312 jzfb.cfg |= STFT_PSHI; 313 REG_LCD_SPL = (spl_s << 16) | spl_e; 314 REG_LCD_CLS = (cls_s << 16) | cls_e; 315 REG_LCD_PS = (ps_s << 16) | ps_e; 316 REG_LCD_REV = (rev_s << 16) | rev_e; 317 break; 318 } 319 320 default: 321 break; 322 } 323 324 /* Configure the LCD panel */ 325 326 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 327 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 328 REG_LCD_CTRL = val; 329 REG_LCD_CFG = jzfb.cfg; 330 331 /* Timing setting */ 332 __cpm_stop_lcd(); 333 334 val = jzfb.fclk; /* frame clk */ 335 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 336 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 337 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 338 } else { 339 /* serial mode: Hsync period = 3*Width_Pixel */ 340 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 341 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 342 } 343 344 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 345 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 346 pclk = (pclk * 3); 347 348 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 349 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 350 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 351 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 352 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 353 354 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 355 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 356 pclk >>= 1; 357 358 #ifdef CONFIG_CPU_JZ4730 359 val = __cpm_get_pllout() / pclk; 360 REG_CPM_CFCR2 = val - 1; 361 val = pclk * 4 ; 362 if ( val > 150000000 ) { 363 val = 150000000; 364 } 365 val = __cpm_get_pllout() / val; 366 val--; 367 if ( val > 0xF ) 368 val = 0xF; 369 #else 370 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 371 pll_div = pll_div ? 1 : 2 ; 372 val = ( __cpm_get_pllout()/pll_div ) / pclk; 373 val--; 374 if ( val > 0x1ff ) { 375 val = 0x1ff; 376 } 377 __cpm_set_pixdiv(val); 378 379 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 380 if ( val > 150000000 ) { 381 val = 150000000; 382 } 383 val = ( __cpm_get_pllout()/pll_div ) / val; 384 val--; 385 if ( val > 0x1f ) { 386 val = 0x1f; 387 } 388 #endif 389 __cpm_set_ldiv( val ); 390 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 391 392 __cpm_start_lcd(); 393 udelay(1000); 394 395 /* Configure DMA. */ 396 397 REG_LCD_DA0 = (unsigned long) fbi->fdadr0; /* frame descriptor */ 398 399 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 400 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 401 REG_LCD_DA1 = (unsigned long) fbi->fdadr1; /* frame descriptor */ 402 403 return 0; 404 } 405 406 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 407 { 408 } 409 410 void lcd_initcolregs (void) 411 { 412 }