1 /* 2 * U-Boot and JzRISC LCD controller definitions 3 * 4 * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. 6 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #ifndef __JZLCD_H__ 26 #define __JZLCD_H__ 27 28 unsigned long lcd_ctrl_init(); 29 void lcd_enable(void); 30 void lcd_disable(void); 31 32 /* 33 * Framebuffer characteristics 34 */ 35 struct jzfb_info { 36 unsigned int cfg; /* panel mode and pin usage etc. */ 37 unsigned int w; 38 unsigned int h; 39 unsigned int bpp; /* bit per pixel */ 40 unsigned int fclk; /* frame clk */ 41 unsigned int hsw; /* hsync width, in pclk */ 42 unsigned int vsw; /* vsync width, in line count */ 43 unsigned int elw; /* end of line, in pclk */ 44 unsigned int blw; /* begin of line, in pclk */ 45 unsigned int efw; /* end of frame, in line count */ 46 unsigned int bfw; /* begin of frame, in line count */ 47 }; 48 49 /* 50 * LCD controller stucture for JZSOC: JZ4740 51 */ 52 struct jz_fb_dma_descriptor { 53 struct jz_fb_dma_descriptor *fdadr; /* Frame descriptor address register */ 54 unsigned long fsadr; /* Frame source address register */ 55 unsigned long fidr; /* Frame ID register */ 56 unsigned long ldcmd; /* Command register */ 57 }; 58 59 /* 60 * Jz LCD info 61 */ 62 struct jz_fb_info { 63 64 struct jz_fb_dma_descriptor *fdadr0; /* physical address of frame/palette descriptor */ 65 struct jz_fb_dma_descriptor *fdadr1; /* physical address of frame descriptor */ 66 67 /* DMA descriptors */ 68 struct jz_fb_dma_descriptor *dmadesc_fblow; 69 struct jz_fb_dma_descriptor *dmadesc_fbhigh; 70 struct jz_fb_dma_descriptor *dmadesc_palette; 71 72 unsigned long screen; /* address of frame buffer */ 73 unsigned long palette; /* address of palette memory */ 74 }; 75 76 /* 77 * Concise display characteristics with low-level structure reference 78 */ 79 typedef struct vidinfo { 80 unsigned short vl_col; /* Number of columns (i.e. 640) */ 81 unsigned short vl_row; /* Number of rows (i.e. 480) */ 82 unsigned char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ 83 84 struct jz_fb_info jz_fb; 85 } vidinfo_t; 86 87 /* Alignment/rounding macros. */ 88 89 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 90 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 91 92 /* General values for colour depths and framebuffer characteristics. */ 93 94 #define LCD_MONOCHROME 0 95 #define LCD_COLOR2 1 96 #define LCD_COLOR4 2 97 #define LCD_COLOR8 3 98 #define LCD_COLOR16 4 99 #define LCD_COLOR32 5 100 101 /* Calculate number of bits per pixel and number of colours. */ 102 103 #define NBITS(bit_code) (1 << (bit_code)) 104 #define NCOLORS(bit_code) (1 << NBITS(bit_code)) 105 106 /* Transfer and display types. */ 107 108 #define MODE_MASK 0x0f 109 #define MODE_TFT_GEN 0x00 110 #define MODE_TFT_SHARP 0x01 111 #define MODE_TFT_CASIO 0x02 112 #define MODE_TFT_SAMSUNG 0x03 113 #define MODE_CCIR656_NONINT 0x04 114 #define MODE_CCIR656_INT 0x05 115 #define MODE_STN_COLOR_SINGLE 0x08 116 #define MODE_STN_MONO_SINGLE 0x09 117 #define MODE_STN_COLOR_DUAL 0x0a 118 #define MODE_STN_MONO_DUAL 0x0b 119 #define MODE_8BIT_SERIAL_TFT 0x0c 120 121 #define MODE_TFT_18BIT (1<<7) 122 123 #define STN_DAT_PIN1 (0x00 << 4) 124 #define STN_DAT_PIN2 (0x01 << 4) 125 #define STN_DAT_PIN4 (0x02 << 4) 126 #define STN_DAT_PIN8 (0x03 << 4) 127 #define STN_DAT_PINMASK STN_DAT_PIN8 128 129 #define STFT_PSHI (1 << 15) 130 #define STFT_CLSHI (1 << 14) 131 #define STFT_SPLHI (1 << 13) 132 #define STFT_REVHI (1 << 12) 133 134 #define SYNC_MASTER (0 << 16) 135 #define SYNC_SLAVE (1 << 16) 136 137 #define DE_P (0 << 9) 138 #define DE_N (1 << 9) 139 140 #define PCLK_P (0 << 10) 141 #define PCLK_N (1 << 10) 142 143 #define HSYNC_P (0 << 11) 144 #define HSYNC_N (1 << 11) 145 146 #define VSYNC_P (0 << 8) 147 #define VSYNC_N (1 << 8) 148 149 #define DATA_NORMAL (0 << 17) 150 #define DATA_INVERSE (1 << 17) 151 152 #endif /* __JZLCD_H__ */