1 /* 2 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 3 * Copyright (C) 2009 Qi Hardware Inc. 4 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 3 of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 /* 23 * This file contains the configuration parameters for the NanoNote. 24 */ 25 #ifndef __NANONOTE_H__ 26 #define __NANONOTE_H__ 27 28 #include "jz4740_lcd.h" 29 30 /* 31 * Display configuration 32 */ 33 #define LCD_BPP LCD_COLOR32 34 35 /* 36 * RAM configuration 37 */ 38 #define CONFIG_SYS_SDRAM_BASE 0x80000000 39 40 /* 41 * SDRAM configuration (timings in ns) 42 */ 43 #define CONFIG_NR_DRAM_BANKS 1 44 45 #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ 46 #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ 47 #define SDRAM_ROW 13 /* Row address: 11 to 13 */ 48 #define SDRAM_COL 9 /* Column address: 8 to 12 */ 49 #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ 50 #define SDRAM_TRAS 45 /* RAS# Active Time */ 51 #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ 52 #define SDRAM_TPC 20 /* RAS# Precharge Time */ 53 #define SDRAM_TRWL 7 /* Write Latency Time */ 54 #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ 55 56 #define SDRAM_ROW0 11 /* Row address minimum */ 57 #define SDRAM_COL0 8 /* Column address minimum */ 58 #define SDRAM_BANK40 0 /* Bank minimum */ 59 60 /* 61 * Cache configuration 62 */ 63 #define CONFIG_SYS_DCACHE_SIZE 16384 64 #define CONFIG_SYS_ICACHE_SIZE 16384 65 #define CONFIG_SYS_CACHELINE_SIZE 32 66 67 /* 68 * Memory configuration 69 */ 70 #define KSEG0 0x80000000 71 #define PAGE_SIZE 4096 72 73 /* 74 * GPIO definition 75 * See: http://en.qi-hardware.com/wiki/Hardware_basics 76 */ 77 #define GPIO_LCD_CS (2 * 32 + 21) 78 #define GPIO_AMP_EN (3 * 32 + 4) 79 80 #define GPIO_SDPW_EN (3 * 32 + 2) 81 #define GPIO_SD_DETECT (3 * 32 + 0) 82 83 #define GPIO_BUZZ_PWM (3 * 32 + 27) 84 #define GPIO_USB_DETECT (3 * 32 + 28) 85 86 #define GPIO_AUDIO_POP (1 * 32 + 29) 87 #define GPIO_COB_TEST (1 * 32 + 30) 88 89 #define GPIO_KEYOUT_BASE (2 * 32 + 10) 90 #define GPIO_KEYIN_BASE (3 * 32 + 18) 91 #define GPIO_KEYIN_8 (3 * 32 + 26) 92 93 #define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ 94 #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ 95 96 #define GPIO_SD_CMD (3 * 32 + 8) 97 98 #define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */ 99 #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */ 100 #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */ 101 102 #endif /* __NANONOTE_H__ */