1 /* 2 * JzRISC lcd controller 3 * 4 * Xiangfu Liu <xiangfu@sharism.cc> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 /* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h 23 via u-boot/arch/mips/include/asm/io.h */ 24 #define virt_to_phys(n) (((int) n) & 0x1fffffff) 25 26 #include "jz4740.h" 27 #include "nanonote_gpm940b0.h" 28 #include "board-nanonote.h" 29 30 #define align2(n) (n)=((((n)+1)>>1)<<1) 31 #define align4(n) (n)=((((n)+3)>>2)<<2) 32 #define align8(n) (n)=((((n)+7)>>3)<<3) 33 34 struct jzfb_info { 35 unsigned int cfg; /* panel mode and pin usage etc. */ 36 unsigned int w; 37 unsigned int h; 38 unsigned int bpp; /* bit per pixel */ 39 unsigned int fclk; /* frame clk */ 40 unsigned int hsw; /* hsync width, in pclk */ 41 unsigned int vsw; /* vsync width, in line count */ 42 unsigned int elw; /* end of line, in pclk */ 43 unsigned int blw; /* begin of line, in pclk */ 44 unsigned int efw; /* end of frame, in line count */ 45 unsigned int bfw; /* begin of frame, in line count */ 46 }; 47 48 static struct jzfb_info jzfb = { 49 MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, 50 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 51 }; 52 53 vidinfo_t panel_info = { 54 320, 240, LCD_BPP, 55 }; 56 57 int lcd_line_length; 58 int lcd_color_fg; 59 int lcd_color_bg; 60 /* 61 * Frame buffer memory information 62 */ 63 void *lcd_base; /* Start of framebuffer memory */ 64 void *lcd_console_address; /* Start of console buffer */ 65 66 short console_col; 67 short console_row; 68 69 void lcd_ctrl_init (void *lcdbase); 70 void lcd_enable (void); 71 void lcd_disable (void); 72 73 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 74 static void jz_lcd_desc_init(vidinfo_t *vid); 75 static int jz_lcd_hw_init(vidinfo_t *vid); 76 /* extern int flush_cache_all(void); */ 77 78 void lcd_ctrl_init (void *lcdbase) 79 { 80 jz_lcd_init_mem(lcdbase, &panel_info); 81 jz_lcd_desc_init(&panel_info); 82 jz_lcd_hw_init(&panel_info); 83 } 84 85 /* 86 * Before enabled lcd controller, lcd registers should be configured correctly. 87 */ 88 void lcd_enable (void) 89 { 90 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 91 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 92 } 93 94 void lcd_disable (void) 95 { 96 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 97 /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ 98 } 99 100 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 101 { 102 unsigned long palette_mem_size; 103 struct jz_fb_info *fbi = &vid->jz_fb; 104 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; 105 106 fbi->screen = (unsigned long)lcdbase; 107 fbi->palette_size = 256; 108 palette_mem_size = fbi->palette_size * sizeof(u16); 109 110 /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ 111 /* locate palette and descs at end of page following fb */ 112 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 113 114 return 0; 115 } 116 117 static void jz_lcd_desc_init(vidinfo_t *vid) 118 { 119 struct jz_fb_info * fbi; 120 fbi = &vid->jz_fb; 121 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 122 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 123 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 124 125 #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) 126 127 /* populate descriptors */ 128 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 129 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); 130 fbi->dmadesc_fblow->fidr = 0; 131 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; 132 133 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 134 135 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 136 fbi->dmadesc_fbhigh->fidr = 0; 137 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ 138 139 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 140 fbi->dmadesc_palette->fidr = 0; 141 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 142 143 if(NBITS(vid->vl_bpix) < 12) 144 { 145 /* assume any mode with <12 bpp is palette driven */ 146 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 147 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 148 /* flips back and forth between pal and fbhigh */ 149 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 150 } else { 151 /* palette shouldn't be loaded in true-color mode */ 152 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 153 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 154 } 155 156 flush_cache_all(); 157 } 158 159 static int jz_lcd_hw_init(vidinfo_t *vid) 160 { 161 struct jz_fb_info *fbi = &vid->jz_fb; 162 unsigned int val = 0; 163 unsigned int pclk; 164 unsigned int stnH; 165 int pll_div; 166 167 /* Setting Control register */ 168 switch (jzfb.bpp) { 169 case 1: 170 val |= LCD_CTRL_BPP_1; 171 break; 172 case 2: 173 val |= LCD_CTRL_BPP_2; 174 break; 175 case 4: 176 val |= LCD_CTRL_BPP_4; 177 break; 178 case 8: 179 val |= LCD_CTRL_BPP_8; 180 break; 181 case 15: 182 val |= LCD_CTRL_RGB555; 183 case 16: 184 val |= LCD_CTRL_BPP_16; 185 break; 186 case 17 ... 32: 187 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 188 break; 189 190 default: 191 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 192 val |= LCD_CTRL_BPP_16; 193 break; 194 } 195 196 switch (jzfb.cfg & MODE_MASK) { 197 case MODE_STN_MONO_DUAL: 198 case MODE_STN_COLOR_DUAL: 199 case MODE_STN_MONO_SINGLE: 200 case MODE_STN_COLOR_SINGLE: 201 switch (jzfb.bpp) { 202 case 1: 203 /* val |= LCD_CTRL_PEDN; */ 204 case 2: 205 val |= LCD_CTRL_FRC_2; 206 break; 207 case 4: 208 val |= LCD_CTRL_FRC_4; 209 break; 210 case 8: 211 default: 212 val |= LCD_CTRL_FRC_16; 213 break; 214 } 215 break; 216 } 217 218 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 219 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 220 221 switch (jzfb.cfg & MODE_MASK) { 222 case MODE_STN_MONO_DUAL: 223 case MODE_STN_COLOR_DUAL: 224 case MODE_STN_MONO_SINGLE: 225 case MODE_STN_COLOR_SINGLE: 226 switch (jzfb.cfg & STN_DAT_PINMASK) { 227 case STN_DAT_PIN1: 228 /* Do not adjust the hori-param value. */ 229 break; 230 case STN_DAT_PIN2: 231 align2(jzfb.hsw); 232 align2(jzfb.elw); 233 align2(jzfb.blw); 234 break; 235 case STN_DAT_PIN4: 236 align4(jzfb.hsw); 237 align4(jzfb.elw); 238 align4(jzfb.blw); 239 break; 240 case STN_DAT_PIN8: 241 align8(jzfb.hsw); 242 align8(jzfb.elw); 243 align8(jzfb.blw); 244 break; 245 } 246 break; 247 } 248 249 REG_LCD_CTRL = val; 250 251 switch (jzfb.cfg & MODE_MASK) { 252 case MODE_STN_MONO_DUAL: 253 case MODE_STN_COLOR_DUAL: 254 case MODE_STN_MONO_SINGLE: 255 case MODE_STN_COLOR_SINGLE: 256 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 257 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 258 stnH = jzfb.h >> 1; 259 else 260 stnH = jzfb.h; 261 262 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 263 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 264 265 /* Screen setting */ 266 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 267 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 268 REG_LCD_DAV = (0 << 16) | (stnH); 269 270 /* AC BIAs signal */ 271 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 272 273 break; 274 275 case MODE_TFT_GEN: 276 case MODE_TFT_SHARP: 277 case MODE_TFT_CASIO: 278 case MODE_TFT_SAMSUNG: 279 case MODE_8BIT_SERIAL_TFT: 280 case MODE_TFT_18BIT: 281 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 282 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 283 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 284 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 285 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 286 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 287 break; 288 } 289 290 switch (jzfb.cfg & MODE_MASK) { 291 case MODE_TFT_SAMSUNG: 292 { 293 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 294 unsigned int rev_s, rev_e, inv_s, inv_e; 295 296 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 297 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 298 299 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 300 tp_s = jzfb.blw + jzfb.w + 1; 301 tp_e = tp_s + 1; 302 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 303 ckv_s = tp_s - pclk/(1000000000/4100); 304 ckv_e = tp_s + total; 305 rev_s = tp_s - 11; /* -11.5 clk */ 306 rev_e = rev_s + total; 307 inv_s = tp_s; 308 inv_e = inv_s + total; 309 REG_LCD_CLS = (tp_s << 16) | tp_e; 310 REG_LCD_PS = (ckv_s << 16) | ckv_e; 311 REG_LCD_SPL = (rev_s << 16) | rev_e; 312 REG_LCD_REV = (inv_s << 16) | inv_e; 313 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 314 break; 315 } 316 case MODE_TFT_SHARP: 317 { 318 unsigned int total, cls_s, cls_e, ps_s, ps_e; 319 unsigned int spl_s, spl_e, rev_s, rev_e; 320 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 321 spl_s = 1; 322 spl_e = spl_s + 1; 323 cls_s = 0; 324 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 325 ps_s = cls_s; 326 ps_e = cls_e; 327 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 328 rev_e = rev_s + total; 329 jzfb.cfg |= STFT_PSHI; 330 REG_LCD_SPL = (spl_s << 16) | spl_e; 331 REG_LCD_CLS = (cls_s << 16) | cls_e; 332 REG_LCD_PS = (ps_s << 16) | ps_e; 333 REG_LCD_REV = (rev_s << 16) | rev_e; 334 break; 335 } 336 case MODE_TFT_CASIO: 337 break; 338 } 339 340 /* Configure the LCD panel */ 341 REG_LCD_CFG = jzfb.cfg; 342 343 /* Timing setting */ 344 __cpm_stop_lcd(); 345 346 val = jzfb.fclk; /* frame clk */ 347 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 348 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 349 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 350 } else { 351 /* serial mode: Hsync period = 3*Width_Pixel */ 352 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 353 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 354 } 355 356 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 357 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 358 pclk = (pclk * 3); 359 360 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 361 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 362 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 363 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 364 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 365 366 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 367 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 368 pclk >>= 1; 369 370 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 371 pll_div = pll_div ? 1 : 2 ; 372 val = ( __cpm_get_pllout()/pll_div ) / pclk; 373 val--; 374 if ( val > 0x1ff ) { 375 /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */ 376 val = 0x1ff; 377 } 378 __cpm_set_pixdiv(val); 379 380 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 381 if ( val > 150000000 ) { 382 /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */ 383 /* printf("Change LCDClock to 150MHz\n"); */ 384 val = 150000000; 385 } 386 val = ( __cpm_get_pllout()/pll_div ) / val; 387 val--; 388 if ( val > 0x1f ) { 389 /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */ 390 val = 0x1f; 391 } 392 __cpm_set_ldiv( val ); 393 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 394 395 __cpm_start_lcd(); 396 udelay(1000); 397 398 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 399 400 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 401 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 402 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 403 404 return 0; 405 } 406 407 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 408 { 409 } 410 411 void lcd_initcolregs (void) 412 { 413 }