1 /* 2 * JzRISC lcd controller 3 * 4 * Xiangfu Liu <xiangfu@sharism.cc> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __QI_LB60_GPM940B0_H__ 23 #define __QI_LB60_GPM940B0_H__ 24 25 #include "nanonote.h" 26 #include "jz4740_lcd.h" 27 #include "jz4740.h" 28 29 unsigned long lcd_get_size(void); 30 void lcd_ctrl_init(void *lcdbase); 31 void lcd_enable(void); 32 void lcd_disable(void); 33 34 struct lcd_desc{ 35 unsigned int next_desc; /* LCDDAx */ 36 unsigned int databuf; /* LCDSAx */ 37 unsigned int frame_id; /* LCDFIDx */ 38 unsigned int cmd; /* LCDCMDx */ 39 }; 40 41 #define MODE_MASK 0x0f 42 #define MODE_TFT_GEN 0x00 43 #define MODE_TFT_SHARP 0x01 44 #define MODE_TFT_CASIO 0x02 45 #define MODE_TFT_SAMSUNG 0x03 46 #define MODE_CCIR656_NONINT 0x04 47 #define MODE_CCIR656_INT 0x05 48 #define MODE_STN_COLOR_SINGLE 0x08 49 #define MODE_STN_MONO_SINGLE 0x09 50 #define MODE_STN_COLOR_DUAL 0x0a 51 #define MODE_STN_MONO_DUAL 0x0b 52 #define MODE_8BIT_SERIAL_TFT 0x0c 53 54 #define MODE_TFT_18BIT (1<<7) 55 56 #define STN_DAT_PIN1 (0x00 << 4) 57 #define STN_DAT_PIN2 (0x01 << 4) 58 #define STN_DAT_PIN4 (0x02 << 4) 59 #define STN_DAT_PIN8 (0x03 << 4) 60 #define STN_DAT_PINMASK STN_DAT_PIN8 61 62 #define STFT_PSHI (1 << 15) 63 #define STFT_CLSHI (1 << 14) 64 #define STFT_SPLHI (1 << 13) 65 #define STFT_REVHI (1 << 12) 66 67 #define SYNC_MASTER (0 << 16) 68 #define SYNC_SLAVE (1 << 16) 69 70 #define DE_P (0 << 9) 71 #define DE_N (1 << 9) 72 73 #define PCLK_P (0 << 10) 74 #define PCLK_N (1 << 10) 75 76 #define HSYNC_P (0 << 11) 77 #define HSYNC_N (1 << 11) 78 79 #define VSYNC_P (0 << 8) 80 #define VSYNC_N (1 << 8) 81 82 #define DATA_NORMAL (0 << 17) 83 #define DATA_INVERSE (1 << 17) 84 85 86 /* Jz LCDFB supported I/O controls. */ 87 #define FBIOSETBACKLIGHT 0x4688 88 #define FBIODISPON 0x4689 89 #define FBIODISPOFF 0x468a 90 #define FBIORESET 0x468b 91 #define FBIOPRINT_REG 0x468c 92 93 /* 94 * LCD panel specific definition 95 */ 96 #define MODE (0xc9) /* 8bit serial RGB */ 97 98 #define __spi_write_reg1(reg, val) \ 99 do { \ 100 unsigned char no; \ 101 unsigned short value; \ 102 unsigned char a=reg; \ 103 unsigned char b=val; \ 104 __gpio_set_pin(SPEN); \ 105 __gpio_set_pin(SPCK); \ 106 __gpio_clear_pin(SPDA); \ 107 __gpio_clear_pin(SPEN); \ 108 value=((a<<8)|(b&0xFF)); \ 109 for(no=0;no<16;no++) \ 110 { \ 111 __gpio_clear_pin(SPCK); \ 112 if((value&0x8000)==0x8000) \ 113 __gpio_set_pin(SPDA); \ 114 else \ 115 __gpio_clear_pin(SPDA); \ 116 __gpio_set_pin(SPCK); \ 117 value=(value<<1); \ 118 } \ 119 __gpio_set_pin(SPEN); \ 120 } while (0) 121 122 #define __lcd_display_pin_init() \ 123 do { \ 124 __cpm_start_tcu(); \ 125 __gpio_as_output(SPEN); \ 126 __gpio_as_output(SPCK); \ 127 __gpio_as_output(SPDA); \ 128 } while (0) 129 130 #define __lcd_display_on() \ 131 do { \ 132 __spi_write_reg1(0x05, 0x1e); \ 133 __spi_write_reg1(0x05, 0x5e); \ 134 __spi_write_reg1(0x07, 0x8d); \ 135 __spi_write_reg1(0x13, 0x01); \ 136 __spi_write_reg1(0x05, 0x5f); \ 137 } while (0) 138 139 #define __lcd_display_off() \ 140 do { \ 141 __spi_write_reg1(0x05, 0x5e); \ 142 } while (0) 143 144 #endif /* __QI_LB60_GPM940B0_H__ */