1 /* 2 * Generic board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 5 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 6 * Copyright (C) 2006 Stefan Roese, DENX Software Engineering, sr@denx.de. 7 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 8 * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> 9 * 10 * This program is free software: you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 3 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program. If not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifdef CONFIG_CPU_JZ4730 25 #include "jz4730.h" 26 #include "jz4730_compat.h" 27 #else 28 #include "jz4740.h" 29 #endif 30 31 #include "memory.h" 32 #include "sdram.h" 33 #include "cpm.h" 34 #include "usb_boot_defines.h" 35 36 /* These arguments are initialised by usbboot and are defined in... 37 /etc/xburst-tools/usbboot.cfg. */ 38 39 struct fw_args *fw_args; 40 volatile uint32_t FW_CPU_ID; 41 volatile uint8_t FW_SDRAM_BW16; 42 volatile uint8_t FW_SDRAM_BANK4; 43 volatile uint8_t FW_SDRAM_ROW; 44 volatile uint8_t FW_SDRAM_COL; 45 volatile uint8_t FW_CONFIG_MOBILE_SDRAM; 46 volatile uint8_t FW_IS_SHARE; 47 48 void load_args() 49 { 50 /* Get the fw args from memory. See head1.S for the memory layout. */ 51 52 fw_args = (struct fw_args *) STAGE1_ARGS; 53 FW_CPU_ID = fw_args->cpu_id ; 54 55 /* Where the arguments have not been initialised, use the defaults. */ 56 57 FW_SDRAM_BW16 = FW_CPU_ID ? fw_args->bus_width : SDRAM_BW16; 58 FW_SDRAM_BANK4 = FW_CPU_ID ? fw_args->bank_num : SDRAM_BANK4; 59 FW_SDRAM_ROW = FW_CPU_ID ? fw_args->row_addr : SDRAM_ROW; 60 FW_SDRAM_COL = FW_CPU_ID ? fw_args->col_addr : SDRAM_COL; 61 FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 62 FW_IS_SHARE = fw_args->is_busshare; 63 } 64 65 /* Initialisation functions. */ 66 67 void gpio_init() 68 { 69 #ifdef CONFIG_CPU_JZ4730 70 /* 71 * Initialize SDRAM pins 72 */ 73 __gpio_as_emc(); 74 #else 75 /* 76 * Initialize NAND Flash Pins 77 */ 78 __gpio_as_nand(); 79 80 /* 81 * Initialize SDRAM pins 82 */ 83 __gpio_as_sdram_16bit_4720(); 84 #endif 85 } 86 87 void pll_init() 88 { 89 register unsigned int cfcr, plcr1; 90 int nf, pllout2; 91 92 /* See CPCCR (Clock Control Register). 93 * 0 == same frequency; 2 == f/3 94 */ 95 96 cfcr = CPM_CPCCR_CLKOEN | 97 CPM_CPCCR_PCS | 98 (0 << CPM_CPCCR_CDIV_BIT) | 99 (2 << CPM_CPCCR_HDIV_BIT) | 100 (2 << CPM_CPCCR_PDIV_BIT) | 101 (2 << CPM_CPCCR_MDIV_BIT) | 102 (2 << CPM_CPCCR_LDIV_BIT); 103 104 /* Init USB Host clock. 105 * Desired frequency == 48MHz 106 */ 107 108 #ifdef CONFIG_CPU_JZ4730 109 cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); 110 #else 111 /* Determine the divider clock output based on the PCS bit. */ 112 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 113 114 /* Divisor == UHCCDR + 1 */ 115 jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_UHCCDR, pllout2 / 48000000 - 1); 116 #endif 117 118 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 119 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 120 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 121 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 122 CPM_CPPCR_PLLEN; /* enable PLL */ 123 124 /* Update PLL and wait. */ 125 126 jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPCCR, cfcr); 127 jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPPCR, plcr1); 128 while (!jz4740_cpm_have_pll((void *) CPM_BASE)); 129 } 130 131 void sdram_init() 132 { 133 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 134 135 unsigned int cas_latency_sdmr[2] = { 136 EMC_SDMR_CAS_2, 137 EMC_SDMR_CAS_3, 138 }; 139 140 unsigned int cas_latency_dmcr[2] = { 141 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 142 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 143 }; 144 145 cpu_clk = jz4740_cpm_get_cpu_frequency((void *) CPM_BASE); 146 mem_clk = jz4740_cpm_get_memory_frequency((void *) CPM_BASE); 147 148 REG_EMC_BCR = 0; /* Disable bus release */ 149 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 150 151 /* Fault DMCR value for mode register setting*/ 152 dmcr0 = (0<<EMC_DMCR_RA_BIT) | 153 (0<<EMC_DMCR_CA_BIT) | 154 (0<<EMC_DMCR_BA_BIT) | 155 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 156 EMC_DMCR_EPIN | 157 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 158 159 /* Basic DMCR value */ 160 dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | 161 ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | 162 ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | 163 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 164 EMC_DMCR_EPIN | 165 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 166 167 /* SDRAM timimg */ 168 ns = 1000000000 / mem_clk; 169 tmp = SDRAM_TRAS/ns; 170 if (tmp < 4) tmp = 4; 171 if (tmp > 11) tmp = 11; 172 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 173 tmp = SDRAM_RCD/ns; 174 if (tmp > 3) tmp = 3; 175 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 176 tmp = SDRAM_TPC/ns; 177 if (tmp > 7) tmp = 7; 178 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 179 tmp = SDRAM_TRWL/ns; 180 if (tmp > 3) tmp = 3; 181 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 182 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 183 if (tmp > 14) tmp = 14; 184 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 185 186 /* SDRAM mode value */ 187 sdmode = EMC_SDMR_BT_SEQ | 188 EMC_SDMR_OM_NORMAL | 189 EMC_SDMR_BL_4 | 190 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 191 192 /* jz4730 additional measures */ 193 #ifdef CONFIG_CPU_JZ4730 194 if (FW_SDRAM_BW16) 195 sdmode <<= 1; 196 else 197 sdmode <<= 2; 198 #endif 199 200 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 201 REG_EMC_DMCR = dmcr; 202 REG8(EMC_SDMR0|sdmode) = 0; 203 204 /* jz4730 additional measures */ 205 #ifdef CONFIG_CPU_JZ4730 206 REG8(EMC_SDMR1|sdmode) = 0; 207 #endif 208 209 /* Wait for precharge, > 200us */ 210 tmp = (cpu_clk / 1000000) * 1000; 211 while (tmp--); 212 213 /* Stage 2. Enable auto-refresh */ 214 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 215 216 tmp = SDRAM_TREF/ns; 217 tmp = tmp/64 + 1; 218 if (tmp > 0xff) tmp = 0xff; 219 REG_EMC_RTCOR = tmp; 220 REG_EMC_RTCNT = 0; 221 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 222 223 /* Wait for number of auto-refresh cycles */ 224 tmp = (cpu_clk / 1000000) * 1000; 225 while (tmp--); 226 227 /* Stage 3. Mode Register Set */ 228 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 229 REG8(EMC_SDMR0|sdmode) = 0; 230 231 /* jz4730 additional measures */ 232 #ifdef CONFIG_CPU_JZ4730 233 REG8(EMC_SDMR1|sdmode) = 0; 234 #endif 235 236 /* Set back to basic DMCR value */ 237 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 238 239 /* everything is ok now */ 240 }